Device Having Semiconductor Body Comprising Selenium (se) Or Tellurium (te) (epo) Patents (Class 257/E21.068)
  • Patent number: 9029826
    Abstract: Erosion of chalcogenides in phase change memories using ovonic threshold switch selectors can be reduced by controlling columnar morphology in electrodes used in the ovonic threshold switch. The columnar morphology may cause cracks to occur which allow etchants used to etch the ovonic threshold switch to sneak through the ovonic threshold switch and to attack chalcogenides, either in the switch or in the memory element. In one embodiment, the electrode may be split into two metal nitride layers separated by an intervening metal layer.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Wei Chang, Jinwook Lee, Jong-Won Lee, Elijah V. Karpov
  • Patent number: 9012970
    Abstract: A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a contact interface level. A pair of pillars is comprised of an insulating material that extends below the contact interface level. Also, a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, forming a pair of pillars comprised of an insulating material and depositing a gate contact between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level and the insulating material extends below the contact interface level.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
  • Patent number: 9006700
    Abstract: A resistive memory device and a method for fabricating the resistive memory device. The memory device includes a first electrode and a resistive memory element in electrical contact. The memory device also includes a non-programmable stabilizer element in electrical and thermal contact with the resistive memory element. The stabilizer element has at least one physical dimension based on a physical characteristic of the resistive memory element such that the maximum resistance of the stabilizer element is substantially less than the maximum resistance of the resistive memory element.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, SangBum Kim, Chung H. Lam, Asit K. Ray, Norma E. Sosa Cortes
  • Patent number: 8993374
    Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Davide Erbetta, Luca Fumagalli
  • Patent number: 8993441
    Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyung Kim, Eun-Tae Kim, Sung-Lae Cho
  • Patent number: 8987037
    Abstract: A method of manufacturing a solar cell includes forming a buffer layer between an optical absorption layer and a window electrode layer. Forming the buffer layer includes depositing a metal material on the optical absorption layer, supplying a non-metal material on the optical absorption layer, supplying a gas material including oxygen atoms on the optical absorption layer, and reacting the metal material with the non-metal material. The gas material reacts with the metal material and the non-metal material to form a metal sulfur oxide on the optical absorption layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong-Duck Chung, Dae-Hyung Cho, Won Seok Han
  • Patent number: 8987792
    Abstract: Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jaroslaw Adamski, Chris Olson
  • Patent number: 8980679
    Abstract: Provided are apparatus and methods for forming phase change layers, and methods of manufacturing a phase change memory device. A source material is supplied to a reaction chamber, and purges from the chamber. A pressure of the chamber is varied according to the supply of the source material and the purge of the source material.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hyun Im, Byoungjae Bae, Dohyung Kim, Sunglae Cho, Jinil Lee, Juhyung Seo, Hyeyoung Park, Takehiko Fujita
  • Patent number: 8952349
    Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo
  • Patent number: 8933430
    Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: January 13, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ha Chang Jung, Gi A Lee
  • Patent number: 8932897
    Abstract: A phase change memory cell includes a first contact, a phase change region above and in contact with the first contact, an electrode region, and a second contact above and in contact with the electrode region. The phase change region surrounds the electrode region. The electrode region has a first surface in contact with the phase change region and a second surface in contact with the second contact, and the second surface is wider than the first surface.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huei Shen, Tsun Kai Tsao, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8916459
    Abstract: A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the carrier supply layer; ohmic source electrode and drain electrode formed on the cap layer; a recess formed by removing the cap layer between the source and drain electrodes, and exposing the carrier supply layer; an insulating film formed on the cap layer and retracted from an edge of the cap layer away from the recess; a gate electrode extending from the carrier supply layer in the recess to outside of the mesa; and air gap formed by removing side portion of the channel layer facing the gate electrode outside the mesa.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Takahashi, Kozo Makiyama
  • Patent number: 8916411
    Abstract: A gallium-containing alloy is formed on the light-receiving surface of a CIGS absorber layer, and, in conjunction with a subsequent selenization or anneal process, is converted to a gallium-rich region at the light-receiving surface of the CIGS absorber layer. A second gallium-rich region is formed at the back contact surface of the CIGS absorber layer during selenization, so that the CIGS absorber layer has a double-graded gallium concentration that increases toward the light-receiving surface and toward the back contact surface of the CIGS absorber layer. The double-graded gallium concentration advantageously produces a double-graded bandgap profile for the CIGS absorber layer.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: December 23, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Haifan Liang
  • Patent number: 8890230
    Abstract: A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness.
    Type: Grant
    Filed: July 15, 2012
    Date of Patent: November 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Hsu, Chi Ren, Tzeng-Fei Wen
  • Patent number: 8866194
    Abstract: A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a p+ diffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and having an effect as a potential barrier with respect to either electrons or holes.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shinya Naito, Hideaki Fujiwara, Toru Dan
  • Patent number: 8860111
    Abstract: An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: October 14, 2014
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Chung Hon Lam, Matthew J. Breitwisch
  • Patent number: 8852993
    Abstract: A gallium-containing alloy is formed on the light-receiving surface of a CIGS absorber layer, and, in conjunction with a subsequent selenization or anneal process, is converted to a gallium-rich region at the light-receiving surface of the CIGS absorber layer. A second gallium-rich region is formed at the back contact surface of the CIGS absorber layer during selenization, so that the CIGS absorber layer has a double-graded gallium concentration that increases toward the light-receiving surface and toward the back contact surface of the CIGS absorber layer. The double-graded gallium concentration advantageously produces a double-graded bandgap profile for the CIGS absorber layer.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Haifan Liang
  • Patent number: 8846442
    Abstract: The invention relates to a method for producing semiconductor layers and coated substrates treated with elemental selenium and/or sulphur, in particular flat substrates, containing at least one conducting, semiconducting and/or insulating layer, in which a substrate which is provided with at least one metal layer and/or with at least one layer containing metal, in particular a stack of substrates, each of which is provided with at least one metal layer and/or with at least one layer which contains metal, is inserted into a processing chamber and heated to a predetermined substrate temperature; elementary selenium and/or sulphur vapor is guided past on the or on every metal layer and/or layer containing metal, from a source located inside and/or outside the processing chamber, in particular by means of a carrier gas which is in particular inert, under rough vacuum conditions or ambient pressure conditions or overpressure conditions, in order to react chemically with said layer with selenium or sulphur in a tar
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: September 30, 2014
    Inventor: Volker Probst
  • Patent number: 8815632
    Abstract: A method of manufacturing an order vacancy compound (OVC) is provided. The method includes the following steps. A trivalent ion, a hexavalent ion and one of a univalent ion and a bivalent ion for an electrodeposition process are provided to form a solar energy absorbing film. The OVC is formed by performing an electrochemical etching process on the solar energy absorbing film.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 26, 2014
    Assignee: National Chen-Kung University
    Inventor: Wen-Hsi Lee
  • Patent number: 8772077
    Abstract: The present invention concerns a method of forming a chalcogenide thin film for a phase-change memory. In the method of forming a chalcogenide thin film according to the present invention, a substrate with a pattern formed is loaded into a reactor, and a source gas is supplied onto the substrate. Here, the source gas includes at least one source gas selected from germanium (Ge) source gas, gallium (Ga) source gas, indium (In) source gas, selenium (Se) source gas, antimony (Sb) source gas, tellurium (Te) source gas, tin (Sn) source gas, silver (Ag) source gas, and sulfur (S) source gas. A first purge gas is supplied onto the substrate in order to purge the source gas supplied onto the substrate, a reaction gas for reducing the source gas is then supplied onto the substrate, and a second purge gas is supplied onto the substrate in order to purge the reaction gas supplied onto the substrate.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: July 8, 2014
    Assignee: IPS Ltd.
    Inventors: Ki-Hoon Lee, Jung-Wook Lee, Dong-Ho You
  • Patent number: 8743599
    Abstract: A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Roger W. Cheek, Ming-Hsiu Lee
  • Patent number: 8728855
    Abstract: A method for processing a semiconductor assembly is presented. The method includes: (a) contacting at least a portion of a semiconductor assembly with a chalcogen source, wherein the semiconductor assembly comprises a semiconductor layer comprising a semiconductor material disposed on a support; (b) introducing a chalcogen from the chalcogen source into at least a portion of the semiconductor material; and (c) disposing a window layer on the semiconductor layer after the step (b).
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 20, 2014
    Assignee: First Solar, Inc.
    Inventors: Bastiaan Arie Korevaar, Faisal Razi Ahmad
  • Patent number: 8722455
    Abstract: The present invention discloses a phase change memory structure having low-k dielectric heat-insulating material and fabrication method thereof, wherein the phase change memory cell comprises diode, heating electrode, reversible phase change resistor, top electrode and etc; the heating electrode and reversible phase change resistor are surrounded by low-k dielectric heat-insulating layer; an anti-diffusion dielectric layer is designed between the reversible phase change resistor and the low-k dielectric heat-insulating layer surrounding thereof. The present invention utilizes low-k dielectric material as heat-insulating material, thereby avoiding thermal crosstalk and mutual influence during operation between phase change memory cells, enhancing the reliability of devices, and eliminating the influence of temperature, pressure and etc. on phase change random access memory (PCRAM) data retention during the change from amorphous to polycrystalline states.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: May 13, 2014
    Assignee: Chinese Academy of Sciences
    Inventors: Zhitang Song, Liangcai Wu, Songlin Feng
  • Patent number: 8710567
    Abstract: The semiconductor device of the present invention includes a silicon substrate having a logic region and a RAM region, an NMOS transistor formed in the logic region, and an NMOS transistor formed in the RAM region. The NMOS transistor has a stack structure obtained by sequentially stacking the gate insulating film and the metal gate electrode over the silicon substrate. The NMOS transistor has a cap film containing an element selected from a group consisting of lanthanum, ytterbium, magnesium, strontium, and erbium as a composition element between the silicon substrate and metal gate electrode. The cap film is not formed in the NMOS transistor.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tomohiko Moriya
  • Patent number: 8709863
    Abstract: Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: April 29, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: William Hunks, Tianniu Chen, Chongying Xu, Jeffrey F. Roeder, Thomas H. Baum, Matthias Stender, Philip S. H. Chen, Gregory T. Stauf, Bryan C. Hendrix
  • Patent number: 8697486
    Abstract: A method of forming a phase change material which having germanium and tellurium therein includes depositing a germanium-containing material over a substrate. Such material includes elemental-form germanium. A gaseous tellurium-comprising precursor is flowed to the germanium-comprising material and tellurium is removed from the gaseous precursor to react with the elemental-form germanium in the germanium-comprising material to form a germanium and tellurium-comprising compound of a phase change material over the substrate. Other implementations are disclosed.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: April 15, 2014
    Assignee: Micro Technology, Inc.
    Inventors: Eugene P. Marsh, Timothy A. Quick, Stefan Uhlenbrock
  • Patent number: 8698277
    Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamauchi, Shosuke Fujii, Reika Ichihara
  • Patent number: 8685785
    Abstract: A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, John P. Karidis
  • Patent number: 8685783
    Abstract: On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huei Shen, Tsun Kai Tsao, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8680499
    Abstract: Some embodiments include memory cells which contain chalcogenide material having germanium in combination with one or both of antimony and tellurium. An atomic percentage of the germanium within the chalcogenide material is greater than 50%; and may be, for example, within a range of from greater than or equal to about 52% to less than or equal to about 78%. In some embodiments, the memory cell has a top electrode over the chalcogenide material, a heater element under and directly against the chalcogenide material, and a bottom electrode beneath the heater element. The heater element may be L-shaped, with the L-shape having a vertical pillar region joining with a horizontal leg region. A bottom surface of the horizontal leg region may be directly against the bottom electrode, and a top surface of the vertical pillar region may be directly against the chalcogenide material.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Davide Erbetta, Luca Fumagalli, Innocenzo Tortorelli, Enrico Varesi
  • Patent number: 8673717
    Abstract: A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes forming pillars with a doped silicon region on the substrate. An electrically conductive gate material is deposited between and over the pillars. The gate material is etched such that the gate material partially fills a space between the pillars. The pillars are then etched such that a pair of pillars from the pillars include an insulating material over the doped silicon region. A gate contact is deposited between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level, and the insulating material extends below the contact interface level.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
  • Patent number: 8674127
    Abstract: Precursors for use in depositing antimony-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of A Ge2Sb2Te5 chalcogenide thin films in the manufacture of nonvolatile Phase Change Memory (PCM) or for the manufacturing of thermoelectric devices, by deposition techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: March 18, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Tianniu Chen, William Hunks, Philip S. H. Chen, Chongying Xu, Leah Maylott
  • Patent number: 8664033
    Abstract: A gallium-containing alloy is formed on the light-receiving surface of a CIGS absorber layer, and, in conjunction with a subsequent selenization or anneal process, is converted to a gallium-rich region at the light-receiving surface of the CIGS absorber layer. A second gallium-rich region is formed at the back contact surface of the CIGS absorber layer during selenization, so that the CIGS absorber layer has a double-graded gallium concentration that increases toward the light-receiving surface and toward the back contact surface of the CIGS absorber layer. The double-graded gallium concentration advantageously produces a double-graded bandgap profile for the CIGS absorber layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Haifan Liang
  • Patent number: 8653616
    Abstract: It is aimed to provide a photoelectric conversion device having high adhesion between a first semiconductor layer and an electrode layer as well as high photoelectric conversion efficiency. A photoelectric conversion device comprises an electrode layer, a first semiconductor layer located on the electrode layer and comprising a chalcopyrite-based compound semiconductor of group I-III-VI and oxygen, and a second semiconductor layer located on the first semiconductor layer and forming a pn junction with the first semiconductor layer. In the photoelectric conversion device, the first semiconductor layer has a higher molar concentration of oxygen in a part located on the electrode layer side with respect to a center portion in a lamination direction of the first semiconductor layer than a molar concentration of oxygen in the whole of the first semiconductor layer.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: February 18, 2014
    Assignee: KYOCERA Corporation
    Inventors: Rui Kamada, Shuichi Kasai
  • Patent number: 8629034
    Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: January 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Laurent Breuil, Franz Schuler, Georg Tempel
  • Patent number: 8614135
    Abstract: A phase change memory is manufactured by providing a substrate including a layer of phase-change material, forming a damascene pattern on the layer of phase-change material, and forming both a top electrode and a bit line in the damascene pattern.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: December 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ho Eun, JaeHee Oh
  • Patent number: 8597978
    Abstract: A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 3, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kurt Wachtler, Margaret Rose Simmons-Matthews
  • Patent number: 8592979
    Abstract: A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hei-Seung Kim, Gil-Heyun Choi, Ji-Soon Park, Jong-Myeong Lee
  • Patent number: 8586401
    Abstract: A solar cell manufacturing method includes forming a first electrode on a substrate, forming a mixed metal layer on the first electrode, forming a light absorbing layer by injecting hydrogen selenide on the entire surface of the mixed metal layer using a gas injection device, and forming a second electrode on the light absorbing layer. Further, the gas injection device includes a gas pipeline, an inner gas pipe positioned in the gas pipeline and having an opening, and a plurality of injection nozzles disposed below the gas pipeline.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: November 19, 2013
    Assignees: Samsung SDI Co., Ltd., Samsung Display Co., Ltd.
    Inventors: Seoung-Jin Seo, Jung-Gyu Nam, Sang-Cheol Park, Woo-Su Lee, Seong-Ryong Hwang, In-Ki Kim
  • Patent number: 8580602
    Abstract: A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: November 12, 2013
    Assignee: Uriel Solar, Inc.
    Inventor: James David Garnett
  • Patent number: 8563353
    Abstract: Described herein is a method and liquid-based precursor composition for depositing a multicomponent film. In one embodiment, the method and compositions described herein are used to deposit Germanium Tellurium (GeTe), Antimony Tellurium (SbTe), Antimony Germanium (SbGe), Germanium Antimony Tellurium (GST), Indium Antimony Tellurium (IST), Silver Indium Antimony Tellurium (AIST), Cadmium Telluride (CdTe), Cadmium Selenide (CdSe), Zinc Telluride (ZnTe), Zinc Selenide (ZnSe), Copper indium gallium selenide (CIGS) films or other tellurium and selenium based metal compounds for phase change memory and photovoltaic devices.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: October 22, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Liu Yang, Xinjian Lei, Iain Buchanan
  • Patent number: 8563088
    Abstract: A method for preparing a Group 1a-1b-3a-6a material using a selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 22, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Kevin Calzia, David Mosley, David L. Thorsen, Charles R. Szmanda
  • Patent number: 8507887
    Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 13, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sonehara, Nobuaki Yasutake
  • Publication number: 20130193401
    Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
  • Patent number: 8481355
    Abstract: A system and associated process for vapor deposition of a thin film layer on a photovoltaic (PV) module substrate is includes establishing a vacuum chamber and introducing the substrates individually into the vacuum chamber. A conveyor system is operably disposed within the vacuum chamber and is configured for conveying the substrates in a serial arrangement through a vapor deposition apparatus within the vacuum chamber at a controlled constant linear speed. A post-heat section is disposed within the vacuum chamber immediately downstream of the vapor deposition apparatus in the conveyance direction of the substrates. The post-heat section is configured to maintain the substrates conveyed from the vapor deposition apparatus in a desired heated temperature profile until the entire substrate has exited the vapor deposition apparatus.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: July 9, 2013
    Assignee: Primestar Solar, Inc.
    Inventors: Mark Jeffrey Pavol, Russell Weldon Black, Brian Robert Murphy, Christopher Rathweg, Edwin Jackson Little, Max William Reed
  • Publication number: 20130141967
    Abstract: A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an SbmSen material layer (where m and n are positive numbers, respectively) interposed between the first electrode and the second electrode. The SbmSen material layer includes a separation structure in which a plurality of Sb atoms are in contact with a plurality of Se atoms.
    Type: Application
    Filed: May 30, 2012
    Publication date: June 6, 2013
    Inventors: Mann Ho CHO, Ju Heyuck Baeck, Tae Hyeon Kim, Hye Jin Choi
  • Patent number: 8445313
    Abstract: A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 21, 2013
    Assignees: International Business Machines Corporatoin, Macronix International Co., Ltd.
    Inventors: Matthew J. Breitwisch, Chieh-Fang Chen, Shih-Hung Chen, Eric A. Joseph, Chung Hon Lam, Michael F. Lofaro, Hsiang-Lan Lung, Alejandro G. Schrott, Min Yang
  • Patent number: 8440991
    Abstract: A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: May 14, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae Chan Park, Se Ho Lee
  • Publication number: 20130075682
    Abstract: A phase change random access memory includes a semiconductor substrate having a bottom electrode formed over the semiconductor substrate; and a phase change layer formed over the bottom electrode. The phase change layer a first phase change layer formed over the bottom electrode and including at least one of a first element, a second element, and a third element; and a second phase change layer formed over a surface of the first phase change layer and formed of the first element to prevent an area of the first phase change layer from increasing through diffusion.
    Type: Application
    Filed: December 20, 2011
    Publication date: March 28, 2013
    Inventor: Keun LEE
  • Patent number: RE45356
    Abstract: Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide SbxSe100-x phase-change material layer contacting a heat-generating electrode layer exposed through a pore and filling the pore. Due to the use of SbxSe100-x in the phase-change material layer, a higher-speed, lower-power consumption phase-change memory device than a GST memory device can be manufactured.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Min Yoon, Nam Yeal Lee, Sang Ouk Ryu, Seung Yun Lee, Young Sam Park, Kyu Jeong Choi, Byoung Gon Yu