Abstract: A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms.

Abstract: A solution of a hydrazine-based precursor of a metal chalcogenide is prepared by adding an elemental metal and an elemental chalcogen to a hydrazine compound. The precursor solution can be used to form a film. The precursor solutions can be used in preparing field-effect transistors, photovoltaic devices and phase-change memory devices.

Abstract: One embodiment provides a non-volatile semiconductor memory with CBRAM memory cells at which there exists, between the Ag-doped GeSe layer and the Ag top electrode, a chemically inert barrier layer improving the switching properties of the CBRAM memory cell. The active matrix material layer of the memory cell includes a GeSe/Ge:H double layer with a vitreous GeSe layer and an amorphous Ge:H layer. The amorphous Ge:H layer is positioned between the GeSe layer and the second electrode. Thus, the forming of AgSe conglomerates in the Ag doping and/or electrode layer is inhibited, so that precipitations are prevented and a homogeneous deposition of the silver doping layer is enabled. By means of the GeSe/Ge:H double layer system, the resistive non-volatile storage effect of the CBRAM memory cell is, on the one hand, preserved and, on the other hand, the chemical stability of the top electrode positioned thereabove is ensured by means of the thin Ge:H layer.

Abstract: A programmable resistor memory, such as a phase change memory, with a memory element comprising narrow vertical side wall active pins is described. The side wall active pins comprise a programmable resistive material, such as a phase change material. In a first aspect of the invention, a method of forming a memory cell is described which comprises forming a stack comprising a first electrode having a principal surface with a perimeter, an insulating layer overlying a portion of the principal surface of the first electrode, and a second electrode vertically separated from the first electrode and overlying the insulating layer. Side walls on the insulating layer and on the second electrode are positioned over the principle surface of the first electrode with a lateral offset from the perimeter of the first electrode.

Abstract: A method and system to modify a surface composition of thin film Group IBIIIA VIA solar cell absorbers having non-uniformly distributed Group IIIA materials or graded materials, such as Indium (In), gallium (Ga) and aluminum (Al). The graded materials distribution varies between the surface and the bottom of the absorber layer such that a molar ratio of (Ga+Al)/(Ga+Al+In) is the highest at the bottom of the absorber layer and the lowest at the surface of the absorber. Within the bulk of the absorber, the molar ratio gradually changes between the bottom and the surface of the absorber. In one embodiment, the surface composition of a graded absorber layer may be modified by removing a top portion or slice of the absorber layer, where the molar ratio is low so as to expose the inner portions of the absorber layer having a higher molar ratio of graded materials.

Abstract: A three dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.

Abstract: A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first surface coupled to a second surface of said resistivity interfacial layer, and a second electrode coupled to a second surface of said resistance changing material.

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

Abstract: To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.

Abstract: In a memory device, at least one conductive contact having a width of less than, or equal to, about 30 nm may be formed on a first electrode. A dielectric layer may be formed on the sides of the at least one conductive contact, and a phase change material film may be formed on the conductive contact. A second electrode may be formed on the phase change material.

Abstract: Disclosed are a phase-change memory device and its manufacturing method, which can reduce a contact area between a bottom electrode and a phase-change layer, thereby reducing the quantity of current necessary for phase change. The phase-change memory device comprises: a bottom electrode formed on a contact plug; a phase-change layer formed on the bottom electrode and having a shape of a character ‘?’; and a top electrode formed on the phase-change layer.

Abstract: A memory cell includes a memory cell layer over a memory cell access layer. The memory cell access layer comprises a bottom electrode. The memory cell layer comprises a dielectric layer and a side electrode at least partially defining a void with a memory element therein. The memory element comprises a memory material switchable between electrical property states by the application of energy. The memory element is in electrical contact with the side electrode and with the bottom electrode. In some examples the memory element has a pillar shape with a generally constant lateral dimension with the side electrode and the dielectric layer surrounding and in contact with first and second portions of the memory element.

Abstract: An intermediate electrode between an ovonic threshold switch and a memory element may be formed in the same pore with the memory element. This may have many advantages including, in some embodiments, reducing leakage.

Abstract: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.

Abstract: Provided is a thin film transistor (TFT) which uses CIS (CuInSe2), including Se, which is a chalcogen-based material, and can provide a rectifying function, and electric and optical switching functions of a diode. The TFT according to the present invention includes, a substrate, a gate electrode formed on a portion of the substrate, an insulating layer covering the substrate and a gate electrode, a plurality of CIS (CuInSe2) films formed on the insulating layer so as to cover the region where the gate electrode is formed; and source/drain regions separated from each other so as to comprise a trench exposing a portion of a surface of the CIS films.

Abstract: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method.

Abstract: Graded core/shell semiconductor nanorods and shaped nanorods are disclosed comprising Group II-VI, Group III-V and Group IV semiconductors and methods of making the same. Also disclosed are nanorod barcodes using core/shell nanorods where the core is a semiconductor or metal material, and with or without a shell. Methods of labeling analytes using the nanorod barcodes are also disclosed.

Abstract: A method of making an electrically programmable memory element, comprising: providing a first dielectric layer; forming a conductive material over the first dielectric layer; forming a second dielectric layer over the conductive material; and forming a programmable resistance material in electrical contact with a peripheral surface of the conductive material.

Abstract: A memory cell comprises a lower electrode, a phase change feature, a spacer feature, and a dielectric layer. The lower electrode comprises a first surface region as well as a second surface region that is raised in relation to the first surface region. The phase change feature is disposed on the second surface region of the lower electrode and has one or more sidewalls. The spacer feature is also disposed on the second surface region of the lower electrode and against the one or more sidewalls of the phase change feature. The dielectric layer is formed at least partially on top of the first surface region of the lower electrode and abutting the spacer feature.

Abstract: A memory cell comprises a first electrode, a second electrode and a composite material. The composite material electrically couples the first electrode to the second electrode. Moreover, the composite material comprises a phase change material and a resistor material. At least a portion of the phase change material is operative to switch between a substantially crystalline phase and a substantially amorphous phase in response to an application of a switching signal to at least one of the first and second electrodes. In addition, the resistor material has a resistivity lower than that of the phase change material when the phase change material is in the substantially amorphous phase.

Abstract: A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension and is electrically coupled between a second electrode and the first thin film spacer. In this regard, the phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.

Abstract: A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. The bottom electrode can also be tapered to have a smaller cross-sectional area at the top of the bottom electrode than at the bottom of the bottom electrode.

Abstract: A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one layer of resistance variable material and a second, second electrode is in contact with a second portion of the at least one layer of resistance variable material.

Abstract: An HBT structure and manufacturing method thereof, in which the HBT structure includes an emitter, an intrinsic base, a collector, an insulating sidewall, and a stress-inducting base formed by selective epitaxial growth to locally induce a stress to the HBT structure. Compressive or tensile stress is additionally induced from outside to modify physical and electric properties of a semiconductor layer, thereby improving the performance of the transistor.

Abstract: The present invention advantageously provides for, in different embodiments, low-cost deposition techniques to form high-quality, dense, well-adhering Group IBIIIAVIA compound thin films with macro-scale as well as micro-scale compositional uniformities. In one embodiment, there is provided a method of growing a Group IBIIIAVIA semiconductor layer on a base, and includes the steps of depositing on the base a film of Group IB material and at least one layer of Group IIIA material, intermixing the film of Group IB material and the at least one layer of Group IIIA material to form an intermixed layer, and forming over the intermixed layer a metallic film comprising at least one of a Group IIIA material sub-layer and a Group IB material sub-layer. Other embodiments are also described.

Abstract: The present invention provides metal precursors for low temperature deposition. The metal precursors include a metal ring compound including at least one metal as one of a plurality of elements forming a ring. Methods of forming a metal thin layer and manufacturing a phase change memory device including use of the metal precursors is also provided.

Abstract: A phase change memory including a phase change layer, a first electrode, and a porous dielectric layer formed with a plurality of pores. The porous dielectric layer is formed between the phase change layer and the first electrode. Therefore, the phase change layer may make contact with the first electrode thorough the pores thereby decreasing the contact areas of the phase change layer and the first electrode.

Abstract: A vertical elevated pore structure for a phase change memory may include a pore with a lower electrode beneath the pore contacting the phase change material in the pore. The lower electrode may be made up of a higher resistivity lower electrode and a lower resistivity lower electrode underneath the higher resistivity lower electrode. As a result, more uniform heating of the phase change material may be achieved in some embodiments and better contact may be made in some cases.

Abstract: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

Abstract: A phase change memory includes a sidewall insulation film and a heater electrode which are formed in a contact hole formed in an interlayer insulation film on a lower electrode. The heater electrode has a recessed structure. In a recessed area surrounded by the sidewall insulation film, the heater electrode and a phase change film are contacted with each other. A phase change region is formed only in an area contacted with the sidewall insulation film. The sidewall insulation film is an anti-oxidizing insulation film. The phase change region and the heater electrode which are heated to a high temperature upon rewriting are not contacted with the interlayer insulation film as an oxidizing insulation film.

Abstract: A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member.

Abstract: A method is describe for fabricating memory components including memory cells based on an active material of an active layer, the phase state of which can be changed and which is enclosed between a bottom electrode and a top electrode. To reduce the current intensity of the programming current and the erase current required for programming and erasing of the memory element and therefore the quantity of heat which is required to change the phase state, a nanoporous aluminium oxide layer is used as a mask during the production of the active layer or the interface with the electrodes. The nanoporous aluminium oxide layer can be used as a positive mask, as a negative mask, or used directly as an insulating current aperture. The contact surface between electrode and active layer can be set in virtually any desired form by varying the process parameters of the aluminium oxide mask.

Abstract: Both a chalcogenide select device (24, 120) and a chalcogenide memory element (40, 130) are formed within vias within dielectrics (18, 22). As a result, the chalcogenides is effectively trapped within the vias and no glue or adhesion layer is needed. Moreover, delamination problems are avoided. A lance material (30) is formed within the same via (31) with the memory element (40, 130). In one embodiment, the lance material is made thinner by virtue of the presence of a sidewall spacer (28); in another embodiment no sidewall spacer is utilized. A relatively small area of contact between the chalcogenide (40) used to form a memory element (130) and the lance material (30) is achieved by providing a pin hole opening in a dielectric (34), which separates the chalcogenide and the lance material.

Abstract: Example embodiments may provide a doped phase change layer and a method of operating and fabricating a phase change memory with the example embodiment doped phase change layer. The phase change memory may include a storage node having a phase change layer and a switching device, wherein the phase change layer includes indium with a concentration ranging from about 5 at % to about 15 at %. The phase change layer may be a GST layer that includes indium. The phase change layer may be a GST layer that includes gallium.

Abstract: A phase change memory may be formed to have a dimension that is sub-lithographic in one embodiment by forming a surface feature over the phase change material, and coating the surface feature with a mask of sub-lithographic dimensions. The horizontal portions of the mask and the surface feature may then be removed and the remaining portions of the mask may be used to define a dimension of said phase change material. Another dimension of the phase change material may be defined using an upper electrode extending over said phase change material as a mask to etch the phase change material.

Abstract: An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements.

Abstract: Provided is a process for preparing an absorption layer of a solar cell composed of a 1B-3A-Se compound, comprising applying a metal selenide nanoparticle as a precursor material to a base material and subjecting the applied nanoparticle to thermal processing, whereby the crystal size of the 1B-3A-Se compound can be increased as compared to a conventional method using a metal in the form of an oxide as a precursor material, consequently resulting in an enhanced efficiency of the solar cell, and the manufacturing process can be simplified with omission of hydrogen reduction and selenidation processes.

Abstract: A method of forming a diode structure for a phase-change data storage array, having multiple thin film layers adapted to form a plurality of data storage cell diodes is disclosed. The method includes depositing a first diode layer of CuInSe material on a substrate and depositing a second diode layer of phase-change material on the first diode layer.