Abstract: Semiconductor materials suitable for being used in radiation detectors are disclosed. A particular example of the semiconductor materials includes tellurium, cadmium, and zinc. Tellurium is in molar excess of cadmium and zinc. The example also includes aluminum having a concentration of about 10 to about 20,000 atomic parts per billion and erbium having a concentration of at least 10,000 atomic parts per billion.

Abstract: A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.

Abstract: An absorber layer of a photovoltaic device may be formed on an aluminum or metallized polymer foil substrate. A nascent absorber layer containing one or more elements of group IB and one or more elements of group IIIA is formed on the substrate. The nascent absorber layer and/or substrate is then rapidly heated from an ambient temperature to an average plateau temperature range of between about 200° C. and about 600° C. and maintained in the average plateau temperature range 2 to 30 minutes after which the temperature is reduced.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films.

Abstract: Briefly, in accordance with an embodiment of the invention, a memory and a method to manufacture the memory is provided. The memory may include a phase change material over a substrate. The memory may further include a switching material coupled to the phase change material, wherein the switching material comprises a chalcogen other than oxygen and wherein the switching material and the phase change material form portions of a vertical structure over the substrate.

Abstract: A slurry composition for chemical mechanical polishing (CMP) of a phase-change memory device is provided. The slurry composition comprises deionized water and iron or an iron compound. The slurry composition can achieve high polishing rate on a phase-change memory device and improved polishing selectivity between a phase-change memory material and a polish stop layer (e.g., a silicon oxide film), can minimize the occurrence of processing imperfections (e.g., dishing and erosion), and can lower the etch rate on a phase-change memory material to provide a high-quality polished surface. Further provided is a method for polishing a phase-change memory device using the slurry composition.

Abstract: A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.

Abstract: A memory cell for use in integrated circuits comprises a chalcogenide feature and a transition metal oxide feature. Both the chalcogenide feature and transition metal oxide feature each have at least two stable electrical resistance states. At least two bits of data can be concurrently stored in the memory cell by placing the chalcogenide feature into one of its stable electrical resistance states and by placing the transition metal oxide feature into one of its stable electrical resistance states.

Abstract: A contact structure for a PCM device is formed by an elongated formation having a longitudinal extension parallel to the upper surface of the body and an end face extending in a vertical plane. The end face is in contact with a bottom portion of an active region of chalcogenic material so that the dimensions of the contact area defined by the end face are determined by the thickness of the elongated formation and by the width thereof.

Abstract: The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode.

Abstract: A phase change memory device includes switching elements formed on a substrate that includes a cell region and a peripheral region. Heat sinks are formed on the switching elements. Heaters are formed on the heat sink and a phase change layer is formed on the heaters.

Abstract: A multi-layer, phase change material (PCM) memory apparatus includes a plurality of semiconductor layers sequentially formed over a base substrate, wherein each layer comprises an array of memory cells formed therein, each memory cell further including a PCM element, a first diode serving as a heater diode in thermal proximity to the PCM element and configured to program the PCM element to one of a low resistance crystalline state and a high resistance amorphous state, and a second diode serving a sense diode for a current path used in reading the state of the PCM element; the base substrate further including decoding, programming and sensing circuitry formed therein, with each of the plurality of semiconductor layers spaced by an insulating layer; and intralayer wiring for communication between the base substrate circuitry and the array of memory cells in each of the semiconductor layers.

Abstract: Disclosed herein are tellurium metal-organic precursors and methods for depositing tellurium-containing films on a substrate.

Abstract: A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the substrate to expose the first sidewall and a second sidewall of the dielectric pattern, wherein the electric conductive patterns covering the same dielectric pattern are apart from each other; a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the dielectric patterns, wherein the two adjacent electric conductive patterns covering the same dielectric pattern are electrically connected by the phase change spacer; and a dielectric layer formed on the substrate.

Abstract: An inorganic nanocomposite is prepared by obtaining a solution of a soluble hydrazine-based metal chalcogenide precursor; dispersing a nanoentity in the precursor solution; applying a solution of the precursor containing the nanoentity onto a substrate to produce a film of the precursor containing the nanoentity; and annealing the film of the precursor containing the nanoentity to produce the metal chalcogenide nanocomposite film comprising at least one metal chalcogenide and at least one molecularly-intermixed nanoentity on the substrate. The process can be used to prepare field-effect transistors and photovoltaic devices.

Abstract: An electrically rewritable non-volatile memory device is configured by the EEPROM 3, and an electrically non-rewritable non-volatile memory device is configured by the OTPROM 4a. Both the EEPROM 3 and the OTPROM 4a are configured by phase change memory devices each of which can be fabricated in the same fabrication step and at a low cost. The EEPROM3 uses a phase change memory device in which an amorphous state and a crystal state of a phase change material are used for memory information, while the OTPROM 4a uses a phase change memory device in which a non-disconnection state and a disconnection state of a phase change material are used for memory information.

Abstract: Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.

Abstract: A phase-change memory device includes a first insulator having a hole therethrough, a first electrode that conforms at least partially to the hole, a phase-change material in electrical communication with the first electrode, and a second electrode in electrical communication with the phase-change material. When current is passed from the first electrode to the second electrode through the phase-change material, at least one of the first and second electrodes remains unreactive with the phase change material.

Abstract: An integrated circuit includes a first electrode including an inner portion and an outer portion laterally surrounding the inner portion. The outer portion has a greater resistivity than the inner portion. The integrated circuit includes a second electrode and resistivity changing material contacting the first electrode and coupled to the second electrode.

Abstract: A method and memory cell including self-converged bottom electrode ring. The method includes forming a step spacer, a top insulating layer, an intermediate insulating layer, and a bottom insulating layer above a substrate. The method includes forming a step spacer within the top insulating layer and the intermediate insulating layer. The step spacer size is easily controlled. The method also includes forming a passage in the bottom insulating layer with the step spacer as a mask. The method includes forming bottom electrode ring within the passage comprising a cup-shaped outer conductive layer within the passage and forming an inner insulating layer within the cup-shaped outer conductive layer. The method including forming a phase change layer above the bottom electrode ring and a top electrode above the bottom electrode ring.

Abstract: A method for manufacturing a thin film solar cell involves applying an inductively-coupled-plasma during the deposition of selenium. A precursor thin film is formed. The precursor thin film can include copper, indium, and gallium. The inductively-coupled-plasma is applied to the selenium as the selenium is deposited into the precursor thin film to produce the thin film. The selenium is deposited into precursor thin film by evaporation, sputtering, or using a reactive gas. An inert gas is used as a carry and discharge gas. The precursor thin film and the selenium are deposited using a deposition system. The deposition system includes an inductively-coupled-plasma device. The inductively-coupled-plasma device includes a quartz plate, a plasma discharge coil, and an inlet system. The deposition can be an in-line system, a roll-to-roll system, or a hybrid system.

Abstract: A multi-layer storage node, resistive random access memory device and methods of manufacturing the same are provided. The resistive random access memory device includes a switching structure and a storage node connected to the switching structure. The storage node includes a lower electrode, a first layer, a second layer, and an upper electrode that may be sequentially stacked. The first layer may be formed on the lower electrode and includes at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te) and combinations thereof. The second layer may be formed on the first layer and includes at least one of copper (Cu), silver (Ag) and combinations thereof. The second layer may be formed of a material having an oxidizing power less than that of the first layer. The upper electrode may be formed on the second layer.

Abstract: A phase change memory device and a method of fabricating the same are provided. A phase change material layer of the phase change memory device is formed of germanium (Ge)-antimony (Sb)-Tellurium (Te)-based Ge2Sb2+xTe5 (0.12?x?0.32), so that the crystalline state is determined as a stable single phase, not a mixed phase of a metastable phase and a stable phase, in phase transition between crystalline and amorphous states of a phase change material, and the phase transition according to increasing temperature directly transitions to the single stable phase from the amorphous state. As a result, set operation stability and distribution characteristics of set state resistances of the phase change memory device can be significantly enhanced, and an amorphous resistance can be maintained for a long time at a high temperature, i.e., around crystallization temperature, and thus reset operation stability and rewrite operation stability of the phase change memory device can be significantly enhanced.

Abstract: The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.

Abstract: In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.

Abstract: In a method of forming a phase-change memory device, a variable resistance member may be formed on a s semiconductor substrate having a contact region, and a first electrode may be formed to contact a first portion of the variable resistance member and to be electrically connected to the contact region. A second electrode may be formed so as to contact a second portion of the variable resistance member.

Abstract: A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a width and an exposed length of a bottom electrode. The method allows the formation of very small phase-change memory cells.

Abstract: A method for depositing a germanium containing film on a substrate is disclosed. A reactor, and at least one substrate disposed in the reactor, are provided. A germanium containing precursor is provided and introduced into the reactor, which is maintained at a temperature of at least 100° C. Germanium is deposited onto the substrate through a deposition process to form a thin film on the substrate.

Abstract: A non-volatile memory including a diode and a memory cell is described. The diode includes a doped region, a metal silicide layer, and a patterned doped semiconductor layer. The doped region of a first conductive type is formed in a substrate. The metal silicide layer is formed on the substrate. The patterned doped semiconductor layer of a second conductive type is formed on the metal silicide layer. The memory cell is formed on the substrate and coupled with the diode.

Abstract: A method for forming a Phase Change Material (PCM) cell structure comprises forming both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM is protected from damage by a conductive encapsulating layer. Electrical isolation between adjacent cells is provided by modifying the conductivity of both the PCM layer and the conductive encapsulating upper electrode layer subsequent to deposition thereof, thereby forming high electrical resistance regions between the cells.

Abstract: The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.

Abstract: Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide SbxSe100-x phase-change material layer contacting a heat-generating electrode layer exposed through a pore and filling the pore. Due to the use of SbxSe100-x in the phase-change material layer, a higher-speed, lower-power consumption phase-change memory device than a GST memory device can be manufactured.

Abstract: The present invention provides a doped homojunction chalcogenide thin film transistor and a method of fabricating the same, comprising forming an N-type chalcogenide layer constituting a channel layer on a substrate, forming and patterning a diffusion prevention layer on the upper part of the N-type chalcogenide layer, and forming a P-type chalcogenide layer constituting source and drain regions by depositing and diffusing Te alloy on the N-type chalcogenide layer. With the present invention, a thin film transistor can be fabricated using chalcogenide material having N-type conductivity and chalcogenide material having P-type conductivity.

Abstract: A memory device as described herein includes a memory member contacting first and second interface structures. The first interface structure electrically and thermally couples the memory member to access circuitry and has a first thermal impedance therebetween. The second interface structure electrically and thermally couples the memory member to a bit line structure and has a second thermal impedance therebetween. The first and second thermal impedances are essentially equal such that applying a reset pulse results in a phase transition of an active region of the memory member spaced away from both the first and second interface structures.

Abstract: Tellurium (Te)-containing precursors, Te containing chalcogenide phase change materials are disclosed in the specification. A method of making Te containing chalcogenide phase change materials using ALD, CVD or cyclic CVD process is also disclosed in the specification in which at least one of the disclosed tellurium (Te)-containing precursors is introduced to the process.

Abstract: A semiconductor device having a metal insulator semiconductor field effect transistor (MISFET) with interface resistance-reduced source/drain electrodes is disclosed. This device includes a p-type MISFET formed on a semiconductor substrate. The p-MISFET has a channel region in the substrate, a gate insulating film on the channel region, a gate electrode on the gate insulating film, and a pair of laterally spaced-apart source and drain electrodes on both sides of the channel region. These source/drain electrodes are each formed of a nickel (Ni)-containing silicide layer. The p-MISFET further includes an interface layer which is formed on the substrate side of an interface between the substrate and each source/drain electrode. This interface layer contains magnesium (Mg), calcium (Ca) or barium (Ba) therein. A fabrication method of the semiconductor device is also disclosed.

Abstract: A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° C. with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming GST phase change memory films on substrates.

Abstract: A solution of a hydrazine-based precursor of a metal chalcogenide is prepared by adding an elemental metal and an elemental chalcogen to a hydrazine compound. The precursor solution can be used to form a film. The precursor solutions can be used in preparing field-effect transistors, photovoltaic devices and phase-change memory devices.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.

Abstract: A processing method described herein provides a method of patterning a MoSe2 and/or Mo material, for example a layer of such material(s) in a thin-film structure. According to one aspect, the invention relates to etch solutions that can effectively etch through Mo and/or MoSe2. According to another aspect, the invention relates to etching such materials when such materials are processed with other materials in a thin film photovoltaic device. According to other aspects, the invention includes a process of etching Mo and/or MoSe2 with selectivity to a layer of CIGS material in an overall process flow. According to still further aspects, the invention relates to Mo and/or MoSe2 etch solutions that are useful in an overall photolithographic process for forming a photovoltaic cell and/or interconnects and test structures in a photovoltaic device.

Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed.

Abstract: The invention relates to a process for manufacturing a plurality of CBRAM memories, each comprising a memory cell in a chalcogenide solid electrolyte, an anode, and a cathode, the process comprising implementing a sublayer of a high thermal conductivity material, higher than 1.3 W/m/K, which covers the set of contacts, then providing, on said sublayer, a triple layer comprising a chalcogenide layer, then an anodic layer, and a layer with second contacts (36), and finally an etching step.

Abstract: Provided is a method of depositing a chalcogenide film for phase-change memory. When the chalcogenide film for phase-change memory is deposited through a method using plasma such as plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD), a plasma reaction gas including He is used such that the crystallinity of the chalcogenide film is adjusted and the grain size and morphology of the deposited film are adjusted.

Abstract: A method for manufacturing a memory device comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures. The electrode layer includes a first electrode and a second electrode, and an insulating member between the first and second electrodes for each phase change memory cell to be formed. A bridge of memory material is formed on the top surface of the electrode layer across the insulating member for each memory cell to be formed. An access structure over the electrode layer is made by forming a patterned conductive layer over said bridge, and forming a contact between said first electrode and said patterned conductive layer.

Abstract: A memory cell device, including a memory material element switchable between electrical property states by the application of energy, includes depositing an electrical conductor layer, depositing dielectric material layers and etching to create a first electrode and voids. A memory material is applied into a void to create a memory material element in contact with the first electrode. A second electrode is created to contact the memory material element.

Abstract: A thin film solar cell including a Group IBIIIAVIA absorber layer on a defect free base including a stainless steel substrate is provided. The stainless steel substrate of the base is surface treated to reduce the surface roughness such as protrusions that cause shunts. In one embodiment, the surface roughness is reduced by coating surface with a thin silicon dioxide which fills the cavities and recesses around the protrusions and thereby reducing the surface roughness. After the silicon dioxide film is formed, a contact layer is formed over the ruthenium layer and the exposed portions of the substrate to complete the base.

Abstract: A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

Abstract: A phase change memory (PCM) device, a manufacturing technique of making the PCM device, and a way of operating the PCM device is presented. The PCM device is structured to have a silicon on insulator type substrate that provides an advantage of thermally insulating the active area of the PCM device without the need for an additional insulation layer. The PCM device has a phase change resistor PCR that has one terminal connected to a word line and the other terminal connected in common to the N-terminals of two PN diodes in which the P-terminals are connected in common to the bit line. As a result, a current flowing through the phase change resistor PCR is doubled which results in doubling the cell driving capacity.