Abstract: A user device (e.g., a computing device, a smart device, a mobile device, a laptop, a tablet, a set-top box, a display device, etc.) may generate and/or display a scrollable user interface (e.g., a configuration form/interface, a web form, a web page, an application page, a data form, etc.) that includes data fields. A data reflection element for a data field that is displayed based on proximity of an interactive element to the data field may be generated. Based on an interaction with the data reflection element via the interactive element, data input to the data field may be displayed in a field of a data reflection window of the scrollable user interface. An indication element that indicates correspondence between the data field and the field of the data reflection window may also be displayed.

Abstract: A protection layer for use in fabrication of failure analysis (FA) sample is disclosed, which principally comprises a first thin film, a buffer thin film and a second thin film By forming the protection layer on a surface of a malfunction device die, a FA sample of the malfunction device die is obtained. As a result, in the case of treating the sample with a FIB thinning process, there are no cracks, distortion, and/or collapse resulted from inter-elemental isobaric interferences, stress effect or charge accumulation occurring on the surface layer of the malfunction device die because of the protection of the protection layer. On the other hand, this protection layer can also be applied to a microLED element or a VCSEL element, so as to make microLED element and the VCSEL element possess excellent stress withstanding capability.

Abstract: A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 ?m to about 2 ?m, and a length of the channel of the third transistor is in a range of about 1 ?m to about 2.5 ?m.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.

Abstract: A charge-modulation element encompasses a p-type photoelectric-conversion layer, a n-type surface-buried region buried in an upper portion of the photoelectric-conversion layer configured to implement a photodiode with the photoelectric-conversion layer, a n-type modulation region buried in another part of the upper portion of the photoelectric-conversion layer configured to implement a part of the photodiode with the photoelectric-conversion layer, potential-control regions assigned in one of divided areas, n-type charge-accumulation regions configured to accumulate signal charges generated in the photodiode. Potentials in the modulation region and the surface-buried region are controlled by route-select signals applied to the potential-control regions so as to select one of the charge-transport routes, which transfers the signal charges toward one of the charge-accumulation regions.

Abstract: Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.

Abstract: A transistor includes a semiconductor layer comprising a channel portion, a first contact portion and a second contact portion, a gate electrode facing the floating gate, and a floating gate disposed between the semiconductor layer and the gate electrode, the floating gate being insulated from the semiconductor layer and the gate electrode. The floating gate comprises an oxide semiconductor.

Abstract: A method of forming a crystalline semiconductor material on the basis of a very thin semiconductor base material and an amorphous semiconductor material deposited thereon is disclosed. Radiation-based anneal process techniques may be applied by using appropriate radiation wavelengths, for instance, below 380 nm, in order to efficiently restrict energy deposition to the surface-near area. A solid and crystalline bottom portion of the semiconductor base material may be reliably preserved, thereby achieving crystallization of the overlying material portions and, in particular, of the previously deposited amorphous semiconductor material.

Abstract: Discussed is a solar cell including a semiconductor substrate, a first conductive type region formed on a surface of the semiconductor substrate, a second conductive type region formed on the other surface of the semiconductor substrate, the second conductive type region being spaced from an edge of the semiconductor substrate and having a conductive type different from that of the first conductive type region, an isolation portion formed at a perimeter of the second conductive type region on the other surface of the semiconductor substrate, a first electrode connected to the first conductive type region, and a second electrode connected to the second conductive type region, wherein the second conductive type region has a boundary portion in a part adjacent to the isolation portion, and in which a doping concentration or a junction depth varies over a width of the boundary portion.

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing. In one implementation, the method includes removing oxides from an exposed surface of a substrate in an inductively coupled plasma chamber, forming an epitaxial layer on the exposed surface of the substrate in an epitaxial deposition chamber, and performing an outgassing control of the substrate by subjecting the substrate to a first plasma formed from a first etch precursor in the inductively coupled plasma chamber at a first chamber pressure, wherein the first etch precursor comprises a hydrogen-containing precursor, a chlorine-containing precursor, and an inert gas, and subjecting the substrate to a second plasma formed from a second etch precursor in the inductively coupled plasma chamber at a second chamber pressure that is higher than the first chamber pressure, wherein the second etch precursor comprises a hydrogen-containing precursor and an inert gas.

Abstract: A thin-film transistor, including a substrate; an active layer on the substrate; a gate electrode on the active layer; and a gate insulating layer between the active layer and the gate electrode, the active layer including a channel region; source and drain regions at opposite sides of the channel region; and lightly doped regions between the channel region and the source region and between the channel region and the drain region, the source and drain regions being doped with a first element, and the lightly doped regions being doped with a second element different from the first element.

Abstract: A manufacturing method of a display device is provided including forming a first insulation film above a region including a display region of a substrate, adsorbing organic molecules to approximately the entire first surface on the opposite side to the substrate of the first insulation film, removing the organic molecules adsorbed to a first region defined as an inner side region not reaching an end part of the first insulation film including the display region on the first surface of the first insulation film, forming a second insulation film in the first region removed of the organic molecules on the first insulation film, removing the organic molecules adsorbed in regions apart from the first region of the first insulation film, and forming a third insulation film contacting the first insulation film at an outer side of the second insulation film above the first insulation film and the second insulation film.

Abstract: A resonant transducer includes a resonator, a resonator electrodes connected to an end part of the resonator, at least one fixed electrode arranged in the vicinity of the resonator, and a buried part formed between the fixed electrode and the resonator electrode. The resonator, the resonator electrodes and the fixed electrode are formed by the same active layer on a substrate.

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Abstract: Although an organic resin substrate is highly effective at reducing the weight and improving the shock resistance of a display device, it is required to improve the moisture resistance of the organic resin substrate for the sake of maintaining the reliability of an EL element. Hard carbon films are formed to cover a surface of the organic resin substrate and outer surfaces of a sealing member. Typically, DLC (Diamond like Carbon) films are used as the carbon films. The DLC films have a construction where carbon atoms are bonded into an SP3 bond in terms of a short-distance order, although the films have an amorphous construction from a macroscopic viewpoint. The DLC films contain 95 to 70 atomic % carbon and 5 to 30 atomic % hydrogen, so that the DLC films are very hard and minute and have a superior gas barrier property and insulation performance.

Abstract: In a solid state image sensor which has two photodiodes juxtaposed in a predetermined direction in each pixel and is formed by carrying out divided exposure, that is, exposure treatment of an entire chip by a plurality of times of exposure, image quality is improved and autofocusing speed is increased. Provided is a solid state image sensor having a first exposure region having a first region and a second exposure region having a second region. They overlap with each other in a third region between the first and second regions. In a pixel formed in the third region, a photodiode formed through a mask for first exposure region is placed at a position closer to the side of the second region than another photodiode formed through a mask for second exposure region is.

Abstract: The inventive concept relates to a thin film activation method, a thin film transistor fabrication method, and a substrate processing device, and more particularly, to a method of activating a thin film by using electrical energy, a method of fabricating a thin film transistor, and a device of processing a substrate. The thin film activation method according to an embodiment of the inventive concept may include supplying electrical energy to a thin film.

Abstract: A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extending along a top region and along sidewall regions of the semiconductor portion; implanting first ions into the coating, the first ions having a first trajectory along a perpendicular to the substrate plane, wherein the first ions form a etch-hardened portion comprising a hardened state disposed along the top region; and directing a reactive etch using second ions at the coating, the second ions having a second trajectory forming a non-zero angle with respect to the perpendicular, wherein the reactive etch removes the etch-hardened portion at a first etch rate, wherein the first etch rate is less than a second etch rate when the second ions are directed in the reactive etch to the top portion in the unhardened state.

Abstract: Composite substrates include a single crystal silicon layer disposed on a ceramic layer, including a transparent glass layer. Combination of single crystal devices and non-single crystal devices can be fabricated on a ceramic substrate.

Abstract: The disclosure provides a method for growing GZO (ZnO:Ga) single crystals and relates to the technical field of crystal growth. The method may include the following steps: firstly, preparing compact, uniform and single-phase polycrystalline rods; secondly, optimizing the components and the proportions of flux; finally, optimizing the process parameters of travelling solvent floating zone crystal growth method for GZO, such as growth power, growth rate and rotation speed, etc. GZO crystals grown by this disclosure are high in crystalline quality, consistent in growth direction and excellent in electrical properties.

Abstract: A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved.

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Abstract: A method for manufacturing a light-emitting diode, which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type.

Abstract: Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.

Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.

Abstract: A groove structure formed on a surface of a substrate. The groove structure includes a lateral epitaxial pattern in a cross section perpendicular to the surface, which has: a first edge inclined to the surface; a second edge adjacent to first edge and parallel to the surface; a third edge parallel to the first edge, having a projection on the surface covering the second edge; and a fourth edge adjacent to the third edge. A first intersection between the second edge and the third edge on the second edge and an injection of a second intersection between the third edge and the fourth edge on the second edge are located on two sides of a third intersection between the first edge and the second edge, or the injection of the second intersection between the third edge and the fourth edge on the second edge coincides with the third intersection.

Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.

Abstract: A method for manufacturing a light-emitting diode, which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type.

Abstract: A method for growing islands of semiconductor monocrystals from a solution on an amorphous substrate includes the procedures of depositing a semiconductor-metal mixture layer, applying lithography and etching for forming at least one platform, heating the at least one platform, and saturating the semiconductor-metal solution until a monocrystal of the semiconductor component is formed. The procedure of depositing a semiconductor-metal mixture layer, includes a semiconductor component and at least one other metal component, is performed on top of the amorphous substrate. The procedure of applying lithography and etching to the semiconductor-metal mixture layer and a portion of the amorphous substrate is performed for forming at least one platform, the at least one platform having a top view shape corresponding to crystal growth direction and habit respective of the semiconductor component.

Abstract: A method of producing single-crystal semiconductor material comprises: providing a template material; creating a mask on top of the template material; using the mask to form a plurality of nanostructures in the template material; and growing the single-crystal semiconductor material onto the nanostructures.

Abstract: Disclosed is a crystallization apparatus capable of locally crystallizing amorphous silicon. The crystallization apparatus includes a heat emission part, a support part and a roller. The heat emission part emits heat upon receiving a heat emission source. The support part supports the heat emission part and provides the heat emission source to the heat emission part. The roller receives the heat emission part and has at least one opening to provide heat to a target (e.g., amorphous silicon). Local crystallization is performed without causing damage to a substrate.

Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.

Abstract: The invention relates to a new High Electron Mobility Transistor (HEMT), made essentially of layers of Group XIII element(s) nitride(s). Contrary to currently available transistors of this type, the transistor according to the invention is produced on a homosubstrate made of gallium-containing nitride, has no nucleation layer and its buffer layer is remarkably thinner than in known HEMTs. Preferably, at least the buffer layer, being a part of the transistor according to the present invention, is produced by epitaxial methods and the direction of growth of said layer in an epitaxial process is essentially perpendicular to the direction of growth of the substrate. The invention relates also to a method of manufacturing of High Electron Mobility Transistor (HEMT).

Abstract: The present invention relates to a method of manufacturing a vertically-structured GaN-based light emitting diode. The method of manufacturing a vertically-structured GaN-based light emitting diode includes forming a GaN layer on a substrate; patterning the compound layer in a predetermined shape; forming an n-type GaN layer on the patterned compound layer through the epitaxial lateral over-growth process and sequentially forming an active layer and a p-type GaN layer on the n-type GaN layer; forming a structure supporting layer on the p-type GaN layer; sequentially removing the substrate and the GaN layer formed on the substrate after forming the structure supporting layer; removing the patterned compound layer exposed after removing the GaN layer so as to form an n-type GaN layer patterned in a concave shape; and forming an n-type electrode on the n-type GaN layer patterned in a concave shape.

Abstract: There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. The semiconductor wafer further includes an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer. The inhibition layer inhibiting crystal growth of a compound semiconductor. Furthermore, a seed crystal is provided within the opening, and a compound semiconductor has a lattice match or a pseudo lattice match with the seed crystal.

Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.

Abstract: A method of depositing polycrystalline silicon exclusively on monocrystalline first silicon surface portions of a substrate surface which besides the first surface portions additionally has insulator surface portions, comprising the steps of depositing boron on the first silicon surface portions in an amount which in relation to the first silicon surface portions respectively corresponds to more than a monolayer of boron, and depositing silicon on the first silicon surface portions treated in that way.

Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.

Abstract: A method of forming polysilicon, a thin film transistor (TFT) using the polysilicon, and a method of fabricating the TFT are disclosed. The method of forming the polysilicon comprises: forming an insulating layer on a substrate; forming a first electrode and a second electrode on the insulating layer; forming at least one heater layer on the insulating layer so as to connect the first electrode and the second electrode; forming an amorphous material layer containing silicon on the heater layer(s); forming a through-hole under the heater layer(s) by etching the insulating layer; and crystallizing the amorphous material layer into a polysilicon layer by applying a voltage between the first electrode and the second electrode so as to heat the heater layer(s).

Abstract: A method of producing a radiation-emitting thin film component includes providing a substrate, growing nanorods on the substrate, growing a semiconductor layer sequence with at least one active layer epitaxially on the nanorods, applying a carrier to the semiconductor layer sequence, and detaching the semiconductor layer sequence and the carrier from the substrate by at least partial destruction of the nanorods.

Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.

Abstract: A silicon crystallization method renders it is possible to form alignment key without additional photolithography, and to adjust a substrate to a correct position by sensing a deviation of the substrate when the substrate is loaded. The silicon crystallization method includes aligning the substrate by sensing a fixed substrate with a sensing device, and moving and/or rotating a stage, wherein the sensing device faces toward an edge of the substrate to directly sense the edge of the substrate; forming alignment keys on predetermined portions of a non-display area of the substrate by correspondingly placing a mask for formation of an alignment key above the substrate; and crystallizing an amorphous silicon by correspondingly providing a mask for crystallization above the substrate.

Abstract: To provide a semiconductor substrate in which a semiconductor element having favorable crystallinity and high performance can be formed. A single crystal semiconductor substrate having an embrittlement layer and a base substrate are bonded with an insulating layer interposed therebetween; the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment; a single crystal semiconductor layer is fixed to the base substrate; the single crystal semiconductor layer is irradiated with a laser beam; the single crystal semiconductor layer is in a partially melted state to be recrystallized; and crystal defects are repaired. In addition, the energy density of a laser beam with which the best crystallinity of the single crystal semiconductor layer is obtained is detected by a microwave photoconductivity decay method.

Abstract: A method of fabricating a polycrystalline silicon thin that includes a metal layer forming operation of forming a metal layer on an insulating substrate, a first silicon layer forming operation of stacking a silicon layer on the metal layer formed in the metal layer forming operation, a first annealing operation of forming a silicide layer using by moving catalyst metal atoms from the metal layer to the silicon layer using an annealing process, a second silicon layer forming operation of stacking an amorphous silicon layer on the silicide layer, and a crystallization operation of crystallizing the amorphous silicon layer into crystalline silicon through the medium of particles of the silicide layer.

Abstract: A liquid crystal display device which utilizes an active matrix substrate and its substrate, and which is provided with a novel method of manufacture which can reduce the manufacturing process of amorphous silicon thin film transistors of reverse stagger construction, and an electrostatic protection means which is created using this method of manufacture. In a thin film transistor manufacturing process, along with forming an aperture for connecting the contact hole and the external terminal in a manufacturing process for a thin film transistor, utilization is made of ITO film as the wiring. The electrostatic protection means is formed from a bi-directional diode (electrostatic protection element) which is composed utilizing an MOS transistor connected between the electrode (PAD) for connecting the external terminal, and the joint electric potential line.