Abstract: Native Group IV semiconductor thin films formed from coating substrates using formulations of Group IV nanoparticles are described. Such native Group IV semiconductor thin films leverage the vast historical knowledge of Group IV semiconductor materials and at the same time exploit the advantages of Group IV semiconductor nanoparticles for producing novel thin films which may be readily integrated into a number of devices.

Abstract: One aspect of the present invention relates to a method for fabricating a polycrystalline silicon film. In one embodiment, the method includes the steps of providing a substrate having a thermally-grown silicon dioxide layer, forming an amorphous silicon film on the thermally-grown silicon dioxide layer of the substrate, forming an aluminum layer on the amorphous silicon film to form a structure having the substrate, the amorphous silicon film and the aluminum layer, and annealing the structure at an annealing temperature for a period of time in an N2 environment with a ramp-up time to crystallize the amorphous silicon film to form a polycrystalline silicon film.

Abstract: Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method, a condition is provided with a frequency of 15 to 25 kHz and a deposition power of 0.5 to 3 kW. This can sufficiently contain Ar at 10×1020/cm3 or more in an amorphous silicon film, thus making possible to form an amorphous silicon film having distortion.

Abstract: To crystallize a material, a thin layer of amorphous or polycrystalline material is deposited on at least one area of the surface of a top part of a substrate. A metal layer is then deposited on at least one area of the thin layer. Thermal treatment is then performed to enable crystalline growth of the material of the thin layer, resulting in: a rapid temperature increase of the top part of the substrate until liquid or overmelted liquid state is achieved, and heat transfer from the interface between the top part of the substrate and the thin layer to the interface between the thin layer and the metal layer.

Abstract: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating.

Abstract: A semiconductor device having a pair of impurity doped second semiconductor layers, formed on a first semiconductor layer having a channel formation region therein, an outer edge of the first semiconductor film being at least partly coextensive with an outer edge of the impurity doped second semiconductor layers. The semiconductor device further includes source and drain electrodes formed on the pair of impurity doped second semiconductor layers, wherein the pair of impurity doped second semiconductor layers extend beyond inner sides edges of the source and drain electrodes so that a stepped portion is formed from an upper surface of the source and drain electrodes to a surface of the first semiconductor film.

Abstract: A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.

Abstract: Embodiments of the invention as recited in the claims relate to thin film multi-junction solar cells and methods and apparatuses for forming the same. In one embodiment a method of forming a thin film multi-junction solar cell over a substrate is provided. The method comprises positioning a substrate in a reaction zone, providing a gas mixture to the reaction zone, wherein the gas mixture comprises a silicon containing compound and hydrogen gas, forming a first region of an intrinsic type microcrystalline silicon layer on the substrate at a first deposition rate, forming a second region of the intrinsic type microcrystalline silicon layer on the substrate at a second deposition rate higher than the first deposition rate, and forming a third region of the intrinsic type microcrystalline silicon layer on the substrate at a third deposition rate lower than the second deposition rate.

Abstract: A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer.

Abstract: Embodiments of the present invention provide methods of solid phase recrystallization of thin film using a plurality of pulses of electromagnetic energy. In one embodiment, the methods of the present invention may be used to anneal an entire substrate surface or selected regions of a surface of a substrate by delivering a plurality of pluses of energy to a crystalline seed region or layer upon which an amorphous layer is deposited to recrystallize the amorphous layer so that it has the same grain structure and crystal orientation as that of the underlying crystalline seed region or layer.

Abstract: A method of crystallizing an amorphous semiconductor thin film formed on a substrate is provided. The method includes the steps of: forming a gate insulation film and a gate electrode on an amorphous semiconductor thin film; locally forming first and second crystallization induced metal patterns for inducing crystallization of the amorphous semiconductor thin film, on part of the amorphous semiconductor thin film spaced at a predetermined off-set distance from the gate insulation film; ion-injecting impurities into the substrate to thus define a source/drain region; forming a protection film on the whole surface of the substrate; and heat-treating the substrate in the air to thereby crystallize the amorphous semiconductor thin film.

Abstract: A plasma apparatus having a chamber, a set of arc electrodes and a substrate holder is provided. The set of arc electrodes disposed within the chamber has an anode and a cathode, wherein an arc forming space is formed between the anode and the cathode. The anode and the cathode respectively have a crystallized silicon target. The crystallized silicon target of the anode is disposed on an end facing to that of the cathode, wherein the resistance of the crystallized silicon targets is smaller than 0.01 ?·cm. The substrate holder is disposed within the chamber and has a carrying surface, wherein the carrying surface is face to the arc forming space. Besides, a method of fabricating nano-crystalline silicon thin film is also provided. By using the plasma apparatus, a nano-crystalline silicon thin film with high quality is formed.

Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.

Abstract: A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. In a specific embodiment, the present invention includes providing a semiconductor substrate including a surface region. The method includes forming an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region according to a specific embodiment. The method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers.

Abstract: Embodiments of the present invention provide a method for converting a doped amorphous silicon layer deposited onto a crystalline silicon substrate into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited. Additional embodiments of the present invention provide depositing a dielectric passivation layer onto the amorphous silicon layer prior to the conversion. A temperature gradient is provided at a temperature and for a time period sufficient to provide a desired p-n junction depth and dopant profile.

Abstract: An array substrate includes first and second gate electrodes on a substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers on the gate insulating layer; an interlayer insulating layer on the first and second active layers; first to fourth ohmic contact layers respectively contacting both sides of the first active layer and both sides of the second active layer; first and second source electrodes and first and second drain electrodes respectively on the first, third, second and fourth ohmic contact layers; a data line connected to the first source electrode; a first passivation layer connected to the first gate electrode; a power line; one end and the other end of a connection electrode respectively connected to the first drain electrode and the second gate electrode; a second passivation layer; and a pixel electrode-connected to the second drain electrode.

Abstract: An integrated circuit includes at least one photodiode associated with a read transistor. The photodiode is formed from a stack of three semiconductor layers comprising a buried layer, an floating substrate layer and an upper layer. The drain region and/or the source region of the transistor are incorporated within the upper layer. The buried layer is electrically isolated from the upper layer so as to allow the buried layer to be biased independently of the upper layer.

Abstract: A method of fabricating a polycrystalline silicon (poly-Si) layer includes providing a substrate, forming an amorphous silicon (a-Si) layer on the substrate, forming a thermal oxide layer to a thickness of about 10 to 50 ? on the a-Si layer, forming a metal catalyst layer on the thermal oxide layer, and annealing the substrate to crystallize the a-Si layer into the poly-Si layer using a metal catalyst of the metal catalyst layer. Thus, the a-Si layer can be crystallized into a poly-Si layer by a super grain silicon (SGS) crystallization method. Also, the thermal oxide layer may be formed during the dehydrogenation of the a-Si layer so that an additional process of forming a capping layer required for the SGS crystallization method can be omitted, thereby simplifying the fabrication process.

Abstract: According to one embodiment, a method of fabricating a semiconductor device includes forming a first insulator on a semiconductor substrate, forming a first groove on the insulator to expose at least a part of the semiconductor substrate at a bottom of the first groove, forming a first embedding film including at least germanium in the groove, melting the first embedding film by heat treatment, and crystallizing the first embedding film being melted to a single-crystalline film using the semiconductor substrate as a seed.

Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment.

Abstract: The invention relates to the formation of thin-film crystalline silicon using a zone-melting recrystallization process in which the substrate is a ceramic material. Integrated circuits and solar cells are fabricated in the recrystallized silicon thin film and lifted off the substrate. Following lift-off, these circuits and devices are self-sustained, lightweight and flexible and the released ceramic substrate can be reused making the device fabrication process cost effective.

Abstract: Provided is a method of manufacturing a crystalline semiconductor thin film formed on an amorphous or poly-crystalline substrate such as a glass substrate, a ceramic substrate, and a plastic substrate through induction heating using photo-charges. The method of manufacturing a crystalline semiconductor thin film includes a process of forming a low-concentration semiconductor layer on an inexpensive amorphous or poly-crystalline substrate such as a glass substrate, a ceramic substrate, and a plastic substrate and a process of crystallizing the low-concentration semiconductor layer through an induction heating manner using photo-charges. Accordingly, a low-concentration crystalline semiconductor thin film having characteristics better than those of general amorphous or poly-crystalline semiconductor thin film can be obtained by using simple processes at low production cost.

Abstract: A fabricating process of a thermal enhanced substrate is provided for fabricating thermal conduction blocks to increase the heat dissipation area. A metallic substrate having a first surface and a second surface opposite to the first surface is provided. A first shallow trench with a first depth is then formed on the first surface. A second shallow trench with a second depth is formed on the second surface, and a deep trench penetrating the first shallow trench and the second shallow trench is formed, where the metallic substrate is separated into many thermal conduction blocks by the deep trench. At least one metallic layer and at least one insulating material are laminated on the thermal conduction blocks, and the insulating material is filled into the deep trench and covers the thermal conduction blocks.

Abstract: A solar cell device is provided, including a transparent substrate, a composite transparent conductive layer disposed over the transparent substrate, a photovoltaic element formed over the composite transparent conductive layer, and an electrode layer disposed over the photovoltaic element. In one embodiment, the composite transparent conductive layer includes a first transparent conductive layer and a second transparent conductive layer sequentially stacked over the transparent substrate, and the first transparent conductive layer is made of lithium and fluorine-codoped tin oxide and the second transparent conductive layer is made of a material selected from a group consisting of zinc oxide and titanium dioxide.

Abstract: In embodiments of the invention, a method of forming a monolithic three-dimensional memory array is provided, the method including forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper, and forming a silicon diode in each memory cell, wherein the silicon diode is formed at temperatures compatible with the conductors. The silicon diode may be formed using a hot wire chemical vapor deposition technique, for example. Other aspects are also described.

Abstract: A method of forming a localized SOI structure in a substrate (10) wherein a trench (18) is formed in the substrate, and a dielectric layer (20) is formed on the base of the trench (18). The trench is filled with semiconductor material (22) by means of epitaxial growth.

Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (a-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the a-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the a-Si layer, wherein interface defects existing between the a-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.

Abstract: The invention has for its object to provide a process of synthesizing high-purity hBN crystal bodies on a robust substrate even under normal pressure. The inventive process of producing hexagonal boron nitride crystal bodies is characterized by comprising a preparation step of preparing a mixture of a boron nitride raw material and a metal solvent comprising a transition metal, a contact step of bringing a sapphire substrate in contact with the mixture, a heating step of heating the mixture, and a recrystallization step of recrystallizing at normal pressure a melt obtained in the heating step. It is also characterized by using as the metal solvent a transition metal selected from the group consisting of Fe, Ni, Co, and a combination thereof, and at least one substance selected from the group consisting of Cr, TiN and V without recourse to any sapphire substrate.

Abstract: A planar double-gate transistor is manufactured wherein crystallisation inhibitors are implanted into the channel region (16) of a semiconductor wafer (10), said wafer having a laminate structure comprising an initial crystalline semiconductor layer (14) adjacent an amorphous semiconductor layer (12). Upon heating, partial re-growth of the amorphous semiconductor layer is restricted in the channel area thus allowing for the thickness of the source/drain extension regions to be increased whilst maintaining a thin channel. Any remaining amorphous material is selectively removed leaving a cavity to allow for the forming of gate electrodes (30,32) on opposing sides of the channel region. The invention can be exploited to a greater extent by providing an amorphous layer on both sides of the initial crystalline semiconductor layer thus providing for re-growth limitation in two directions.

Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.

Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure.

Abstract: Disclosed herein is a rapid annealing method in a mixed structure composed of a heat treatment-requiring material, dielectric layer and conductive layer, comprising that during rapid annealing on a predetermined part of the heat treatment-requiring material, by instantaneously generated intense heat due to Joule heating by application of an electric field to the conductive layer, the potential difference between the heat treatment-requiring material and the conductive layer is set lower than the dielectric break-down voltage of the dielectric layer, thereby preventing generation of arc by dielectric breakdown of the dielectric layer during the annealing.

Abstract: A thin film transistor (TFT) and an organic light emitting diode (OLED) display device. The TFT and the OLED display device include a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate electrode insulated from the semiconductor layer, a gate insulating layer insulating the semiconductor layer from the gate electrode, and source and drain electrodes insulated from the gate electrode and partially connected to the semiconductor layer, wherein the semiconductor layer is formed from a polycrystalline silicon layer crystallized by a metal catalyst and the metal catalyst is removed by gettering using an etchant. In addition, the OLED display device includes an insulating layer disposed on the entire surface of the substrate, a first electrode disposed on the insulating layer and electrically connected to one of the source and drain electrodes, an organic layer, and a second electrode.

Abstract: A method of forming a polycrystalline silicon layer includes forming an amorphous silicon layer on a substrate by chemical vapor deposition using a gas including a silicon atom and hydrogen gas, and crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal. The resultant polycrystalline silicon layer has an improved charge mobility.

Abstract: A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.

Abstract: The present invention is to provide a technique that can increase productivity with high output power by combining a plurality of laser beams on an irradiation surface without any difficulties in optical alignment. According to this technique, laser beams having different wavelengths are combined using a plurality of laser oscillators and a dichroic mirror, or additionally a polarizer. For example, a first laser beam emitted from a first laser oscillator is combined with a second laser beam emitted from a second laser oscillator having different wavelength from the first laser beam in such a way that the first laser beam passes through a dichroic mirror and the second laser beam is reflected on the dichroic mirror, and the combined laser beam is projected to an irradiation surface.

Abstract: A multi-junction photovoltaic device includes a silicon substrate and a dielectric layer formed on the silicon substrate. A germanium layer is formed on the dielectric layer. The germanium includes a crystalline structure that is substantially similar to the crystalline structure of the silicon substrate. A first photovoltaic sub-cell includes a first plurality of doped semiconductor layers formed on the germanium layer. At least a second photovoltaic sub-cell includes a second plurality of doped semiconductor layers formed on the first photovoltaic sub-cell that is on the germanium layer that is on the dielectric layer.

Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film comprising adjacent primary grain boundaries that are not parallel to each other and do not contact each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.

Abstract: Methods for forming semiconductor devices include providing a crystalline template having an initial grain size, annealing the crystalline template, the annealed template having a final grain size larger than the initial grain size, forming a buffer layer over the annealed template, and forming a semiconductor layer over the buffer layer.

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure.

Abstract: A method of crystallizing amorphous silicon includes forming an amorphous silicon film over a substrate, crystallizing the amorphous silicon film to form a polycrystalline silicon film using a sequential lateral solidification crystallization method, and performing a surface treatment to the polycrystalline silicon film, wherein the sequential lateral solidification crystallization method includes at least a first application of a first laser beam having a first energy density that completely melts a first uncrystallized portion of the amorphous silicon film and melts a first crystallized portion of the amorphous silicon film, and the surface treatment includes application of a second laser beam having a second energy density that partially melts an entire surface of the polycrystalline silicon film.

Abstract: A process for fabricating a semiconductor device comprising the steps of: introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.

Abstract: A method for forming polycrystalline semiconductor film from amorphous semiconductor film at reduced temperatures and/or accelerated rates. The inclusion of a small percentage of semiconductor material, such as 2% within the metal layer, reduces the temperatures required for crystallization of the amorphous semiconductor by at least 50° C. in comparison to the use of the metal layer without the small percentage of semiconductor material. During a low temperature isothermal annealing process adjacent Al-2% Si and a-Si films undergo a layer exchange resulting in formation of a continuous polycrystalline silicon film having good physical and electrical properties. Formation of polycrystalline-semiconductor in this manner is suitable for use with low temperature substrates (e.g., glass, plastic) as well as with numerous integrated circuit and MEMs fabrication devices and practices.

Abstract: Latch-up resistant semiconductor structures formed on a hybrid substrate and methods of forming such latch-up resistant semiconductor structures. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.

Abstract: A method of forming wires of a poly-crystalline TFT by crystallizing an amorphous silicon thin film using a metal film is provided. The wires forming method includes the steps of: removing a MILC metal film; forming etch-stopper layer patterns on at least part of respective source and drain regions formed on a semiconductor layer; forming an interlayer insulation film on the substrate; etching the interlayer insulation film to thereby form contact holes which expose the etch-stopper layer patterns of the source and drain regions; and forming a wires metal film contacting the etch-stopper layer patterns, and patterning the wires metal film to thus form metal wires. Thus, as the etch-stopper layer patterns are additionally installed at the contact positions, a silicon thin film can be protected at etching the interlayer insulation film.

Abstract: A polycrystalline silicon layer, a flat panel display using the polycrystalline silicon layer, and methods of fabricating the same are provided. An amorphous silicon layer is formed on a substrate. A first pattern layer, a second pattern layer, and a metal catalyst layer are formed on the amorphous silicon layer. The first pattern layer and the second pattern layer are formed to define a region of at least 400 ?m2 within which a metal catalyst of the metal catalyst layer is diffused into the amorphous silicon layer. A seed region is crystallized by the diffused metal catalyst. After a crystallization region is grown from the seed region, a semiconductor layer is formed on the crystallization region, so as to fabricate a thin film transistor with excellent characteristics. Using this, a flat panel display is fabricated.

Abstract: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and including source and drain regions, each having a first metal catalyst crystallization region and a second metal catalyst crystallization region, and a channel region having the second metal catalyst crystallization region, a gate electrode disposed in a position corresponding to the channel region of the semiconductor layer, a gate insulating layer interposed between the semiconductor layer and the gate electrode to electrically insulate the semiconductor layer from the gate electrode, and source and drain electrodes electrically insulated from the gate electrode and electrically connected to the source and drain regions, respectively. An OLED display device includes the thin film transistor and a first electrode, an organic layer, and a second electrode electrically connected to the source and drain electrodes.

Abstract: An epitaxial wafer and method for fabricating the same can prevent a bowing phenomenon of the epitaxial wafer. The epitaxial wafer includes a substrate configured to be doped in a first doping concentration; an epitaxial layer configured to be formed over a first side of the substrate and doped in a second doping concentration lower than the first doping concentration; and a back seal layer configured to be formed over a second side of the substrate and include a layer having a tensile stress, wherein the second side is opposite to the first side, of the substrate.

Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.

Abstract: A method of manufacturing a polycrystalline Si film and a method of manufacturing a stacked transistor are provided. The method of manufacturing the polycrystalline Si film includes preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed, forming an interconnection metal line separated from the gate, forming an insulating layer that covers the transistor and the interconnection metal line, forming an amorphous silicon layer on the insulating layer; and annealing the amorphous silicon layer.