Abstract: The invention has for its object to provide a process of synthesizing high-purity hBN crystal bodies on a robust substrate even under normal pressure. The inventive process of producing hexagonal boron nitride crystal bodies is characterized by comprising a preparation step of preparing a mixture of a boron nitride raw material and a metal solvent comprising a transition metal, a contact step of bringing a sapphire substrate in contact with the mixture, a heating step of heating the mixture, and a recrystallization step of recrystallizing at normal pressure a melt obtained in the heating step. It is also characterized by using as the metal solvent a transition metal selected from the group consisting of Fe, Ni, Co, and a combination thereof, and at least one substance selected from the group consisting of Cr, TiN and V without recourse to any sapphire substrate.

Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.

Abstract: A method of forming a crystalline silicon layer on a microrough face of a substrate by reducing the microroughness of the face and then performing a metal induced crystallization process on the face is disclosed. The method further comprises, after metal induced crystallization and before removing the metal layer, removing silicon islands using the metal layer as a mask.

Abstract: Disclosed is a crystallization apparatus capable of locally crystallizing amorphous silicon. The crystallization apparatus includes a heat emission part, a support part and a roller. The heat emission part emits heat upon receiving a heat emission source. The support part supports the heat emission part and provides the heat emission source to the heat emission part. The roller receives the heat emission part and has at least one opening to provide heat to a target (e.g., amorphous silicon). Local crystallization is performed without causing damage to a substrate.

Abstract: One aspect of the present invention relates to a method for fabricating a polycrystalline silicon film. In one embodiment, the method includes the steps of providing a substrate having a thermally-grown silicon dioxide layer, forming an amorphous silicon film on the thermally-grown silicon dioxide layer of the substrate, forming an aluminum layer on the amorphous silicon film to form a structure having the substrate, the amorphous silicon film and the aluminum layer, and annealing the structure at an annealing temperature for a period of time in an N2 environment with a ramp-up time to crystallize the amorphous silicon film to form a polycrystalline silicon film.

Abstract: An active pixel using a transfer gate that has a polysilicon gate doped with P+ is disclosed. The pixel includes a photosensitive element formed in a semiconductor substrate and an n-type floating node formed in the semiconductor substrate. An n-channel transfer transistor having a transfer gate is formed between the floating node and the photosensitive element. The transfer gate is doped with a p-type dopant.

Abstract: A high quality single crystal substrate and a method of fabricating the same are provided. The method of fabricating a single crystal substrate includes: forming an insulator on a substrate; forming a window in the insulator, the window exposing a portion of the substrate; forming an epitaxial growth silicon or germanium seed layer on the portion of the substrate exposed through the window; depositing a silicon or germanium material layer, which are crystallization target material layers, on the epitaxial growth silicon 6r germanium seed layer and the insulator; and crystallizing the crystallization target material layer by melting and cooling the crystallization target material layer.

Abstract: A method of forming a crystalline silicon layer on a microrough face of a substrate by reducing the microroughness of the face and then performing a metal induced crystallization process on the face is disclosed.

Abstract: Disclosed herein is a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor, and more specifically a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor wherein a phosphosilicate-spin-on-glass (P-SOG) is used for a gate insulating film. The method comprises the steps of: forming a buffer layer on an insulating substrate; forming a gate metal pattern on the buffer layer; forming a planarized gate insulating film on the gate metal pattern; depositing an amorphous silicon layer on the gate insulating film; crystallizing the amorphous silicon layer into a polycrystalline silicon layer; forming a n+ or p+ layer on the polycrystalline silicon layer; forming a source/drain metal layer on the n+ or p+ layer; and forming a passivation layer on the source/drain metal layer.

Abstract: An electro-optical device includes: a substrate; a plurality of pixel units provided in a display region on the substrate; and a driving circuit that is provided in a peripheral region surrounding the display region and includes semiconductor elements that drive the plurality of pixel units, each of the semiconductor elements having a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has an SOI (silicon on insulator) structure including a first single crystal silicon layer, and the second semiconductor layer is formed of a second single crystal silicon layer that is formed on the first semiconductor layer by epitaxial growth.

Abstract: A method of forming a circuit structure includes providing a substrate; etching the substrate to form nano-structures; and growing a compound semiconductor material onto the nano-structures using epitaxial growth. Portions of the compound semiconductor material grown from neighboring ones of the nano-structures join each other to form a continuous compound semiconductor film. The method further includes separating the continuous compound semiconductor film from the substrate.

Abstract: One of the objects of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance between the oxide semiconductor layer and a source and drain electrodes is reduced, and to provide a method for manufacturing the thin film transistor. An ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the IGZO semiconductor layer and the source and drain electrode layers.

Abstract: The invention provides a method of fabricating a semiconductor device having an inversely staggered TFT capable of high-speed operation, which has few variations of the threshold. In addition, the invention provides a method of fabricating a semiconductor device with high throughput where the cost reduction is achieved with few materials.

Abstract: A method for manufacturing a semiconductor including the steps of supplying a substrate having a support with one face supporting a strained silicon thin layer; forming a first mask on a portion of the strained silicon thin layer; epitaxy of Si1-xGex on the portion of the layer not masked by the first mask; condensating germanium to obtain a strained germanium layer, the strained germanium layer then covered by a silicon oxide layer; eliminating the first mask and of the silicon oxide layer thereby exposing a semi-conducting thin layer; forming a second mask on the semi-conducting thin layer exposed via the previous step, the second mask protecting a region of the exposing a remaining strained germanium portion; epitaxial growing germanium on the remaining strained germanium portion; and removing the second mask.

Abstract: A Pendeo-epitaxy growth substrate and a method of manufacturing the same are provided. The Pendeo-epitaxy growth substrate includes a substrate, a plurality of pattern areas formed on the substrate in a first direction for Pendeo-epitaxy growth, and at least one solution blocking layer contacting the plurality of pattern areas and formed on the substrate in a second direction, thereby preventing contamination of a semiconductor device due to air gaps and reducing the percentage defects of the semiconductor device during a Pendeo-epitaxy growth process.

Abstract: A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.

Abstract: Embodiments in accordance with the present invention relate to the fabrication of thin (>1 ?m) polycrystalline, nanocrystalline, or amorphous silicon films on a substrate. Particular embodiments utilize liquid sources of silane, including but not limited to cyclohexasilane (CHS), cyclopentasilane (CPS) or related derivatives of these compounds. In one embodiment, the silane is applied in liquid form contained by the use of a series of raised walls. Subsequent polymerization results in the material being a solid form. In other embodiments, the silane is applied as a liquid which is then frozen, with subsequent localized melting allowing polymerization to convert the material into a stable solid form. Embodiments of the present invention are particularly suited for forming thick (>10 ?m) silicon films needed to achieve light absorption efficiencies deemed acceptable for thin film photovoltaic devices.

Abstract: The present invention provides a phase transition method of an amorphous material, comprising steps of: depositing the amorphous material on a dielectric substrate; forming a cap layer on the amorphous material; depositing a metal on the cap layer; and crystallizing the amorphous material. According to the present invention, the surface of the amorphous material is protected by the cap layer, so that clean surface can be obtained and the roughness of the surface can be remarkably reduced during thermal process and sample handling. In addition, the cap layer is disposed between the amorphous material and the metal to diffuse the metal, so that the metal contamination due to the direct contact of the metal and the amorphous material in the conventional method can be remarkably reduced.

Abstract: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.

Abstract: A doped semiconductor junction for use in an electronic device and a method for making such junction is disclosed. The junction includes a first polycrystalline semiconductor layer doped with donors or acceptors over a substrate such that the first doped semiconductor layer has a first polarity, the first layer including fused semiconductor nanoparticles; and a second layer in contact with the first semiconductor layer over a substrate to form the semiconductor junction.

Abstract: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) providing an insulating layer on a top surface of the semiconductor substrate, c) making an amorphous layer in a top layer of said semiconductor substrate by a suitable implant, d) implanting a dopant into said semiconductor substrate through said insulating layer to provide said amorphous layer with a predetermined doping profile, said implant being performed such that said doping profile has a peak value located within said insulating layer, e) applying a solid phase epitaxial regrowth action to regrow said amorphous layer and activate said dopant.

Abstract: Wafers of semi-conducting material are formed by moulding and directional crystallization from a liquid mass of this material. A seed, situated at the bottom of the crucible, presents an orientation along non-dense crystallographic planes. The mould is filled with the molten semi-conducting material by means of a piston or by creation of a pressure difference in the device. The mould is preferably coated with a non-wettable anti-adhesive deposit.

Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.

Abstract: The present invention relates to a thin-film solar cell and a fabrication method thereof, the solar cell having a structure that a glass substrate, a transparent conductive oxide, a multi-junction solar cell layer and an electrode layer are stacked, wherein a first solar cell layer and a second solar cell layer, which are in a multi-junction, are electrically connected with each other in parallel, and one or more unit cells connected in parallel are grouped to be electrically connected with each other in series. According to the present invention, a thin-film solar cell having a unit cell in a structure that two solar cell layers having different characteristics are connected with each other in parallel, and having a structure that several unit cells are connected with each other in series, can achieve higher output and efficiency than a thin-film solar cell having a structure that several solar cell layers are connected in series.

Abstract: A display panel including a pixel array region. The pixel array region includes a plurality of pixel cells disposed in a matrix configuration. Each pixel cell has an active device. A relative position of a first active device in a first pixel cell among the pixel cells is different from that of a second active device in a second pixel cell among the pixel cells.

Abstract: The present process for rapidly heating and cooling a target material without damaging the substrate upon which it has been deposited. More specifically, target material is coated onto a first substrate. A self-propagating nanoenergetic material is selected that combusts at temperatures sufficient to change the target material and creates a flame front that propagates sufficiently quickly that the first substrate is not substantially heated. The nanoenergetic material is deposited on the target material, such that the target material and the nanoenergetic material is sandwiched between the substrate and the target material. The nanoenergetic material is ignited and the flame front of the nanoenergetic material is allowed to propagate over the second substrate and change the target material.

Abstract: Devices and methods for junction formation in manufacturing a semiconductor device are disclosed. The devices have shallow junction depths far removed from end-of range defects. The method comprises forming an amorphous region in a crystalline semiconductor such as silicon down to a first depth, followed by implantation of a substitutional element such as carbon to a smaller depth than the first depth. The region is then doped with suitable dopants, e.g. phosphorus or boron, and the amorphous layer recrystallized by a thermal process.

Abstract: The present invention relates to a method for manufacturing a semiconductor film, including the steps of forming a transparent conductive film, forming a first conductive film over the transparent conductive film, forming a second conductive film over the first conductive film, etching the second conductive film with a gas including chlorine, and etching the first conductive film with a gas including fluorine. During etching of the second conductive film with a gas including chlorine, the transparent conductive film is protected by the first conductive film. During etching of the first conductive film with the gas including fluorine, the transparent conductive film does not react with the gas including fluorine. Therefore, no particle is formed.

Abstract: A method for fabricating a semiconductor device includes providing a substrate, forming an amorphous silicon layer over the substrate, forming a heat retaining layer on the amorphous silicon layer, patterning the heat retaining layer, and irradiating the patterned heat retaining layer.

Abstract: In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching of the dislocations, an epitaxial layer overgrowth is performed. In certain embodiments, the etching of the dislocations occurs simultaneously with growth of the epitaxial layer. In other embodiments, a dielectric mask is deposited within the etch pits formed at the dislocations prior to the epitaxial layer overgrowth.

Abstract: A method of fabricating a thin film transistor can include forming a metal catalyst layer on a substrate on which an amorphous silicon layer and a capping layer are formed. The metal catalyst may be formed using a sputtering target in which a composition ratio of the metal catalyst is controlled in the process of forming the sputtering target. The target may be composed of the metal catalyst and a metal with a larger atomic weight than the metal catalyst. The alloy may be formed with a predetermined composition ratio. The substrate may be annealed to crystallize the amorphous silicon layer to a polycrystalline silicon layer.

Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

Abstract: A first interconnection is formed along a groove of a substrate and on a bottom surface of the groove, and has a first thickness. A second interconnection is electrically connected to the first interconnection and has a second thickness larger than the first thickness. An acceleration sensing unit is electrically connected to the second interconnection. A sealing unit has a portion opposed to the substrate with the first interconnection therebetween, and surrounds the second interconnection and the acceleration sensing unit on the substrate. A cap is arranged on the sealing unit to form a cavity on a region of the substrate surrounded by the sealing unit. Thereby, airtightness of the cavity can be ensured and also an electric resistance of the interconnection connected to the acceleration sensing unit can be reduced.

Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure.

Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.

Abstract: A method for determining the movement of particles, particularly impurities, in a medium, under the influence of a changing interface between two neighboring phases. In a first step, the temporal and/or local evolution of said interface is determined. In a second step, the movement of said particles in dependence of the temporal and/or local evolution of the phase interface as determined in the first step is calculated. Optionally, the distribution of the particles within the medium at a certain time is then determined.

Abstract: Embodiments of the present invention may include an improved thin film solar cell device that is formed by sequentially depositing an intrinsic amorphous silicon layer and an intrinsic microcrystalline silicon layer during the p-i-n or n-i-p junction formation process. Embodiments of the invention also generally provide a method and apparatus for forming the same. The present invention may be used to advantage to form other single junction, tandem junction, or multi-junction thin film solar cell devices.

Abstract: Example embodiments relate to a poly-crystalline silicon (Si) thin film, a thin film transistor (TFT) formed from a poly-crystalline silicon (Si) thin film and methods of manufacturing the same. The method of manufacturing the poly-crystalline Si thin film includes forming an active layer formed of amorphous Si on a substrate, coating a gold nanorod on the active layer, and irradiating infrared rays onto the gold nanorod to crystallize the active layer.

Abstract: A semiconductor device includes a single crystal silicon substrate an insulating layer partially formed on the single crystal silicon substrate, a single crystal silicon layer formed on the single crystal silicon substrate and the insulating layer, and containing a defect layer resulting from an excessive group IV element, and a plurality of first gate structures for memory cells, each including a first gate insulating film formed on the single crystal silicon layer, a charge storage layer formed on the first gate insulating film, a second gate insulating film formed on the charge storage layer, and a control gate electrode formed on the second gate insulating film.

Abstract: A separation layer containing a halogen element is formed over a glass substrate by a plasma CVD method; a semiconductor element is formed over the separation layer; and separation is then performed inside the separation layer or at its interface, so that the large-area glass substrate and the semiconductor element are detached from each other. In order to perform detachment at the interface between the glass substrate and the separation layer, the separation layer may have concentration gradient of the halogen element, and the halogen element is contained more near the interface between the separation layer and the glass substrate than in the other areas.

Abstract: A manufacturing method of a semiconductor device with improved operating characteristics and reliability is provided. An amorphous semiconductor film is formed over a substrate, doped with a metal element promoting crystallization, and crystallized by first heat treatment to form a crystalline semiconductor film; a first oxide film formed over the crystalline semiconductor film is removed and a second oxide film is formed; the crystalline semiconductor film having the second oxide film formed thereover is irradiated with first laser light; a semiconductor film containing a rare gas element is formed over the second oxide film; the metal element contained in the crystalline semiconductor film is gettered to the semiconductor film containing a rare gas element by second heat treatment; the semiconductor film containing a rare gas element and the second oxide film are removed; and the crystalline semiconductor film is irradiated with second laser light in an atmosphere containing oxygen.

Abstract: A thin film transistor (TFT), including a substrate, an active layer and a gate electrode on the substrate, and a first gate insulating layer and a second gate insulating layer between the active layer and the gate electrode. Each of the first gate insulating layer and the second gate insulating layer may have a thickness between approximately 200 ? and approximately 400 ?, inclusive.

Abstract: A method of crystallizing an amorphous semiconductor thin film used for a thin film transistor (TFT) is provided. The method includes the steps of: forming first and second crystallization induced metal patterns locally in respective portions of a source region and a drain region of the TFT on an amorphous semiconductor thin film; and crystallizing an amorphous semiconductor via independent two-times heat treatment using the first and second crystallization induced metal patterns. In this case, the independent two-times heat treatment is executed before and after ions of impurities are injected, respectively. In this way, a metal induced lateral crystallization double heat treatment is executed before and after ions of impurities are injected, respectively. As a result, the entire crystallization heat treatment time necessary for crystallizing the amorphous semiconductor thin film can be greatly reduced, and a poly-crystalline TFT having low leakage current can be obtained.

Abstract: The present invention provides for a low-temperature method to crystallize a silicon-germanium film. Metal-induced crystallization of a deposited silicon film can serve to reduce the temperature required to crystallize the film. Increasing germanium content in a silicon-germanium alloy further decreases crystallization temperature. By using metal-induced crystallization to crystallize a deposited silicon-germanium film, temperature can be reduced substantially. In preferred embodiments, for example in a monolithic three dimensional array of stacked memory levels, reduced temperature allows the use of aluminum metallization. In some embodiments, use of metal-induced crystallization in a vertically oriented silicon-germanium diode having conductive contacts at the top and bottom end is be particularly advantageous, as increased solubility of the metal catalyst in the contact material will reduce the risk of metal contamination of the diode.

Abstract: A method is disclosed for making a doped semiconductor transport layer for use in an electronic device comprising: growing in-situ doped semiconductor nanoparticles in a colloidal solution; depositing the in-situ doped semiconductor nanoparticles on a surface; and annealing the deposited in-situ doped semiconductor nanoparticles so that the organic ligands boil off the surface of the in-situ doped semiconductor nanoparticles.

Abstract: A semiconductor device composed of III-nitride materials is produced with epitaxial growth that permits vertical and lateral growth geometries to improve device characteristics. The resulting device has a greater breakdown voltage due to the greater integrity of the semiconductor material structure since no ion implantation processes are used. The epitaxially grown layers also exhibit greater thermal conductivity for improved operation with power semiconductor devices. The device may include a laterally grown charge compensated area to form a superjunction device. The resulting device may be bidirectional and have improved breakdown voltage in addition to higher current capacity for a given voltage rating.

Abstract: A method of selectively heating a predetermined region of a semiconductor substrate includes providing a semiconductor substrate, selectively focusing a free carrier generation light on only a predetermined region of the semiconductor substrate, irradiating the free carrier generation light on the predetermined region of the semiconductor substrate to increase a free carrier concentration within the predetermined region of the semiconductor substrate, wherein the free carrier generation light causes the predetermined region to increase in temperature by less than a temperature necessary to change the solid phase of the predetermined region, and irradiating the semiconductor substrate with a heating light to selectively heat the predetermined region of the semiconductor substrate.

Abstract: An array substrate includes a thin-film transistor (TFT), a first insulation layer and a second insulation layer. The TFT is formed on the substrate. The TFT includes an active pattern, a gate metal pattern and a data metal pattern. The first insulation layer insulates the active pattern from the gate metal pattern. The second insulation layer is formed spaced apart by a predetermined width from at least one edge of the substrate. The second insulation layer insulates the gate metal pattern from the data metal pattern. Therefore, the second insulation layer is formed so that stress that is inflicted on a substrate may be decreased, thereby preventing deformation during a manufacturing process of the substrate.

Abstract: The invention includes a method of fabricating a gate structure for a field effect transistor and the gate structure. The method includes providing a crystalline silicon substrate and epitaxially growing a gate insulating layer of crystalline rare earth insulating material on the crystalline silicon substrate. A gate stack of crystalline silicon is then epitaxially grown on the layer of crystalline rare earth insulating material and doped to provide a desired type of conductivity. The gate insulating layer and the gate stack are etched and a metal electrical contact is deposited on the epitaxially grown gate stack of crystalline silicon to define a gate structure.

Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.