From A Liquid, E.g., Electrolytic Deposition (epo) Patents (Class 257/E21.174)
  • Patent number: 8318601
    Abstract: The present invention discloses a display device and a manufacturing method thereof by which a manufacturing process can be simplified. Further, the present invention discloses technique for manufacturing a pattern such as a wiring into a desired shape with good controllability. A method for forming a pattern for constituting the display device according to the present invention comprises the steps of forming a first region and a second region; discharging a composition containing a pattern formation material to a region across the second region and the first region; and flowing a part of the composition discharged to the first region into the second region; wherein wettability with respect to the composition of the first region is lower than that of the second composition.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Gen Fujii
  • Patent number: 8293658
    Abstract: Methods and structures relating to the formation of mixed SAMs for preventing undesirable growth or nucleation on exposed surfaces inside a reactor are described. A mixed SAM can be formed on surfaces for which nucleation is not desired by introducing a first SAM precursor having molecules of a first length and a second SAM precursor having molecules of a second length shorter than the first. Examples of exposed surfaces for which a mixed SAM can be provided over include reactor surfaces and select surfaces of integrated circuit structures, such as insulator and dielectric layers.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 23, 2012
    Assignee: ASM America, Inc.
    Inventors: Eric Shero, Mohith Verghese, Anthony Muscat, Shawn Miller
  • Publication number: 20120255605
    Abstract: The invention relates to a method of manufacturing a p-type electrode comprising the steps of: preparing an N-type base semiconductor substrate comprising an n-base layer, a p-type emitter on the n-base layer, a first passivation layer on the p-type emitter, and a second passivation layer on the n-base layer; applying a conductive paste onto the first passivation layer, wherein the conductive paste comprises (i) 100 parts by weight of a conductive powder comprising a metal selected from the group consisting of silver, nickel, copper and a mixture thereof, (ii) 0.3 to 8 parts by weight of aluminum powder with particle diameter of 3 to 11 ?m, (iii) 3 to 22 parts by weight of a glass frit, and (iv) an organic medium; and firing the conductive paste.
    Type: Application
    Filed: April 5, 2012
    Publication date: October 11, 2012
    Applicant: E. I. DU PONT DE NEMOURS AND COMPANY
    Inventor: NORIHIKO TAKEDA
  • Patent number: 8268725
    Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: September 18, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
  • Patent number: 8247301
    Abstract: A substrate having, on a base material, a barrier film for preventing copper diffusion containing one or more metal elements selected from tungsten, molybdenum and niobium, a metal element having a catalytic function in electroless plating such as ruthenium, rhodium, and iridium, and nitrogen contained in the form of a nitride of the aforementioned one or more metal elements selected from tungsten, molybdenum and niobium. The barrier film for preventing copper diffusion is manufactured by sputtering in a nitrogen atmosphere using a target containing one or more metal elements selected from tungsten, molybdenum and niobium and the aforementioned metal element having a catalytic function in electroless plating.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: August 21, 2012
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Junichi Ito, Atsushi Yabe, Junnosuke Sekiguchi, Toru Imori
  • Patent number: 8247883
    Abstract: An embodiment is a method and apparatus to construct a shielded cable, wire, or circuit. A first insulator layer is deposited on a first conductor or semiconductor layer. A second conductor or semiconductor layer is deposited on the first insulator layer. A second insulator layer is deposited on the first insulator layer. The second insulator layer covers the second conductor or semiconductor layer and defines a shielded region. A third conductor or semiconductor layer is deposited on the first conductor or semiconductor layer. The third conductor or semiconductor layer covers the first and second insulator layers. At least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: August 21, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jurgen H. Daniel, Tse Nga Ng
  • Patent number: 8227325
    Abstract: An article includes a polycrystalline semiconductor layer having a plurality of single crystal crystallites of semiconductor material and a substrate having a melting or softening point of <200° C. supporting the semiconductor layer. An average grain size of the plurality of single crystal crystallites is less at an interface proximate to the substrate as compared to an average grain size in the semiconductor layer remote from the interface. The semiconductor layer is fused exclusive of any bonding agent or intermediate layer to the surface of the substrate.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: July 24, 2012
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Sachin Bet, Aravinda Kar
  • Publication number: 20120122311
    Abstract: An electroless plated metal layer formation method for forming a metal layer on a diode chip/wafer for wire bonding is disclosed to include the step of forming a metal base material on a diode chip/wafer adapted for inducing a reduction system to cause a catalytic reaction at location(s) where the desired metal layer is to be formed, and the step of employing an electroless plating process to form a metal layer on the diode chip/wafer that surrounds the metal base material. An isolation layer may be formed on the metal base layer and opening(s) may be formed on the isolation layer before deposition of the metal layer.
    Type: Application
    Filed: January 26, 2012
    Publication date: May 17, 2012
    Inventor: Chun-Pin CHEN
  • Publication number: 20120100709
    Abstract: A plating apparatus allows a substrate holder to be serviced easily while ensuring easy access to the substrate holder and while a substrate is being processed in the plating apparatus. The plating apparatus includes a plating section for plating a substrate, a substrate holder for holding the substrate, a substrate holder transporter for holding and transporting the substrate holder, a stocker for storing the substrate holder, and a stocker setting section for storing the stocker therein. The stocker includes a moving mechanism for moving the stocker into and out of the stocker setting section.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 26, 2012
    Inventor: Yoshio MINAMI
  • Patent number: 8163641
    Abstract: A charge transfer mechanism is used to locally deposit or remove material for a small structure. A local electrochemical cell is created without having to immerse the entire work piece in a bath. The charge transfer mechanism can be used together with a charged particle beam or laser system to modify small structures, such as integrated circuits or micro-electromechanical system. The charge transfer process can be performed in air or, in some embodiments, in a vacuum chamber.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: April 24, 2012
    Assignee: FEI Company
    Inventors: George Y. Gu, Neil J. Bassom, Thomas J. Gannon, Kun Liu
  • Patent number: 8158517
    Abstract: An object of the present invention is to provide a method for manufacturing a display device by improving the utilization efficiency of materials and simplifying manufacturing process. Another object of the invention is to provide a technique for forming a pattern such as a wiring having a predetermined shape included in a display device with good controllability. A method for manufacturing a wiring substrate of the invention includes the steps of: forming a first region having a subject material; modifying the surface of the subject material partly to form a second region having a boundary with respect to the first region; continuously discharging a composition containing a conductive material to a part of the first region across the boundary and the second region; solidifying the composition to form a conductive layer; and removing the conductive layer formed in a part of the first region across the boundary.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: April 17, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroko Yamamoto, Ryo Tokumaru
  • Publication number: 20120068334
    Abstract: Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 ?m or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo MIGITA, Hirokazu Ezawa, Soichi Yamashita
  • Publication number: 20120060912
    Abstract: The present invention provides a method of forming a conductive electrode structure including: applying a conductive paste on a substrate; forming a conductive pattern having an outwardly convex shape by heat-treating the conductive paste; and forming a solder layer to conformally cover the conductive pattern.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 15, 2012
    Inventors: Su Hwan Cho, Dong Hoon Kim, Byung Ho Jun, Kyoung Jin Jeong
  • Patent number: 8105945
    Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: January 31, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Nakamura, Kiyofumi Ogino
  • Patent number: 8039379
    Abstract: Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for this deposition process without adding footprint in the semiconductor fabrication plant.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: October 18, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Glenn Alers, Robert H. Havemann
  • Patent number: 8026175
    Abstract: After a liquid chemical treatment is finished, in parallel with a washing away treatment and/or a drying treatment, by spraying from a nozzle for a cleaning liquid supplied by a cleaning line to an outer surface of a nozzle for a liquid chemical, crystals and the like of components of the liquid chemical adhered on the outer surface of the nozzle are removed. In the cleaning treatment, a spraying time of the cleaning liquid is five seconds to ten seconds. In addition, the components of the cleaning liquid is not specifically limited, however, since ammonium phosphate tends to be solved in purified water, if a liquid chemical containing ammonium phosphate is used, it is preferable to use purified water as the cleaning liquid. Depending on the components and the like of the liquid chemical, a solution that can solve the crystals and the like may be used in stead.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: September 27, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tadashi Oshima
  • Patent number: 8003533
    Abstract: A disclosed laminated structure includes a wettability-variable layer containing a wettability-variable material whose surface energy changes when energy is applied thereto and including at least a high-surface-energy area having high surface energy and a low-surface-energy area having low surface energy; and a conductive layer formed on the high-surface-energy area. The high-surface-energy area includes a first area and a second area extending from the first area and having a width smaller than that of the first area.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: August 23, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Atsushi Onodera, Hidenori Tomono, Koei Suzuki, Takanori Tano, Takumi Yamaga
  • Publication number: 20110201196
    Abstract: A method for producing an electrically conducting metal contact on a semiconductor component having a coating on the surface of a semiconductor substrate. In order to keep transfer resistances low while maintaining good mechanical strength, the invention proposes applying a particle-containing fluid onto the coating, where the particles contain at least metal particles and glass frits, curing the fluid while simultaneously forming metal areas in the substrate through heat treatment, removing the cured fluid and the areas of the coating covered by the fluid, and depositing, for the purposes of forming the contact without using intermediate layers, electrically conducting material from a solution onto areas of the semiconductor component in which the coating is removed while at the same time conductively connecting the metal areas present in said areas on the substrate.
    Type: Application
    Filed: November 26, 2009
    Publication date: August 18, 2011
    Applicant: SCHOTT SOLAR AG
    Inventors: Jorg Horzel, Gunnar Schubert, Stefan Dauwe, Peter Roth, Tobias Droste, Wilfried Schmidt, Ingrid Ernst
  • Publication number: 20110195542
    Abstract: A method of providing solar cell electrode by electroless plating and an activator used therein are disclosed. The method of the present invention can be performed without silver paste, and comprises steps: (A) providing a silicon substrate; (B) contacting the silicon substrate with an activator, wherein the activator comprises: a noble metal or a noble metal compound, a thickening agent, and water; (C) washing the silicon substrate by a cleaning agent; (D) dipping the silicon substrate in an electroless nickel plating solution to perform electroless plating. The method of providing solar cell electrode by electroless plating of the present invention has high selectivity between silicon nitride and silicon, large working window, and is steady, easily to be controlled, therefore is suitable for being used in the fabrication of the electrodes of the solar cell substrate.
    Type: Application
    Filed: January 26, 2011
    Publication date: August 11, 2011
    Applicant: E-CHEM ENTERPRISE CORP.
    Inventors: Chia Wei Chou, Su-Fei Hsu, Michael Liu
  • Patent number: 7951710
    Abstract: The present invention discloses a display device and a manufacturing method thereof by which a manufacturing process can be simplified. Further, the present invention discloses technique for manufacturing a pattern such as a wiring into a desired shape with good controllability. A method for forming a pattern for constituting the display device according to the present invention comprises the steps of forming a first region and a second region; discharging a composition containing a pattern formation material to a region across the second region and the first region; and flowing a part of the composition discharged to the first region into the second region; wherein wettability with respect to the composition of the first region is lower than that of the second composition.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: May 31, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Gen Fujii
  • Patent number: 7952146
    Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Shom Ponoth
  • Patent number: 7919411
    Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: April 5, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Nakamura, Kiyofumi Ogino
  • Patent number: 7875934
    Abstract: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: January 25, 2011
    Assignee: Intel Corporation
    Inventors: Rajashree Baskaran, Kramadhati V. Ravi
  • Patent number: 7820465
    Abstract: A circuit pattern is formed by following steps: forming a light-blocking mask over a major surface of a light-transmitting substrate, forming a first film in a first region over the substrate and the mask, forming a photocatalytic film in at least a part of the first region over the first film, changing wettability of the first film in a second region which is in the first region, being in contact with the photocatalytic film, and not overlapping the mask, by light irradiation from a back surface opposite to the major surface of the substrate, removing the photocatalytic film, and forming a composition including a pattern forming material in the second region.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: October 26, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Gen Fujii
  • Patent number: 7816277
    Abstract: A deposit forming method including ejecting droplets of a deposit forming material onto a substrate, thereby forming a deposit by the droplets on the substrate, is provided. The droplets are ejected along a direction inclined at a predetermined angle in a predetermined direction with respect to a normal line of the substrate and at a predetermined pitch in the predetermined direction. The predetermined angle is set in correspondence with the diameter of each of the droplets and the predetermined pitch in such a manner that the dimension of a dot formed by each droplet on the substrate in the predetermined direction becomes greater than or equal to the predetermined pitch.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: October 19, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Kei Hiruma, Osamu Kasuga, Yuji Iwata
  • Patent number: 7800209
    Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Yukihiro Kozaka, Nozomi Shimoishizaka, Toshiyuki Fukuda
  • Patent number: 7785982
    Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw, Devendra K. Sadana, Katherine L. Saenger
  • Patent number: 7781321
    Abstract: The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Michael P. Chudzik, Renee T. Mo
  • Patent number: 7776766
    Abstract: A trench embedding method comprising the steps of applying a composition for filling trenches which comprises a complex of an amine compound and aluminum hydride and an organic solvent to a substrate having trenches; and heating and/or exposing the composition to light to convert the complex into aluminum in the trenches so as to embed aluminum into the trenches. According to this method, even when aluminum is embedded into trenches having a fine and complex pattern, embedding performance is high and trenches in a large substrate can filled. This method can be carried out at a low cost.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: August 17, 2010
    Assignee: JSR Corporation
    Inventors: Tatsuya Sakai, Yasuo Matsuki
  • Patent number: 7767504
    Abstract: A method for forming a film pattern by disposing a functional liquid in a pattern forming region partitioned by a bank includes: disposing a first bank forming material to a substrate so as to form a first bank layer; and forming a second bank layer on the first bank layer, wherein the first bank forming material is an organic material while the second bank layer is made of a fluorine resin material covering the first bank layer.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: August 3, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Katsuyuki Moriya, Toshimitsu Hirai
  • Patent number: 7732349
    Abstract: The invention provides a manufacturing method of an insulating film having a plurality of pores, as well as a manufacturing method of a highly integrated semiconductor device with high yield. According to the invention, a porous insulating film is formed by forming a plurality of pores in an interlayer insulating film using a laser beam, which results in lower dielectric constant of the interlayer insulating film. In addition, a composition containing conductive particles is discharged onto the porous insulating film by a droplet discharge method typified by an ink jet printing method, and then baked to form a wire. As the laser beam, an ultrashort pulse laser beam is preferably used.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: June 8, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroko Yamamoto
  • Patent number: 7732330
    Abstract: The manufacturing method of the present invention includes steps of selectively forming a photocatalyst material or a material including an amino group by discharging a composition including the photocatalyst material or the material including an amino group; immersing the photocatalyst material or the material including an amino group in a solution including a plating catalyst material so as to adsorb or deposit the plating catalyst material onto the photocatalyst material or the material including an amino group; and immersing the plating catalyst material in a plating solution including a metal material so as to form a metal film on a surface of the photocatalyst material or the material including an amino group adsorbing or depositing the plating catalyst material, thereby manufacturing a semiconductor device. The pH of the solution including the plating catalyst material is adjusted in a range of 3 to 6.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: June 8, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Gen Fujii
  • Patent number: 7727863
    Abstract: Sonic radiation is applied to a wafer portion of the planar surface of a rotating, tilted wafer as it is being immersed into a liquid treatment bath. The portion includes the leading outer edge region of the wafer. The area of the wafer portion is significantly less than the total surface area of the planar wafer surface. Power density is minimized. As a result, bubbles are removed from the wafer surface and cavitation in the liquid bath is avoided. In some embodiments, the liquid bath is de-gassed to inhibit bubble formation.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: June 1, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Bryan L. Buckalew, Jonathan D. Reid, Johanes H. Sukamto, Frederick Dean Wilmot, Richard S. Hill
  • Patent number: 7718531
    Abstract: Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the plane of the main surface of the substrate. The method comprises obtaining a three-dimensional structure on the main surface, the three-dimensional structure comprising catalyst nanoparticles embedded in a non-catalytic matrix and selectively removing at least part of the non-catalytic matrix at the sidewalls of the three-dimensional structure to thereby expose at least one catalyst nanoparticle.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: May 18, 2010
    Assignee: IMEC
    Inventors: Aleksandar Radisic, Philippe M. Vereecken
  • Patent number: 7718550
    Abstract: The present invention involves a method and apparatus for depositing a silicon oxide onto a substrate from solution at low temperatures in a manner that produces homogeneous growth of the silicon oxide. The method generally comprises the following steps: (a) Chemically treating a substrate to activate it for growth of the silicon oxide. (b) Immersing the treated substrate into a bath with a reactive solution. (c) Regenerating the reactive solution to allow for continued growth of the silicon oxide. In another embodiment of the present invention, the apparatus includes a first container holding a reactive solution, a substrate on which the silicon oxide is deposited, a second container holding silica, and a means for adding silica to the reactive solution.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: May 18, 2010
    Assignee: William Marsh Rice University
    Inventors: Andrew R. Barron, Elizabeth Anne Whitsitt
  • Patent number: 7714354
    Abstract: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: May 11, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: David R. Evans, John W. Hartzell
  • Patent number: 7691731
    Abstract: A method of forming crystalline semiconducting layers on low melting or low softening point substrates includes the steps of providing an aqueous solution medium including a plurality of semiconductor nanoparticles dispersed therein having a median size less than 10 nm, and applying the solution medium to at least one region of a substrate to be coated. The substrate has a melting or softening point of <200° C. The solution medium is evaporated and the at least one region is laser irradiated for fusing the nanoparticles followed by annealing to obtain a continuous film having a recrystallized microstructure. An article includes a polycrystalline semiconducting layer including a plurality of crystallites predominately in the size range of 2 to 50 ?m, and a substrate having a melting or softening point of <200° C. supporting the semiconducting layer.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: April 6, 2010
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Sachin M. Bet, Aravinda Kar
  • Patent number: 7670950
    Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ions, an organic sulfonic acid or inorganic acid, or one or more organic compounds selected from among polarizers and/or depolarizers, and chloride ions.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: March 2, 2010
    Assignee: Enthone Inc.
    Inventors: Thomas B. Richardson, Yun Zhang, Chen Wang, Vincent Paneccasio, Jr., Cai Wang, Xuan Lin, Richard Hurtubise, Joseph A. Abys
  • Patent number: 7648897
    Abstract: To provide a method for manufacturing a wiring, a conductive layer, a display device, and a semiconductor device, each of which can meet a large sized substrate and which is manufactured with a higher throughput by using a material efficiently, the conductive layer is formed over the substrate having an insulating surface by discharging the conductive material, and heat treatment is performed by a lamp or a laser beam over the conductive layer. Furthermore, the conductive film is formed under reduced pressure according to the present invention.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: January 19, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuko Watanabe, Yasuyuki Arai
  • Patent number: 7635860
    Abstract: To increase productivity of organic thin-film transistors, in an organic thin-film transistor manufacturing equipment, a liquid containing at least either one of a wiring material and a semiconductor material is coated on a substrate to form a number of organic thin-film transistors. Substrate carrying means carry the substrate. The substrate is heated by a first heating means, and the temperature of the substrate is controlled by a controller. The liquid containing at least either one of the wiring material and the semiconductor material is heated by a second heating means, and the temperature of this liquid is controlled also by the controller.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: December 22, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Inoue, Akira Doi, Masahiko Ando
  • Patent number: 7633145
    Abstract: The invention provides a semiconductor device which can reliably restrict transmission/reception of signals or a power source voltage between a reader/writer when peeled off after stuck to an object. The semiconductor device of the invention includes an integrated circuit and an antenna formed on a support base. In the semiconductor device of the invention, a separating layer which is overlapped with the integrated circuit and the antenna sandwiching an insulating film is formed on the support base. A wiring for electrically connecting the integrated circuit and the antenna, a wiring for electrically connecting semiconductor elements in an integrated circuit, or a wiring which forms the antenna passes through the separating layer.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: December 15, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuyuki Arai, Mai Akiba, Yuko Tachimura, Yohei Kanno
  • Patent number: 7625493
    Abstract: In order to achieve low cost of manufacture of a display device by reducing the use of primary material used in a manufacturing process of a display device and saving labor taken for a vacuum process, according to the invention, liquid droplets containing conductive particles are ejected on a film being processed by using a first liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices, thereby a conductive film is formed. After that, a resist pattern is locally formed on the conductive film by using a second liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices. The conductive film is etched with the resist pattern as a mask to form a wiring.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: December 1, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20090291552
    Abstract: The invention provides a manufacturing method of a substrate having a film pattern including an insulating film, a semiconductor film, a conductive film and the like by simple steps, and also a manufacturing method of a semiconductor device which is low in cost with high throughput and yield. According to the invention, after forming a first protective film which has low wettability on a substrate, a material which has high wettability is applied or discharged on an outer edge of a first mask pattern, thereby a film pattern and a substrate having the film pattern are formed.
    Type: Application
    Filed: August 6, 2009
    Publication date: November 26, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinji MAEKAWA, Gen FUJII, Hiroko SHIROGUCHI, Masafumi MORISUE
  • Patent number: 7608476
    Abstract: A technique for high-resolution surface energy assisted patterning of semiconductor active layer islands on top of an array of predefined source-drain electrodes without requiring an additional process step for surface energy patterning.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: October 27, 2009
    Assignee: Plastic Logic Limited
    Inventors: Catherine Mary Ramsdale, Henning Sirringhaus, Timothy Allan Von Werne
  • Patent number: 7605082
    Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: October 20, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
  • Patent number: 7601639
    Abstract: The present invention provides, in one aspect, the present invention provides, in one embodiment, a method of conditioning a deposition chamber 100. This method comprises placing an undercoat on the walls of a deposition chamber 100 and depositing a pre-deposition coat over the undercoat with a plasma gas mixture conducted at a high pressure and with high gas flow.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: October 13, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Salvator F. Pavone, Jason J New
  • Patent number: 7595268
    Abstract: A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an internal wiring disposed to be exposed to outside; an insulating film formed on the semiconductor to expose the pads for power supply and the internal wirings; and re-distribution lines formed on the insulating film to connect between the exposed portions of the pads for power supply and the internal wiring.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: September 29, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwon Whan Han
  • Patent number: 7592267
    Abstract: This invention provides a method for manufacturing a semiconductor silicon substrate by use of carbon dioxide in a supercritical state, which method is capable of making the semiconductor silicon substrate highly reliable one. Specifically, this invention provides a method for manufacturing a semiconductor silicon substrate including at least two of: a cleaning step of cleaning a substrate to be treated in a presence of carbon dioxide in a supercritical state; a film forming step of forming at least one of a conducting film, an insulating film and barrier film on the substrate to be treated in the presence of carbon dioxide in the supercritical state; an etching step of etching the substrate to be treated in the presence of carbon dioxide in the supercritical state; and a resist removing step of removing a resist on the substrate to be treated in the presence of carbon dioxide in the supercritical state.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: September 22, 2009
    Assignee: Elpida Memory Inc.
    Inventor: Hiroyuki Ode
  • Patent number: 7585770
    Abstract: In a method of forming carbon nanotubes (CNTs) and a method of manufacturing a field emission display (FED) device using the CNTs, the method includes preparing a substrate on which a silicon layer is formed, sequentially forming a buffer layer and a catalyst metal layer on the silicon layer, partly forming metal silicide domains by diffusion between the silicon layer, the buffer layer and the catalyst metal layer by annealing the substrate, and growing CNTs on a surface of the catalyst metal layer.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: September 8, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Young-Jun Park, Ha-Jin Kim
  • Patent number: 7575952
    Abstract: A method of manufacturing a semiconductor device having an organic semiconductor film comprises a step of preparing a transparent substrate at least having an opaque gate electrode and a gate insulator thereover, a step of forming a layer containing metal-nano-particles as a conductive layer for a source electrode and a drain electrode to the thus prepared transparent substrate, a step of applying exposure to the transparent substrate on the side of a surface not mounted with the opaque gate electrode, a step of flushing away a portion other than the source electrode and the drain electrode in the layer containing the metal-nano-particles after the exposure, and a step of forming an organic semiconductor layer forming a channel portion. Lower and upper electrodes are positioned in self-alignment manner and thus no positional displacement occurs even if a printing method is used.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: August 18, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Arai, Shinichi Saito