Abstract: A plating apparatus allows a substrate holder to be serviced easily while ensuring easy access to the substrate holder and while a substrate is being processed in the plating apparatus. The plating apparatus includes a plating section for plating a substrate, a substrate holder for holding the substrate, a substrate holder transporter for holding and transporting the substrate holder, a stocker for storing the substrate holder, and a stocker setting section for storing the stocker therein. The stocker includes a moving mechanism for moving the stocker into and out of the stocker setting section.

Abstract: A charge transfer mechanism is used to locally deposit or remove material for a small structure. A local electrochemical cell is created without having to immerse the entire work piece in a bath. The charge transfer mechanism can be used together with a charged particle beam or laser system to modify small structures, such as integrated circuits or micro-electromechanical system. The charge transfer process can be performed in air or, in some embodiments, in a vacuum chamber.

Abstract: An object of the present invention is to provide a method for manufacturing a display device by improving the utilization efficiency of materials and simplifying manufacturing process. Another object of the invention is to provide a technique for forming a pattern such as a wiring having a predetermined shape included in a display device with good controllability. A method for manufacturing a wiring substrate of the invention includes the steps of: forming a first region having a subject material; modifying the surface of the subject material partly to form a second region having a boundary with respect to the first region; continuously discharging a composition containing a conductive material to a part of the first region across the boundary and the second region; solidifying the composition to form a conductive layer; and removing the conductive layer formed in a part of the first region across the boundary.

Abstract: Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 ?m or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Abstract: The present invention provides a method of forming a conductive electrode structure including: applying a conductive paste on a substrate; forming a conductive pattern having an outwardly convex shape by heat-treating the conductive paste; and forming a solder layer to conformally cover the conductive pattern.

Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.

Abstract: Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for this deposition process without adding footprint in the semiconductor fabrication plant.

Abstract: After a liquid chemical treatment is finished, in parallel with a washing away treatment and/or a drying treatment, by spraying from a nozzle for a cleaning liquid supplied by a cleaning line to an outer surface of a nozzle for a liquid chemical, crystals and the like of components of the liquid chemical adhered on the outer surface of the nozzle are removed. In the cleaning treatment, a spraying time of the cleaning liquid is five seconds to ten seconds. In addition, the components of the cleaning liquid is not specifically limited, however, since ammonium phosphate tends to be solved in purified water, if a liquid chemical containing ammonium phosphate is used, it is preferable to use purified water as the cleaning liquid. Depending on the components and the like of the liquid chemical, a solution that can solve the crystals and the like may be used in stead.

Abstract: A disclosed laminated structure includes a wettability-variable layer containing a wettability-variable material whose surface energy changes when energy is applied thereto and including at least a high-surface-energy area having high surface energy and a low-surface-energy area having low surface energy; and a conductive layer formed on the high-surface-energy area. The high-surface-energy area includes a first area and a second area extending from the first area and having a width smaller than that of the first area.

Abstract: A method for producing an electrically conducting metal contact on a semiconductor component having a coating on the surface of a semiconductor substrate. In order to keep transfer resistances low while maintaining good mechanical strength, the invention proposes applying a particle-containing fluid onto the coating, where the particles contain at least metal particles and glass frits, curing the fluid while simultaneously forming metal areas in the substrate through heat treatment, removing the cured fluid and the areas of the coating covered by the fluid, and depositing, for the purposes of forming the contact without using intermediate layers, electrically conducting material from a solution onto areas of the semiconductor component in which the coating is removed while at the same time conductively connecting the metal areas present in said areas on the substrate.

Abstract: A method of providing solar cell electrode by electroless plating and an activator used therein are disclosed. The method of the present invention can be performed without silver paste, and comprises steps: (A) providing a silicon substrate; (B) contacting the silicon substrate with an activator, wherein the activator comprises: a noble metal or a noble metal compound, a thickening agent, and water; (C) washing the silicon substrate by a cleaning agent; (D) dipping the silicon substrate in an electroless nickel plating solution to perform electroless plating. The method of providing solar cell electrode by electroless plating of the present invention has high selectivity between silicon nitride and silicon, large working window, and is steady, easily to be controlled, therefore is suitable for being used in the fabrication of the electrodes of the solar cell substrate.

Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.

Abstract: The present invention discloses a display device and a manufacturing method thereof by which a manufacturing process can be simplified. Further, the present invention discloses technique for manufacturing a pattern such as a wiring into a desired shape with good controllability. A method for forming a pattern for constituting the display device according to the present invention comprises the steps of forming a first region and a second region; discharging a composition containing a pattern formation material to a region across the second region and the first region; and flowing a part of the composition discharged to the first region into the second region; wherein wettability with respect to the composition of the first region is lower than that of the second composition.

Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.

Abstract: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed.

Abstract: A circuit pattern is formed by following steps: forming a light-blocking mask over a major surface of a light-transmitting substrate, forming a first film in a first region over the substrate and the mask, forming a photocatalytic film in at least a part of the first region over the first film, changing wettability of the first film in a second region which is in the first region, being in contact with the photocatalytic film, and not overlapping the mask, by light irradiation from a back surface opposite to the major surface of the substrate, removing the photocatalytic film, and forming a composition including a pattern forming material in the second region.

Abstract: A deposit forming method including ejecting droplets of a deposit forming material onto a substrate, thereby forming a deposit by the droplets on the substrate, is provided. The droplets are ejected along a direction inclined at a predetermined angle in a predetermined direction with respect to a normal line of the substrate and at a predetermined pitch in the predetermined direction. The predetermined angle is set in correspondence with the diameter of each of the droplets and the predetermined pitch in such a manner that the dimension of a dot formed by each droplet on the substrate in the predetermined direction becomes greater than or equal to the predetermined pitch.

Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.

Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

Abstract: The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.

Abstract: A trench embedding method comprising the steps of applying a composition for filling trenches which comprises a complex of an amine compound and aluminum hydride and an organic solvent to a substrate having trenches; and heating and/or exposing the composition to light to convert the complex into aluminum in the trenches so as to embed aluminum into the trenches. According to this method, even when aluminum is embedded into trenches having a fine and complex pattern, embedding performance is high and trenches in a large substrate can filled. This method can be carried out at a low cost.

Abstract: A method for forming a film pattern by disposing a functional liquid in a pattern forming region partitioned by a bank includes: disposing a first bank forming material to a substrate so as to form a first bank layer; and forming a second bank layer on the first bank layer, wherein the first bank forming material is an organic material while the second bank layer is made of a fluorine resin material covering the first bank layer.

Abstract: The invention provides a manufacturing method of an insulating film having a plurality of pores, as well as a manufacturing method of a highly integrated semiconductor device with high yield. According to the invention, a porous insulating film is formed by forming a plurality of pores in an interlayer insulating film using a laser beam, which results in lower dielectric constant of the interlayer insulating film. In addition, a composition containing conductive particles is discharged onto the porous insulating film by a droplet discharge method typified by an ink jet printing method, and then baked to form a wire. As the laser beam, an ultrashort pulse laser beam is preferably used.

Abstract: The manufacturing method of the present invention includes steps of selectively forming a photocatalyst material or a material including an amino group by discharging a composition including the photocatalyst material or the material including an amino group; immersing the photocatalyst material or the material including an amino group in a solution including a plating catalyst material so as to adsorb or deposit the plating catalyst material onto the photocatalyst material or the material including an amino group; and immersing the plating catalyst material in a plating solution including a metal material so as to form a metal film on a surface of the photocatalyst material or the material including an amino group adsorbing or depositing the plating catalyst material, thereby manufacturing a semiconductor device. The pH of the solution including the plating catalyst material is adjusted in a range of 3 to 6.

Abstract: Sonic radiation is applied to a wafer portion of the planar surface of a rotating, tilted wafer as it is being immersed into a liquid treatment bath. The portion includes the leading outer edge region of the wafer. The area of the wafer portion is significantly less than the total surface area of the planar wafer surface. Power density is minimized. As a result, bubbles are removed from the wafer surface and cavitation in the liquid bath is avoided. In some embodiments, the liquid bath is de-gassed to inhibit bubble formation.

Abstract: The present invention involves a method and apparatus for depositing a silicon oxide onto a substrate from solution at low temperatures in a manner that produces homogeneous growth of the silicon oxide. The method generally comprises the following steps: (a) Chemically treating a substrate to activate it for growth of the silicon oxide. (b) Immersing the treated substrate into a bath with a reactive solution. (c) Regenerating the reactive solution to allow for continued growth of the silicon oxide. In another embodiment of the present invention, the apparatus includes a first container holding a reactive solution, a substrate on which the silicon oxide is deposited, a second container holding silica, and a means for adding silica to the reactive solution.

Abstract: Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the plane of the main surface of the substrate. The method comprises obtaining a three-dimensional structure on the main surface, the three-dimensional structure comprising catalyst nanoparticles embedded in a non-catalytic matrix and selectively removing at least part of the non-catalytic matrix at the sidewalls of the three-dimensional structure to thereby expose at least one catalyst nanoparticle.

Abstract: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).

Abstract: A method of forming crystalline semiconducting layers on low melting or low softening point substrates includes the steps of providing an aqueous solution medium including a plurality of semiconductor nanoparticles dispersed therein having a median size less than 10 nm, and applying the solution medium to at least one region of a substrate to be coated. The substrate has a melting or softening point of <200° C. The solution medium is evaporated and the at least one region is laser irradiated for fusing the nanoparticles followed by annealing to obtain a continuous film having a recrystallized microstructure. An article includes a polycrystalline semiconducting layer including a plurality of crystallites predominately in the size range of 2 to 50 ?m, and a substrate having a melting or softening point of <200° C. supporting the semiconducting layer.

Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ions, an organic sulfonic acid or inorganic acid, or one or more organic compounds selected from among polarizers and/or depolarizers, and chloride ions.

Abstract: To provide a method for manufacturing a wiring, a conductive layer, a display device, and a semiconductor device, each of which can meet a large sized substrate and which is manufactured with a higher throughput by using a material efficiently, the conductive layer is formed over the substrate having an insulating surface by discharging the conductive material, and heat treatment is performed by a lamp or a laser beam over the conductive layer. Furthermore, the conductive film is formed under reduced pressure according to the present invention.

Abstract: To increase productivity of organic thin-film transistors, in an organic thin-film transistor manufacturing equipment, a liquid containing at least either one of a wiring material and a semiconductor material is coated on a substrate to form a number of organic thin-film transistors. Substrate carrying means carry the substrate. The substrate is heated by a first heating means, and the temperature of the substrate is controlled by a controller. The liquid containing at least either one of the wiring material and the semiconductor material is heated by a second heating means, and the temperature of this liquid is controlled also by the controller.

Abstract: The invention provides a semiconductor device which can reliably restrict transmission/reception of signals or a power source voltage between a reader/writer when peeled off after stuck to an object. The semiconductor device of the invention includes an integrated circuit and an antenna formed on a support base. In the semiconductor device of the invention, a separating layer which is overlapped with the integrated circuit and the antenna sandwiching an insulating film is formed on the support base. A wiring for electrically connecting the integrated circuit and the antenna, a wiring for electrically connecting semiconductor elements in an integrated circuit, or a wiring which forms the antenna passes through the separating layer.

Abstract: In order to achieve low cost of manufacture of a display device by reducing the use of primary material used in a manufacturing process of a display device and saving labor taken for a vacuum process, according to the invention, liquid droplets containing conductive particles are ejected on a film being processed by using a first liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices, thereby a conductive film is formed. After that, a resist pattern is locally formed on the conductive film by using a second liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices. The conductive film is etched with the resist pattern as a mask to form a wiring.

Abstract: The invention provides a manufacturing method of a substrate having a film pattern including an insulating film, a semiconductor film, a conductive film and the like by simple steps, and also a manufacturing method of a semiconductor device which is low in cost with high throughput and yield. According to the invention, after forming a first protective film which has low wettability on a substrate, a material which has high wettability is applied or discharged on an outer edge of a first mask pattern, thereby a film pattern and a substrate having the film pattern are formed.

Abstract: A technique for high-resolution surface energy assisted patterning of semiconductor active layer islands on top of an array of predefined source-drain electrodes without requiring an additional process step for surface energy patterning.

Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

Abstract: The present invention provides, in one aspect, the present invention provides, in one embodiment, a method of conditioning a deposition chamber 100. This method comprises placing an undercoat on the walls of a deposition chamber 100 and depositing a pre-deposition coat over the undercoat with a plasma gas mixture conducted at a high pressure and with high gas flow.

Abstract: A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an internal wiring disposed to be exposed to outside; an insulating film formed on the semiconductor to expose the pads for power supply and the internal wirings; and re-distribution lines formed on the insulating film to connect between the exposed portions of the pads for power supply and the internal wiring.

Abstract: This invention provides a method for manufacturing a semiconductor silicon substrate by use of carbon dioxide in a supercritical state, which method is capable of making the semiconductor silicon substrate highly reliable one. Specifically, this invention provides a method for manufacturing a semiconductor silicon substrate including at least two of: a cleaning step of cleaning a substrate to be treated in a presence of carbon dioxide in a supercritical state; a film forming step of forming at least one of a conducting film, an insulating film and barrier film on the substrate to be treated in the presence of carbon dioxide in the supercritical state; an etching step of etching the substrate to be treated in the presence of carbon dioxide in the supercritical state; and a resist removing step of removing a resist on the substrate to be treated in the presence of carbon dioxide in the supercritical state.

Abstract: In a method of forming carbon nanotubes (CNTs) and a method of manufacturing a field emission display (FED) device using the CNTs, the method includes preparing a substrate on which a silicon layer is formed, sequentially forming a buffer layer and a catalyst metal layer on the silicon layer, partly forming metal silicide domains by diffusion between the silicon layer, the buffer layer and the catalyst metal layer by annealing the substrate, and growing CNTs on a surface of the catalyst metal layer.

Abstract: A method of manufacturing a semiconductor device having an organic semiconductor film comprises a step of preparing a transparent substrate at least having an opaque gate electrode and a gate insulator thereover, a step of forming a layer containing metal-nano-particles as a conductive layer for a source electrode and a drain electrode to the thus prepared transparent substrate, a step of applying exposure to the transparent substrate on the side of a surface not mounted with the opaque gate electrode, a step of flushing away a portion other than the source electrode and the drain electrode in the layer containing the metal-nano-particles after the exposure, and a step of forming an organic semiconductor layer forming a channel portion. Lower and upper electrodes are positioned in self-alignment manner and thus no positional displacement occurs even if a printing method is used.

Abstract: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.

Abstract: A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom composite electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer and the bottom composite electrode, and a top electrode layer deposited over the active material layer. The device uses a chemical or electrochemical liquid phase deposition process to selectively and conformally fill the insulative layer opening with the conductive bottom composite electrode layer. Conformally filling the conductive material within the opening reduces structural irregularities within the opening thereby increasing material density and resistivity within the device and thereby improving device performance and reducing programming current.

Abstract: In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed.

Abstract: A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than ?200 nm, a conductive layer being present on at least a portion of said surface, (b) filling said recessed feature with a conductive material, and (c) prior to filling said recessed feature with said conductive material, treating said surface with an accelerator.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A method of forming a film pattern by disposing functional liquid on a substrate includes: forming banks on the substrate; disposing the functional liquid in regions partitioned by the banks; and drying the functional liquid disposed on the substrate. The forming of the banks includes forming a thin film on the substrate, the thin film being made of a material for forming the banks, performing lyophobic treatment on a surface of the thin film, and patterning the thin film into the shapes of the banks.

Abstract: A slit forming process with respect to a coated film, includes: forming a step pattern having an end part on a substrate; coating a liquid material for forming a coated film on the substrate in the manner of covering at least the end part of the step pattern; and forming the coated film by drying the coated liquid material, together with forming a slit at a position corresponding to the end part of the step pattern.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.