From A Liquid, E.g., Electrolytic Deposition (epo) Patents (Class 257/E21.174)
  • Patent number: 7575952
    Abstract: A method of manufacturing a semiconductor device having an organic semiconductor film comprises a step of preparing a transparent substrate at least having an opaque gate electrode and a gate insulator thereover, a step of forming a layer containing metal-nano-particles as a conductive layer for a source electrode and a drain electrode to the thus prepared transparent substrate, a step of applying exposure to the transparent substrate on the side of a surface not mounted with the opaque gate electrode, a step of flushing away a portion other than the source electrode and the drain electrode in the layer containing the metal-nano-particles after the exposure, and a step of forming an organic semiconductor layer forming a channel portion. Lower and upper electrodes are positioned in self-alignment manner and thus no positional displacement occurs even if a printing method is used.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: August 18, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Arai, Shinichi Saito
  • Patent number: 7572723
    Abstract: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: August 11, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Varughese Mathew, Eddie Acosta, Ritwik Chatterjee, Sam S. Garcia
  • Patent number: 7566643
    Abstract: A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom composite electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer and the bottom composite electrode, and a top electrode layer deposited over the active material layer. The device uses a chemical or electrochemical liquid phase deposition process to selectively and conformally fill the insulative layer opening with the conductive bottom composite electrode layer. Conformally filling the conductive material within the opening reduces structural irregularities within the opening thereby increasing material density and resistivity within the device and thereby improving device performance and reducing programming current.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: July 28, 2009
    Assignee: Ovonyx, Inc.
    Inventors: Wolodymyr Czubatyi, Tyler Lowrey, Ed Spall
  • Patent number: 7566653
    Abstract: In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel C. Edelstein
  • Publication number: 20090170306
    Abstract: A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than ?200 nm, a conductive layer being present on at least a portion of said surface, (b) filling said recessed feature with a conductive material, and (c) prior to filling said recessed feature with said conductive material, treating said surface with an accelerator.
    Type: Application
    Filed: March 30, 2006
    Publication date: July 2, 2009
    Applicant: FREESCALE SEMICONDUTOR INC
    Inventor: John C Flake
  • Patent number: 7553754
    Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: June 30, 2009
    Assignee: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Hiroshi Gotoh, Toshihiro Kugimiya, Junichi Nakai, Katsufumi Tomihisa
  • Patent number: 7547567
    Abstract: A method of forming a film pattern by disposing functional liquid on a substrate includes: forming banks on the substrate; disposing the functional liquid in regions partitioned by the banks; and drying the functional liquid disposed on the substrate. The forming of the banks includes forming a thin film on the substrate, the thin film being made of a material for forming the banks, performing lyophobic treatment on a surface of the thin film, and patterning the thin film into the shapes of the banks.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: June 16, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Katsuyuki Moriya, Toshimitsu Hirai
  • Patent number: 7544614
    Abstract: A slit forming process with respect to a coated film, includes: forming a step pattern having an end part on a substrate; coating a liquid material for forming a coated film on the substrate in the manner of covering at least the end part of the step pattern; and forming the coated film by drying the coated liquid material, together with forming a slit at a position corresponding to the end part of the step pattern.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: June 9, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka
  • Patent number: 7541279
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: June 2, 2009
    Assignee: Dongbu Electronics Co., Ltd
    Inventors: Sang Chul Kim, Jae Won Han
  • Patent number: 7537976
    Abstract: The invention provides a manufacturing method of a circular thin film transistor of which shape is more controlled than the conventional case, while simplifying the steps and reducing the manufacturing time and cost by forming a circular thin film transistor by a maskless process such as a droplet discharge method. In the invention, a circular thin film transistor having a circular electrode is formed by stacking concentric circular thin films over a substrate by a maskless process such as a droplet discharge method. Moreover, a circular thin film transistor having a circular semiconductor layer may be formed by stacking concentric circular thin films over a substrate by a maskless process such as a droplet discharge method.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 26, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Patent number: 7534724
    Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wing formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: May 19, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Nakamura, Kiyofumi Ogino
  • Publication number: 20090124051
    Abstract: In a thin-film field effect transistor with a MIS structure, the materials of which the semiconductor and insulating layers are made are polymers which are dissolvable in organic solvents and have a weight average molecular weight of more than 2,000 to 1,000,000. Use of polymers for both the semiconductor layer and insulating layer of TFT eliminates such treatments as patterning and etching using photoresists in the prior art circuit-forming technology, reduces the probability of TFT defects and achieves a reduction of TFT manufacture cost.
    Type: Application
    Filed: January 8, 2009
    Publication date: May 14, 2009
    Inventor: Ikuo FUKUI
  • Patent number: 7524764
    Abstract: A method of forming a film pattern by disposing a functional liquid on a substrate, includes: forming banks on the substrate; disposing the functional liquid in areas partitioned by the banks; and drying the functional liquid disposed on the substrate, wherein the forming of the banks including: forming a plurality of layers made of inorganic materials; patterning a plurality of the layers by using an organic mask; and removing the organic mask.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: April 28, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Toshimitsu Hirai
  • Publication number: 20090101996
    Abstract: A nanoelectronic device includes a nanostructure, such as a nanotube or network of nanotube, disposed on a substrate. Nanoparticles are disposed on or adjacent to the nanostructure so as to operatively effect the electrical properties of the nanostructure. The nanoparticles may be composed of metals, metal oxides or salts and nanoparticles composed of different materials may be present. The amount of nanoparticles may be controlled to preserve semiconductive properties of the nanostructure, and the substrate immediately adjacent to the nanostructure may remain substantially free of nanoparticles. A method for fabricating the device includes electrodeposition of the nanoparticles using one of more solutions of dissolved ions while providing an electric current to the nanostructures but not to the surrounding substrate.
    Type: Application
    Filed: November 10, 2008
    Publication date: April 23, 2009
    Applicant: NANOMIX, INC.
    Inventors: Keith BRADLEY, Alona J. Davis, Jean-Christophe P. Gabriel, Tzong-Ru Han, Vikram Joshi, Alexander Star
  • Patent number: 7521802
    Abstract: A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2 film provided on the silicon substrate, copper films embedded in the SiO2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO2 film, and SiON films covering an upper face of the TiN films.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: April 21, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Toshiyuki Takewaki, Mari Watanabe
  • Patent number: 7517782
    Abstract: By performing an electroless deposition and an electro deposition process in situ, highly reliable metallizations may be provided, wherein limitations with respect to contaminations and device scaling, encountered by conventional chemical vapor deposition (CVD), atomic layer deposition (ALD) and physical vapor deposition (PVD) techniques for the formation of seed layers may be overcome. In some embodiments, a barrier layer is also deposited on the basis of a wet chemical deposition process.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Axel Preusse, Susanne Wehner, Markus Nopper
  • Patent number: 7482691
    Abstract: A semiconductor device and a method of fabricating a semiconductor device is provided. The semiconductor device can include a semiconductor substrate; an interlayer dielectric layer having a damascene pattern formed on the semiconductor substrate; a diffusion barrier formed in the damascene pattern and made of a trivalent material; a seed layer formed on the diffusion barrier; and a copper interconnection formed on the seed layer. In one embodiment, the trivalent material is CoFeB.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: January 27, 2009
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Sung Joong Joo
  • Publication number: 20090017622
    Abstract: A chemical treatment apparatus and a method for performing a chemical treatment of a wafer, etc., by supplying a chemical via a cell. The apparatus includes a cylindrical inner cell and a cylindrical outer cell with open ends disposed at an outer circumference of the inner cell. The outer cell is axially movable to vary the width of a slit formed between a bottom end of the outer cell and a top surface of the substrate-holding means by the axial movement, thereby adjusting the discharge rate of the chemical and varying the pressure of the chemical.
    Type: Application
    Filed: September 26, 2008
    Publication date: January 15, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yoshiaki Tomari
  • Patent number: 7476559
    Abstract: A thin film pattern substrate on which a thin film pattern is formed by placing a functional liquid on the substrate, the thin film pattern includes a first domain area into which the functional liquid is infused and a second domain area on which the functional liquid infused into the first domain area flows, wherein the first domain area includes a plurality of linear patterns the width of which is narrower than the width of the first domain area, and the linear patterns forming the second domain area are connected to at least one of the plural linear patterns that constitute the first domain area.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: January 13, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Shinri Sakai, Toshimitsu Hirai
  • Patent number: 7470617
    Abstract: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Ramanan Chebiam, Chin-Chang Cheng, Damian Whitney, Harsono Simka
  • Patent number: 7465652
    Abstract: A method is provided for depositing a conductive material in a sub-micron recessed feature formed on a substrate. The method begins by depositing a barrier layer over a dielectric layer disposed on the substrate while under a vacuum of the type found in a vacuum chamber. A catalytic layer is deposited over the barrier layer without breaking the vacuum. A conductive material layer is deposited over the catalytic layer by electroless deposition.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: December 16, 2008
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Takeshi Nogami
  • Patent number: 7462514
    Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device having a semiconductor element capable of reducing a cost and improving a throughput with a minute structure, and further, a method for manufacturing a liquid crystal television and an EL television. According to one feature of the invention, a method for manufacturing a semiconductor device comprises the steps of: forming a light absorption layer over a substrate, forming a first region over the light absorption layer by using a solution, generating heat by irradiating the light absorption layer with laser light, and forming a first film pattern by heating the first region with the heat.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: December 9, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroko Shiroguchi, Yoshiaki Yamamoto
  • Patent number: 7456102
    Abstract: Disclosed is a procedure for bottom-up fill of electroless copper film in sub-micron integrated circuit features. By repeatedly placing an integrated circuit wafer in an electroless bath, a transient period of time of accelerated growth in the feature is repeated to achieve many small layers of deposition, each of which is thicker near the base of the feature. The net result is filing of the feature from the bottom-up fill without formation of voids. The electroless bath employed to form the continuous electroless copper film may include a reducing agent, a complexing agent, a source of copper ions, a pH adjuster, and optionally one or more surfactants and/or stabilizers.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: November 25, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Seshasayee Varadarajan, Jian Zhou
  • Publication number: 20080258270
    Abstract: The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable organomagnesium compound and/or of at least one hydrolysable magnesium salt, capable of forming a homogeneous polymer layer of magnesium oxyhydroxide by hydrolysis/condensation reaction with water; depositing the treatment solution of the hydrolysable organomagnesium compound or of the hydrolysable magnesium salt, onto a surface to form a magnesium oxide-based layer; and densifying the layer formed at a temperature of less than or equal to 1000° C.
    Type: Application
    Filed: October 12, 2005
    Publication date: October 23, 2008
    Applicant: Commissariat a L'Energie Atomique
    Inventors: Celine Bondoux, Philippe Prene, Philippe Belleville, Robert Jerisian
  • Patent number: 7432200
    Abstract: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally consists of providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. Various processing steps and structures may be utilized in the fabrication of the interconnect, which may include but is not limited to forming barrier layers, utilizing seed materials, utilizing activation materials, and treating the dielectric material to be receptive to electroless deposition.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: October 7, 2008
    Assignee: Intel Corporation
    Inventors: Shaestagir Chowdhury, Chi-Hwa Tsang
  • Patent number: 7429530
    Abstract: A method of forming a pattern of a functional layer on a surface of a substrate, where a pattern region, to which the pattern is provided, is edged with a boundary layer, and has a first region and a second region communicated with the first region and having a narrower width than the first region, the method includes: providing an intermediate layer having adhesiveness with the substrate and lyophilicity with a functional fluid to the first and the second regions; ejecting a droplet of the functional fluid to the first region; and allowing the droplet of the functional fluid ejected to the first region to automatically flow to the second region with the lyophilicity with the intermediate layer.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: September 30, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Katsuyuki Moriya, Toshimitsu Hirai
  • Patent number: 7417321
    Abstract: Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: August 26, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jung-Chih Tsao, Kei-Wei Chen, Ying-Jing Lu, Yu-Sheng Wang, Yu-Ku Lin
  • Patent number: 7381633
    Abstract: A method of making a patterned metal oxide film includes jetting a sol-gel solution on a substrate. The sol-gel solution is dried to form a gel layer on the substrate. Portions of the gel layer are irradiated to pattern the gel layer and to form exposed portions. Irradiation causes the exposed portions of the gel layer to become at least one of substantially condensed to an oxide, substantially densified, substantially cured, and combinations thereof. The unexposed portions of the gel layer are removed, thereby forming the patterned metal oxide film.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: June 3, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: John O. Thompson, Curt Lee Nelson, David Punsalan
  • Patent number: 7358174
    Abstract: A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In addition, an interconnection structure may be provided on the conductive barrier layer with the conductive barrier layer being between the interconnection structure and the metal pad. Moreover, the interconnection structure and the conductive barrier layer may include different materials. Related structures are also discussed.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: April 15, 2008
    Assignee: Amkor Technology, Inc.
    Inventor: J. Daniel Mis
  • Patent number: 7332432
    Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: February 19, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Nakamura, Kiyofumi Ogino
  • Patent number: 7320937
    Abstract: The present invention is a reliable method of electroless-plating integrated circuit die that achieves high yield. Die are attached to a holder using a polyimide adhesive to eliminate voltage differences on bond pads which would otherwise interfere with the plating. The die are aggressively cleaned using multiple cleaning solutions, one heated to a user-defined temperature. Each cleaning is followed by an aggressive rinse in de-ionized water. Die are immersed into multiple metal solutions at user-definable temperatures. Each immersion is followed by an aggressive rinse in de-ionized water, one with heated de-ionized water.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: January 22, 2008
    Assignee: The United States of America as represented by the National Security Agency
    Inventors: Rathindra N. Pal, Kingsley R. Berlin
  • Publication number: 20070285592
    Abstract: A method for fabricating a system for displaying images is provided, wherein the system comprises a low temperature polysilicon thin film transistor (LTPS-TFT) substrate. The method comprises providing a substrate comprising a first metal layer and a silicon film layer. The silicon film layer is illuminated t by a laser light having a wavelength larger than 400 nm. The silicon film layer is heated to crystallize by absorbing a part of the laser light, and is heated to re-crystallize by absorbing another part of the laser light, which passes through the silicon film layer and is reflected from the first metal layer to the silicon film layer.
    Type: Application
    Filed: April 16, 2007
    Publication date: December 13, 2007
    Inventors: Yoshihiro Morimoto, Ryan Lee, Hanson Liu
  • Patent number: 7306962
    Abstract: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: December 11, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: David R. Evans, John W. Hartzell
  • Patent number: 7285494
    Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: October 23, 2007
    Assignee: Intel Corporation
    Inventors: Chin-Chang Cheng, Valery M. Dubin
  • Patent number: 7273813
    Abstract: A method and cleaning solution that removes contaminants from a dielectric material and polished surfaces of copper interconnect structures prior to an electroless deposition of a capping layer without substantially adversely affecting the interconnect formed therefrom are disclosed. The cleaning solution includes combinations of a core mixture and sulfuric acid or sulfonic compounds such as sulfonic acids that include methanesulfonic acid. In one embodiment, the core mixture includes a citric acid solution and a pH adjuster such as tetra-methyl ammonium hydroxide or ammonia. One embodiment of the method includes providing a planarized substrate, applying the cleaning solution to the substrate to simultaneously clean at least one metal feature and a dielectric material of the substrate, and depositing the metal capping layer selectively on the at least one metal feature using electroless deposition.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: September 25, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Ramin Emami, Timothy Weidman, Sergey Lopatin, Hongbin Fang, Arulkumar Shanmugasundram
  • Patent number: 7262504
    Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Chin-Chang Cheng, Valery M. Dubin
  • Patent number: 7241690
    Abstract: The present invention provides, in one aspect, a method of conditioning a deposition chamber 100. An undercoat is placed on the walls of a deposition chamber 100 and a pre-deposition coat is deposited over the undercoat with a plasma gas mixture conducted at a high pressure and with high gas flow.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: July 10, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Salvator F. Pavone, Jason J. New
  • Patent number: 7232747
    Abstract: A method of bumping a wafer for facilitating bonding of bond wires to elevate the bond location above the passivation layer. The wafer is bumped by disposing the wafer in at least one electroless bath having a nickel-containing solution therein, wherein bumps having a nickel-containing material are formed simultaneously on the exposed bond pads to an elevation sufficient to prevent damage to a passivation layer surrounding the bond pads by contact of a wire bonding capillary. A gold or palladium cap may optionally be formed over the nickel-containing material of the bumps. A method of forming a semiconductor device assembly is also disclosed.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: June 19, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Jerry M. Brooks
  • Publication number: 20070120273
    Abstract: A separable connection is created between at least one transfer support and the conductor structure. The transfer support including the conductor structure and the substrate are joined together such that a connection that is stronger than the separable connection between the transfer support and the conductor structure is created between the conductor structure and the substrate. The separable connection between the transfer support and the conductor structure of the transfer support is separated while the connection between the conductor structure and the substrate remains intact. The method is particularly suitable for laterally disposing conductor structures comprising nanotubes at relatively low temperatures (T<600° C.), resulting in a substrate with a conductor structure which is connected to the substrate on a contact surface of the substrate and at least one additional contact surface of the substrate.
    Type: Application
    Filed: January 26, 2005
    Publication date: May 31, 2007
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Gerald Eckstein, Wolfram Wersing
  • Patent number: 7220682
    Abstract: A method for fabricating a pattern on a substrate, includes the steps of forming banks according to formation areas of the pattern on the substrate, disposing a first function liquid between the banks, disposing a second function liquid on the first function liquid, and applying predetermined treatments to the first and the second function liquids which are disposed between the banks so as to form the pattern with plural materials stacked one on the other.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: May 22, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Toshimitsu Hirai
  • Patent number: 7205664
    Abstract: A semiconductor device including a multilevel wiring with a small interwiring capacitance is provided by comprising a wiring, a conductive film formed on an upper surface of the wiring to prevent diffusion of a wiring material, and an insulating film which is constituted of low dielectric constant insulating films stacked to form at least two layers, an interface thereof being positioned in a side face of the wiring.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: April 17, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumichi Tsumura, Takamasa Usui
  • Patent number: 7179716
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: February 20, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7169705
    Abstract: A plating method is capable of depositing a plated film having excellent in-plane uniformity with respect to a thin seed layer and excellent embeddability with respect to fine damascene structures. The plating method includes: positioning an electric resistor between a conductive layer formed on at least a portion of a surface of a substrate and an anode; introducing respectively a plating solution into a space between the conductive layer and the anode on a conductive layer side, and an anode solution into a space between the conductive layer and the anode on an anode side, thereby filling the space with a plating bath composed of the plating solution and the anode solution, with the plating solution containing 25 to 75 g/L of copper ions and at least 0.4 mole/L of an organic acid or an inorganic acid, and the anode solution being of the same composition as the plating solution, or containing 0 to 75 g/L of copper ions and at most 0.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: January 30, 2007
    Assignee: Ebara Corporation
    Inventors: Kunihito Ide, Koji Mishima, Hiroyuki Kanda, Hidenao Suzuki, Kazufumi Nomura
  • Patent number: 7141492
    Abstract: The invention provides a method of forming a high-performance thin-film at low cost using a liquid material in safety, an apparatus to form a thin-film, a method of manufacturing a semiconductor device, an electro-optical unit, and an electronic apparatus. An apparatus to form a thin-film includes a coating unit to apply a liquid material containing a thin-film component onto a substrate and also includes heat-treating units to heat the substrate applied with the liquid material. The coating unit and the heat-treating units each include a control device to control the atmosphere in a treating chamber to treat the substrate.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: November 28, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka