Etching Of Group Iii-v Compound (epo) Patents (Class 257/E21.22)
  • Patent number: 10001480
    Abstract: A photo-electrochemical bio-sensor uses a semiconductor heterostructure located in an etching solution. An outer layer of the heterostructure is functionalized, such as with a self-assembled monolayer, to provide adherence of a charged molecule of interest. When contacted by a test solution, the functionalization immobilizes a quantity of the molecule that corresponds to its concentration in the test solution. The heterostructure undergoes photocorrosion when illuminated by a laser at a rate corresponding to the quantity of immobilized charged molecules. The rate of photocorrosion is monitored to determine the concentration of the molecule in the test solution. The monitoring may make use of a photoluminescent material in the heterostructure that emits photoluminescence in response to the laser illumination. The photoluminescence changes with the advancement of the photocorrosion, and the change is therefore indicative of the concentration of the molecule in the test solution.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: June 19, 2018
    Inventor: Jan J. Dubowski
  • Patent number: 8871649
    Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignees: GLOBALFOUNDRIES Inc., Renesas Electronics Corporation, International Business Machines Corporation
    Inventors: Linus Jang, Yoshinori Matsui, Chiahsun Tseng
  • Patent number: 8679922
    Abstract: The method includes a step of forming a mask having an opening, for forming an opening in multiple insulating films, above a semiconductor substrate on which a member becoming a first insulating film, a member becoming a second insulating film being different from the member becoming the first insulating film, a member becoming a third insulating film, and a member becoming a fourth insulating film being different from the member becoming the third insulating film are stacked in this order; a first step of continuously removing the member becoming the fourth insulating film and the member becoming the third insulating film at a portion corresponding to the opening of the mask; and a second step of removing the member becoming the second insulating film, after the first step, at a portion corresponding to the opening of the mask.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaharu Kondo, Takashi Usui
  • Patent number: 8536061
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisataka Hayashi, Yusuke Kasahara, Tsubasa Imamura
  • Patent number: 8420543
    Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: April 16, 2013
    Assignee: National Chiao Tung University
    Inventors: Wei-I Lee, Yen-Hsien Yeh, Yin-Hao Wu, Tzu-Yi Yu
  • Patent number: 8415253
    Abstract: Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 9, 2013
    Assignee: International Business Machinees Corporation
    Inventors: Thomas N. Adam, Stephen W. Bedell, Alexander Reznicek, Devendra K. Sadana
  • Patent number: 8313966
    Abstract: Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: November 20, 2012
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventor: Zetian Mi
  • Patent number: 8279615
    Abstract: A method for producing an encapsulation module and/or for encapsulating a micromechanical arrangement, wherein electronic connection provisions are formed from a blank of electrically conductive semiconductor material, by one or more structuring processes and/or etching processes, wherein, in the course of forming the electronic connection provisions, a pedestal of the semiconductor material arises, on which the electronic connection provisions are arranged, wherein the latter are subsequently embedded with an embedding material and the embedding material and/or the semiconductor pedestal are removed after the embedding to an extent such that a defined number of the electronic connection provisions have electrical contacts on at least one of the outer surfaces of the encapsulation module thus produced, wherein upon forming the electronic connection provisions, on the pedestal of the semiconductor material, an insular material hump is formed, on which a plated-through hole is arranged in each case, and which e
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: October 2, 2012
    Assignee: Continental Teves AG & Co. oHG
    Inventors: Bernhard Schmid, Roland Hilser, Heikki Kuisma, Altti Torkkeli
  • Patent number: 8263500
    Abstract: A method for fabricating a semiconductor laser device, by etching facets using a photoelectrochemical (PEC) etch, so that the facets are sufficiently smooth to support optical modes within a cavity bounded by the facets.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: September 11, 2012
    Assignee: The Regents of the University of California
    Inventors: Adele C. Tamboli, Evelyn L. Hu, Steven P. DenBaars, Arpan Chakraborty
  • Patent number: 8252662
    Abstract: A method for manufacturing a plurality light emitting diodes includes providing a gallium nitride containing bulk crystalline substrate material configured in a non-polar or semi-polar crystallographic orientation, forming an etch stop layer, forming an n-type layer overlying the etch stop layer, forming an active region, a p-type layer, and forming a metallization. The method includes removing a thickness of material from the backside of the bulk gallium nitride containing substrate material. A plurality of individual LED devices are formed from at least a sandwich structure comprising portions of the metallization layer, the p-type layer, active layer, and the n-type layer. The LED devices are joined to a carrier structure.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: August 28, 2012
    Assignee: Soraa, Inc.
    Inventors: Christiane Poblenz, Mathew C. Schmidt, Daniel F. Feezell, James W. Raring, Rajat Sharma
  • Publication number: 20120184102
    Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.
    Type: Application
    Filed: May 18, 2011
    Publication date: July 19, 2012
    Applicant: National Chiao Tung University
    Inventors: Wei-I Lee, Kuei-Ming Chen, Yin-Hao Wu, Yen-Hsien Yeh
  • Patent number: 8124497
    Abstract: A method of manufacturing a nitride semiconductor device is disclosed. The method includes forming a gallium nitride (GaN) epitaxial layer on a first support substrate, forming a second support substrate on the GaN epitaxial layer, forming a passivation layer on a surface of the other region except for the first support substrate, etching the first support substrate by using the passivation layer as a mask, and removing the passivation layer and thereby exposing the second support substrate and the GaN epitaxial layer.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: February 28, 2012
    Assignee: Siltron, Inc.
    Inventors: Yong-Jin Kim, Dong-Kun Lee, Doo-Soo Kim, Ho-Jun Lee, Kye-Jin Lee
  • Publication number: 20120034785
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).
    Type: Application
    Filed: March 11, 2011
    Publication date: February 9, 2012
    Inventors: Hisataka HAYASHI, Yusuke Kasahara, Tsubasa Imamura
  • Publication number: 20120034787
    Abstract: The present invention provides an etching solution for revealing defects in a germanium layer, a method for revealing defects in a germanium layer using such an etching solution and to a method for making such an etching solution. The etching solution according to embodiments of the present invention is able to exhibit an etch rate of between 4 nm·min?1 and 450 nm·min?1, which makes it suitable to be used for revealing defects in a thin layer of germanium, i.e. in a layer of germanium with a thickness of between 20 nm and 10 ?m, for example between 20 nm and 2 ?m, between 20 nm and 1 ?m or between 20 nm and 200 nm.
    Type: Application
    Filed: October 18, 2011
    Publication date: February 9, 2012
    Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)
    Inventors: Laurent Souriau, Valentina Terzieva
  • Patent number: 8101481
    Abstract: A spacer lithography process for creating negative features such as, for example, cut-lines, or trenches, and holes is provided. The negative spacer lithography process may be utilized along with positive spacer lithography to fabricate electronic devices or the like. In one embodiment, a process is provided for fabricating a 6-transistor Static Random-Access Memory (SRAM) cell or arrays of 6-transistor SRAM cells using only, or at least primarily, positive and negative spacer lithography.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: January 24, 2012
    Assignee: The Regents of the University of California
    Inventor: Andrew E. Carlson
  • Patent number: 8093082
    Abstract: A method of fabricating a photoelectric device of Group III nitride semiconductor, where the method comprises the steps of: forming a first Group III nitride semiconductor layer on a surface of a temporary substrate; patterning the first Group III nitride semiconductor layer using photolithography and etching processes; forming a second Group III nitride semiconductor layer on the patterned first Group III nitride semiconductor layer; forming a conductive layer on the second Group III nitride semiconductor layer; and releasing the temporary substrate by removing the first Group III nitride semiconductor layer to obtain a composite of the second Group III nitride semiconductor layer and the conductive layer.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: January 10, 2012
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Shih Cheng Huang, Po Min Tu, Ying Chao Yeh, Wen Yu Lin, Peng Yi Wu, Chih Peng Hsu, Shih Hsiung Chan
  • Patent number: 8048700
    Abstract: A semiconductor light-emitting device (LE1) comprises a multilayer structure LS generating light. This multilayer structure includes a plurality of laminated compound semiconductor layers (3 to 8) and has first and second main faces (61, 62) opposing each other. A first electrode (21) and a second electrode (31) are arranged on the first and second main faces, respectively. A film made of silicon oxide (10) is also formed on the first main face so as to cover the first electrode. A glass substrate (1) optically transparent to the light generated by the multilayer structure is secured to the multilayer structure through the film made of silicon oxide.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: November 1, 2011
    Assignee: Hamamatsu-shi Photonics K.K.
    Inventor: Akimasa Tanaka
  • Publication number: 20110263129
    Abstract: Disclosed is a method of etching semiconductor nanocrystals, which includes dissolving semiconductor nanocrystals in a halogenated solvent containing phosphine so that anisotropic etching of the surface of semiconductor nanocrystals is induced or adding a primary amine to a halogenated solvent containing phosphine and photoexciting semiconductor nanocrystals thus inducing isotropic etching of the surface of the nanocrystals, thereby reproducibly controlling properties of semiconductor nanocrystals including absorption wavelength, emission wavelength, emission intensity, average size, size distribution, shape, and surface state.
    Type: Application
    Filed: December 28, 2010
    Publication date: October 27, 2011
    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Seung Koo Shin, Won Jung Kim, Sung Jun Lim
  • Publication number: 20110142089
    Abstract: A first semiconductor layer, an active layer, a second semiconductor layer, and a contact layer are sequentially stacked on a substrate. A ridge portion extending between both facets of a resonator is provided in the second semiconductor layer and the contact layer. A current confining layer is formed to be in contact with the ridge portion. The current confining layer has an opening on an upper surface of the ridge portion. A first electrode in contact with the contact layer is formed in the opening. A second electrode is provided on the first electrode. A non-current injection portion in contact with the contact layer is provided on the upper surface of the ridge portion near the resonator facet. The current confining layer and the non-current injection portion are formed of the same dielectric film. The second electrode is spaced apart from an upper surface region of the non-current injection portion.
    Type: Application
    Filed: November 1, 2010
    Publication date: June 16, 2011
    Inventor: Akiyoshi KUDO
  • Patent number: 7955982
    Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: June 7, 2011
    Assignee: Sumco Corporation
    Inventors: Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
  • Patent number: 7867787
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: January 11, 2011
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Patent number: 7851372
    Abstract: In one aspect, a composition is provided which is capable of removing an insulation material which includes at least one of a low-k material and a passivation material. The composition of this aspect includes about 5 to about 40 percent by weight of a fluorine compound, about 0.01 to about 20 percent by weight of a first oxidizing agent, about 10 to about 50 percent by weight of a second oxidizing agent, and a remaining water.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Kang, Kui-Jong Baek, Woong Hahn, Chun-Deuk Lee, Jung-Hun Lim, Young-Nam Kim, Hyun-Joon Kim
  • Publication number: 20100304570
    Abstract: Disclosed is a semiconductor etching method whereby a semiconductor layer made of, for example, a Group III-V nitride semiconductor resistant to etching can be etched by a relatively easier process. This etching method comprises forming a metal-fluoride layer 3 at least as a part of an etching mask on the surface of a base structure (1,2); treating the metal-fluoride layer with a liquid; and etching the base structure using the metal-fluoride layer as a mask.
    Type: Application
    Filed: October 31, 2008
    Publication date: December 2, 2010
    Applicant: Mitsubishi Chemical Corporation
    Inventors: Hideyoshi Horie, Takashi Fukada
  • Publication number: 20100258841
    Abstract: An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.
    Type: Application
    Filed: April 7, 2010
    Publication date: October 14, 2010
    Inventors: Alexander Lidow, Robert Beach, Guang Y. Zhao, Jianjun Cao
  • Patent number: 7807490
    Abstract: Provided is a manufacturing method of a nitride semiconductor device having a nitride semiconductor substrate (e.g. GaN substrate) in which dislocation concentrated regions align in stripe formation, the dislocation concentrated regions extending from a front surface to a back surface of the substrate, the manufacturing method being for stacking each of a plurality of nitride semiconductor layers on the front surface of the substrate in a constant film thickness. Grooves are formed on the nitride semiconductor substrate in the immediate areas of dislocation concentrated regions. Each of the nitride semiconductor layers is formed as a crystal growth layer on the main surface of the nitride semiconductor substrate to which the grooves have been formed.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: October 5, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Kano, Tsutomu Yamaguchi, Hiroaki Izu, Masayuki Hata, Yasuhiko Nomura
  • Patent number: 7790493
    Abstract: Disclosed herein is a method of fabricating a device having a microstructure. The method includes forming a connector on a semiconductor substrate, coating the connector with a polymer layer, and immersing the semiconductor substrate and the coated connector in an etchant solution to form the microstructure from the semiconductor substrate and to release the coated connector and the microstructure from the semiconductor substrate such that the microstructure remains coupled to a further element of the device via the coated connector. In some cases, the microstructure is defined by forming an etch stop in the semiconductor substrate, and the microstructure and the semiconductor substrate are coated with a polymer layer, which may then be selectively patterned. The microstructure may then be released from the semiconductor substrate in accordance with the etch stop.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: September 7, 2010
    Assignee: The Regents of the University of Michigan
    Inventors: Kensall D. Wise, Mayurachat Ning Gulari, Ying Yao
  • Patent number: 7776752
    Abstract: Provided are an etching method for a multi-layered structure of semiconductors in groups III-V and a method of manufacturing a VCSEL using the etching method. According to the etching method, a stacked structure including a first semiconductor layer and a second semiconductor layer is exposed to a plasma of a mixture consisting of Cl2, Ar, CH4, and H2 to etch the stacked structure, so that a mirror layer of the VCSEL is formed. The first semiconductor layer is formed of a semiconductor in groups III-V and the second semiconductor layer is formed of a semiconductor in groups III-V, other than the semiconductor of the first semiconductor layer. At least part of a lower mirror layer, a lower electrode layer, an optical gain layer, an upper electrode layer, and an upper mirror layer is etched using one time of an etching process, so that a clean and smooth etched surface is obtained.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: August 17, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: O Kyun Kwon, Mi Ran Park, Won Seok Han, Hyun Woo Song
  • Publication number: 20100195684
    Abstract: A method for fabricating a semiconductor laser device, by etching facets using a photoelectrochemical (PEC) etch, so that the facets are sufficiently smooth to support optical modes within a cavity bounded by the facets.
    Type: Application
    Filed: February 1, 2010
    Publication date: August 5, 2010
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Adele C. Tamboli, Evelyn L. Hu, Steven P. DenBaars, Arpan Chakraborty
  • Patent number: 7759257
    Abstract: Methods are disclosed generally directed to design and synthesis of quantum dot nanoparticles having improved uniformity and size. In a preferred embodiment, a release layer is deposited on a semiconductor wafer. A heterostructure is grown on the release layer using epitaxial deposition techniques. The heterostructure has at least one layer of quantum dot material, and optionally, one or more layers of reflective Bragg reflectors. A mask is deposited over a top layer and reactive ion-beam etching applied to define a plurality of heterostructures. The release layer can be dissolved releasing the heterostructures from the wafer. Some exemplary applications of these methods include formation of fluorophore materials and high efficiency photon emitters, such as quantum dot VCSEL devices. Other applications include fabrication of other optoelectronic devices, such as photodetectors.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: July 20, 2010
    Assignee: Spire Corporation
    Inventor: Kurt J. Linden
  • Patent number: 7723751
    Abstract: A semiconductor device includes a substrate, a SiC drift layer formed above the substrate, a GaN-based semiconductor layer that is formed on the SiC drift layer and includes a channel layer, a source electrode and a gate electrode formed on the GaN-based semiconductor layer, current blocking regions formed in portions of the SiC drift layer and located below the source and gate electrodes, and a drain electrode formed on a surface that opposes the GaN-based semiconductor layer across the SiC layer.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 25, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Takeshi Kawasaki, Ken Nakata, Seiji Yaegashi
  • Patent number: 7713878
    Abstract: A method of recovering a first substrate, including the steps of: sticking a second substrate on a semiconductor layer epitaxially grown on the first substrate; and separating the semiconductor layer and the first substrate. Furthermore, a method of reproducing a first substrate, including the step of surface processing the first substrate separated. Furthermore, a method of reproducing a first substrate, including the step of homoepitaxially growing the first substrate surface processed. Furthermore, a method of producing a semiconductor wafer, including the step of epitaxially growing a semiconductor layer on a first substrate. Thus a group III nitride or similar, expensive substrate can be used to efficiently and economically, epitaxially grow a group III nitride or similar semiconductor layer.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: May 11, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Seiji Nakahata
  • Patent number: 7691735
    Abstract: The invention relates to a method for manufacturing chips composed of at least one electrically conductive material. Such a method comprises the following steps: deposition, on a support, of an alloy comprising at least the electrically conductive material and a second material; exposure of the alloy to plasma etching, in order to cause the desorption of the materials of the alloy not forming part of the composition of the chips, that is at least the second material but not the electrically conductive material; formation of chips composed of at least said electrically conductive material.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: April 6, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Laurent Grenouillet, Jonathan Garcia, François Marion, Nicolas Olivier, Marion Perrin
  • Publication number: 20100072518
    Abstract: Methods of fabricating semiconductor devices using electrode-less wet-etching techniques to reduce defect densities on etched group III-nitride semiconductor surfaces are described herein. The methods generally involve contacting an etched surface of a component of a semiconductor device with a solution comprising a metal hydroxide and an oxidizing agent effective to reduce a roughness of the etched surface, wherein the etched surface is formed from a composition comprising a nitride of a group III element. Improved semiconductor devices are also disclosed.
    Type: Application
    Filed: September 14, 2009
    Publication date: March 25, 2010
    Applicant: Georgia Tech Research Corporation
    Inventors: Shyh-Chiang Shen, Russell Dean Dupuis, Yun Zhang
  • Publication number: 20100048016
    Abstract: A semiconductor device manufacturing method includes: providing a laminated member in which at least a first GaAs layer, an InAlGaAs layer and a second GaAs layer are laminated on or above a substrate in this order; and etching the second GaAs layer using the InAlGaAs layer as an etching stopper layer. A ratio of In:Al of the InAlGaAs layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs layer is in a range of approximately 1.5:8.5 to approximately 5:5.
    Type: Application
    Filed: August 17, 2009
    Publication date: February 25, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Takayuki IZUMI, Ryoji SHIGEMASA, Tomoyuki OHSHIMA
  • Patent number: 7569493
    Abstract: There is provided a cleaning method and production method that suppresses the adhesion of foreign matters including impurity, fine particles and the like on a surface of a compound semiconductor. A method of cleaning a nitride-based compound semiconductor in accordance with the present invention includes the steps of: preparing a nitride-based compound semiconductor (or a substrate preparation step); and cleaning. In the step of cleaning, a cleaning liquid having a pH of 7.1 or higher is used to clean the nitride-based compound semiconductor.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: August 4, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Takayuki Nishiura
  • Publication number: 20080280445
    Abstract: Provided is a manufacturing method of a nitride semiconductor device having a nitride semiconductor substrate (e.g. GaN substrate) in which dislocation concentrated regions align in stripe formation, the dislocation concentrated regions extending from a front surface to a back surface of the substrate, the manufacturing method being for stacking each of a plurality of nitride semiconductor layers on the front surface of the substrate in a constant film thickness. Grooves are formed on the nitride semiconductor substrate in the immediate areas of dislocation concentrated regions. Each of the nitride semiconductor layers is formed as a crystal growth layer on the main surface of the nitride semiconductor substrate to which the grooves have been formed.
    Type: Application
    Filed: July 14, 2008
    Publication date: November 13, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Takashi Kano, Tsutomu Yamaguchi, Hiroaki Izu, Masayuki Hata, Yasuhiko Nomura
  • Patent number: 7413958
    Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 19, 2008
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Liberty L Gunter, Kanin Chu, Charles R Eddy, Jr., Theodore D Moustakas, Enrico Bellotti
  • Patent number: 7405096
    Abstract: Provided is a manufacturing method of a nitride semiconductor device having a nitride semiconductor substrate (e.g. GaN substrate) in which dislocation concentrated regions align in stripe formation, the dislocation concentrated regions extending from a front surface to a back surface of the substrate, the manufacturing method being for stacking each of a plurality of nitride semiconductor layers on the front surface of the substrate in a constant film thickness. Grooves are formed on the nitride semiconductor substrate in the immediate areas of dislocation concentrated regions. Each of the nitride semiconductor layers is formed as a crystal growth layer on the main surface of the nitride semiconductor substrate to which the grooves have been formed.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: July 29, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Kano, Tsutomu Yamaguchi, Hiroaki Izu, Masayuki Hata, Yasuhiko Nomura
  • Patent number: 7371694
    Abstract: The flatness of the surface of a Si substrate is requested as the present gate length is miniaturized. The present invention is a semiconductor device fabrication method for flattening a silicon surface by continuously supplying a high-temperature fluoride ammonium solution to the surface a silicon substrate in which at least the silicon surface is locally exposed.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: May 13, 2008
    Assignee: Elpida Memory Inc.
    Inventors: Ken Sasaki, Hiroyuki Sakaue, Takayuki Takahagi
  • Patent number: 7316961
    Abstract: Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating layer corresponding to a capacitor forming region so that the lower electrode is not exposed, forming an inter-insulating layer by wet-etching the insulating layer so that a region of the lower electrode corresponding to the capacitor forming region is exposed, and sequentially forming a dielectric layer and an upper electrode on the capacitor forming region to fabricate a capacitor.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: January 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Weon-hong Kim, Yong-kuk Jeong
  • Patent number: 7282455
    Abstract: In an embodiment, a method of producing a diffraction grating comprises steps of: forming, on a man surface of a first member, a first mask having a plurality of resist patterns arranged at a Bragg diffraction period; etching the first member by use of the first mask, thereby providing the first member with a diffraction grating; removing the first mask; forming, on the diffraction grating, a second member of which an etching rate is lower than that of the first member; forming a second mask on a first region in a surface of the second member, the first region and a second region in the surface being adjacent to each other; and etching the first member and the second member by use of the second mask.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: October 16, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeshi Kishi
  • Patent number: 7259080
    Abstract: The invented method is distinguished by a combination of the following method steps: provision of a semiconductor planar substrate composed of a semiconductor material, reduction of the thickness of the semiconductor planar substrate inside at least one surface region of the semiconductor planar substrate in order to form a raised surface region in relation to the surface planar region of reduced thickness, structuring the raised surface region of the semiconductor planar substrate by means of local mechanical removal of material in order to place impressions inside the raised surface regions, joining the structured surface of the semiconductor planar substrate with the glasslike planar substrate in such a manner that the glasslike planar substrate at least partially covers the surface planar region of reduced thickness, tempering the joined planar substrates in such a manner that in a first tempering phase, which is conducted under vacuum conditions, the glasslike planar substrate covering the surface reg
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: August 21, 2007
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung e.V.
    Inventors: Hans-Joachim Quenzer, Arne-Veit Schulz, Peter Merz
  • Patent number: 7202122
    Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
    Type: Grant
    Filed: June 11, 2004
    Date of Patent: April 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu
  • Patent number: RE42955
    Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: November 22, 2011
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Liberty L. Gunter, Kanin Chu, Charles R. Eddy, Jr., Theodore D. Moustakas, Enrico Bellotti