Chemical Etching (epo) Patents (Class 257/E21.219)
  • Patent number: 10192732
    Abstract: A chemical solution cleaning process for removing backside contamination prior to metallization involves selective chemistries of a mixture containing NH4OH and H2O2 that may be diluted to specific concentrations depending upon the topside metal and passivation of a semiconductor wafer, which is applied after removing a topside protection material to protect the topside circuitry.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: January 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qin Xu Yu, Tian Yi Zhang, Jian Jun Kong
  • Patent number: 10068778
    Abstract: This plasma processing method includes a film formation step, a plasma processing step and a removal step. In the film formation step, a silicon oxide film is formed on the surface of a member within a chamber by means of plasma of an oxygen-containing gas and a silicon-containing gas at a flow rate ratio of the oxygen-containing gas to the silicon-containing gas of 0.2-1.4. In the plasma processing step, after the formation of the silicon oxide film on the surface of the member, an object to be processed that has been carried into the chamber is subjected to plasma processing with use of plasma of a processing gas. In the removal step, after carrying the plasma-processed object out of the chamber, the silicon oxide film is removed from the surface of the member by means of plasma of a fluorine-containing gas.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: September 4, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Hirayama, Masaaki Miyagawa
  • Patent number: 10026694
    Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kiseok Lee, Sooho Shin, Juik Lee, Jun Ho Lee, Kwangmin Kim, Ilyoung Moon, Jemin Park, Bumseok Seo, Chan-Sic Yoon, Hoin Lee
  • Patent number: 9960048
    Abstract: A surface machining method for a single crystal SiC substrate, including: a step of mounting a grinding plate which includes a soft pad and a hard pad sequentially attached onto a base metal having a flat surface, a step of generating an oxidation product by using the grinding plate, and a step of grinding the surface while removing the oxidation product, wherein abrasive grains made of at least one metallic oxide that is softer than single crystal SiC and has a bandgap are fixed to the surface of the hard pad.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: May 1, 2018
    Assignee: SHOWA DENKO K.K.
    Inventors: Takanori Kido, Tomohisa Kato
  • Patent number: 9958794
    Abstract: According to one embodiment, a management method of a manufacturing apparatus of a semiconductor device, the method includes measuring a weight of a pre-exposure substrate including a semiconductor substrate and a resist film provided on the semiconductor substrate, performing an exposure process for the resist film, measuring a weight of a post-exposure substrate including the semiconductor substrate and the resist film after the exposure process is performed, and acquiring a weight difference between the weight of the pre-exposure substrate and the weight of the post-exposure substrate.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: May 1, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Eishi Shiobara
  • Patent number: 9865613
    Abstract: There is provided a semiconductor device having an arrangement structure in which high-density line patterns having relatively small widths and relatively tight pitches may be formed. The semiconductor device includes a plurality of line patterns that are spaced apart from one another. The plurality of line patterns include a plurality of main lines that have a first gap therebetween and extend in a first direction and a plurality of sublines that are bent from one end of each of the plurality of main lines. The plurality of sublines have therebetween a distance that is greater than the first gap, and may be spaced apart from extension lines that extend from the one end of each of the plurality of main lines corresponding to the plurality of sublines in the first direction.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-min Lee, Ho-jun Seong, Jae-ho Ahn
  • Patent number: 9859366
    Abstract: A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: January 2, 2018
    Assignee: Advanced Silicon Group, Inc.
    Inventors: Brent A. Buchine, Marcie R. Black, Faris Modawar
  • Patent number: 9809882
    Abstract: A process for depositing a metal includes disposing an activating catalyst on a substrate; contacting the activating catalyst with a metal cation from a vapor deposition composition; contacting the substrate with a reducing anion from the vapor deposition composition; performing an oxidation-reduction reaction between the metal cation and the reducing anion in a presence of the activating catalyst; and forming a metal from the metal cation to deposit the metal on the substrate. A system for depositing a metal includes an activating catalyst to deposit on a substrate; and a primary reagent to form: a metal cation to deposit on the substrate as a metal; and a reducing anion to provide electrons to the activating catalyst, the metal cation, the substrate, or a combination thereof, wherein the primary reagent forms the metal cation and the reducing anion in response to being subjected to a dissociating condition.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 7, 2017
    Assignee: The United States of America, as represented by the Secretary of Commerce
    Inventor: Owen Hildreth
  • Patent number: 9786762
    Abstract: A semiconductor device includes a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode having a metal layer, a metal oxide layer and a silicon layer containing a dopant, provided sequentially on the gate insulating film; and a transistor having a gate insulating film and a gate electrode.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: October 10, 2017
    Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.
    Inventors: Hiromu Yamaguchi, Kazuaki Tonari
  • Patent number: 9768017
    Abstract: The invention provides a method of epitaxial structure formation in a semiconductor, comprising: providing a substrate; performing a dry etch to form a first recess; after performing the dry etch, performing a SPM cleaning process on the substrate by using a nozzle spraying SPM solution with an angle greater than zero and less than 45 degrees relative to the substrate; after performing the SPM cleaning process, performing a wet etch to form a second recess; after performing the wet etch, performing a pre-epi cleaning process; and growing an epitaxial structure in the second recess.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: September 19, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Tsung-Hsun Tsai
  • Patent number: 9711419
    Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.
    Type: Grant
    Filed: August 22, 2015
    Date of Patent: July 18, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Carlos A. Fonseca, Benjamen M. Rathsack, Jeffrey Smith, Anton J. deVilliers, Lior Huli, Teruhiko Kodama, Joshua S. Hooge
  • Patent number: 9704738
    Abstract: Bonded semiconductor device structures and device structure fabrication processes to obviate the need for SOI wafers in many device fabrication applications are disclosed. In some examples, multiple etch stop layers are formed in situ during fabrication of an active device structure on a bulk semiconductor wafer. The etch stop layers are incorporated into in a layer transfer process to enable very thin high quality active device layers of substantially uniform across-wafer thickness to be separated from bulk semiconductor wafers and bonded to handle wafers. As a result, these examples can produce high-performance and low-power semiconductor devices while avoiding the high cost of SOI wafers.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: July 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Sinan Goktepeli
  • Patent number: 9502499
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first trench between a first active region and a second active region of the substrate. The semiconductor device structure includes an isolation structure in the first trench. The isolation structure includes a liner layer, an insulating layer, and an isolation layer. The liner layer covers an inner wall and a bottom surface of the first trench. The insulating layer covers the liner layer and has a second trench in the first trench. The isolation layer is over the insulating layer and fills the second trench. A first thickness of the insulating layer is greater than a second thickness of the liner layer.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Ji-Feng Liu
  • Patent number: 9463550
    Abstract: A method of making a polishing layer for polishing a substrate selected from at least one of a magnetic substrate, an optical substrate and a semiconductor substrate is provided, comprising: providing a liquid prepolymer material; providing a plurality of hollow microspheres; exposing the plurality of hollow microspheres to a carbon dioxide atmosphere for an exposure period to form a plurality of treated hollow microspheres; combining the liquid prepolymer material with the plurality of treated hollow microspheres to form a curable mixture; allowing the curable mixture to undergo a reaction to form a cured material, wherein the reaction is allowed to begin ?24 hours after the formation of the plurality of treated hollow microspheres; and, deriving at least one polishing layer from the cured material; wherein the at least one polishing layer has a polishing surface adapted for polishing the substrate.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: October 11, 2016
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: George McClain, Alan Saikin, David Kolesar, Aaron Sarafinas, Robert L. Post
  • Patent number: 9463553
    Abstract: A method of making a polishing layer for polishing a substrate is provided, comprising: providing a liquid prepolymer material; providing a plurality of hollow microspheres; exposing the plurality of hollow microspheres to a vacuum to form a plurality of exposed hollow microspheres; treating the plurality of exposed hollow microspheres with a carbon dioxide atmosphere to form a plurality of treated hollow microspheres; combining the liquid prepolymer material with the plurality of treated hollow microspheres to form a curable mixture; allowing the curable mixture to undergo a reaction to form a cured material, wherein the reaction is allowed to begin ?24 hours after the formation of the plurality of treated hollow microspheres; and, deriving at least one polishing layer from the cured material; wherein the at least one polishing layer has a polishing surface adapted for polishing the substrate.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: October 11, 2016
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: David Kolesar, Aaron Sarafinas, Alan Saikin, Robert L. Post
  • Patent number: 9230824
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes providing an object to be processed including a multilayer film formed by alternately laminating a first film and a second film having different dielectric coefficients within a processing container of a plasma processing apparatus; and repeatedly performing a sequence including: supplying a first gas including O2 gas or N2 gas, and a rare gas into the processing container and exciting the first gas, supplying a second gas including a fluorocarbon gas or a fluorohydrocarbon gas into the processing container and exciting the second gas, and supplying a third gas including HBr gas, a fluorine-containing gas, and a fluorocarbon gas or a fluorohydrocarbon gas into the processing container and exciting the third gas, so that the multilayer film is etched through a mask.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 5, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Wataru Takayama, Shoichiro Matsuyama, Susumu Nogami, Daisuke Tamura, Kyosuke Hayashi, Jun Kawanobe
  • Patent number: 9040431
    Abstract: A method for processing a silicon wafer is provided. The method includes allowing an etchant to flow along a surface of the silicon wafer to form a line in which a plurality of apertures are arranged in a flow direction of the etchant from an upstream side to a downstream side. The apertures arranged in the line include a first aperture formed on the most upstream side and a second aperture formed downstream of the first aperture in the flow direction of the etchant. The first aperture and the second aperture are subjected to different processes after being formed.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 26, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hirohisa Fujita, Shuji Koyama, Keiji Matsumoto, Kenta Furusawa
  • Patent number: 9041119
    Abstract: A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 26, 2015
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Desmond J. Donegan, Jr., Abhishek Dube, Steven Jones, Jophy S. Koshy, Viorel Ontalus
  • Patent number: 9034736
    Abstract: The present invention provides a method of patterning an electronic or photonic material on a substrate comprising: forming a film of said electronic or photonic material on said substrate; and using a fluoropolymer to protect regions of said electronic or photonic material during a patterning process.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Cambridge Enterprise Limited
    Inventors: Henning Sirringhaus, Jui-Fen Chang, Michael Gwinner
  • Patent number: 9018776
    Abstract: A hard mask composition includes a solvent and an aromatic ring-containing compound represented by the following Chemical Formula 1:
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 28, 2015
    Assignee: Cheil Industries, Inc.
    Inventors: Jee-Yun Song, Min-Soo Kim, Hwan-Sung Cheon, Seung-Bae Oh, Yoo-Jeong Choi
  • Patent number: 9006010
    Abstract: Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 ?m to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 14, 2015
    Assignee: General Electric Company
    Inventors: Arie Shahar, Eliezer Traub, Diego Sclar, Peter Rusian
  • Patent number: 8993708
    Abstract: A carbazole polymer including a repeating unit represented by Formula 1 and having excellent one electron oxidation-state stability, wherein, in Formula 1, R1-R4 each independently represents an alkyl group having 1-60 carbon atoms, a haloalkyl group having 1-60 carbon atoms, or similar, Cz represents a divalent group including a carbazole skeleton represented by Formula 2, and Ar represents a divalent aromatic ring or similar; wherein, in Formula 2, R5 represents a hydrogen atom, an alkyl group having 1-60 carbon atoms, or similar, R6-R11 each independently represents a hydrogen atom, a halogen atom, or similar, and m represents an integer 1-10.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 31, 2015
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Yuki Shibano, Takuji Yoshimoto
  • Patent number: 8987807
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shosuke Fujii, Kiwamu Sakuma, Jun Fujiki, Atsuhiro Kinoshita
  • Patent number: 8987781
    Abstract: An improved structure of heterojunction field effect transistor (HFET) and a fabrication method thereof are disclosed. The improved HFET structure comprises sequentially a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a Schottky capping layer formed by a higher energy gap material, a tunneling layer formed by a lower energy gap material, a first etching stop layer, and a first n type doped layer.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: March 24, 2015
    Assignee: Win Semiconductors Corp.
    Inventors: Cheng-Guan Yuan, Shih-Ming Liu
  • Patent number: 8981507
    Abstract: According to one embodiment, a method for manufacturing a nonvolatile memory device including a plurality of memory cells is disclosed. Each of the plurality of memory cells includes a base layer including a first electrode, a magnetic tunnel junction device provided on the base layer, and a second electrode provided on the magnetic tunnel junction device. The magnetic tunnel junction device includes a first magnetic layer, a tunneling barrier layer provided on the first magnetic layer, and a second magnetic layer provided on the tunneling barrier layer. The method can include etching a portion of the second magnetic layer and a portion of the first magnetic layer by irradiating gas clusters onto a portion of a surface of the second magnetic layer or a portion of a surface of the first magnetic layer.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Takahashi, Kyoichi Suguro, Junichi Ito, Yuichi Ohsawa, Hiroaki Yoda
  • Patent number: 8980748
    Abstract: A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to carry out two or more stages of chemical-mechanical polishing processing of a polishing object oxide film on a substrate to flatten the polishing object film.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Hiroko Nakamura, Takaaki Kozuki, Takayuki Enomoto, Yuichi Yamamoto
  • Patent number: 8981461
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shosuke Fujii, Daisuke Hagishima, Kiwamu Sakuma
  • Patent number: 8975090
    Abstract: A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 10, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Goro Nakatani, Toma Fujita
  • Patent number: 8969183
    Abstract: Method for making thin crystalline or polycrystalline layers. The method includes electrochemically etching a crystalline silicon template to form a porous double layer thereon, the double layer including a highly porous deeper layer and a less porous shallower layer. The shallower layer is irradiated with a short laser pulse selected to recrystallize the shallower layer resulting in a crystalline layer. Silicon is deposited on the recrystallized shallower layer and the silicon is irradiated with a short laser pulse selected to crystalize the silicon leaving a layer of crystallized silicon on the template. Thereafter, the layer of crystallized silicon is separated from the template. The process of the invention can be used to make optoelectronic devices.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 3, 2015
    Assignees: President and Fellows of Harvard College, Massachusetts Institute of Technology
    Inventors: Mark T. Winkler, Tonio Buonassisi, Riley E. Brandt, Michael J. Aziz, Austin Joseph Akey
  • Patent number: 8940640
    Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ying Xiao
  • Patent number: 8932476
    Abstract: Apparatuses and methods are provided where porous metal is deposited on a substrate, a mask is provided on the porous metal and then an etching is performed.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 13, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kunstmann, Stefan Willkofer, Anja Gissibl, Johann Strasser, Matthias Mueller, Eva-Maria Hess
  • Patent number: 8932961
    Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: January 13, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sohan Mehta, Tong Qing Chen, Vikrant Chauhan, Ravi Srivastava, Catherine Labelle, Mark Kelling
  • Patent number: 8906812
    Abstract: A method of removing non-noble metal oxides from material (e.g., semiconductor material) used to make a microelectronic device includes providing the material comprising traces of the conducting non-noble metal oxides; applying a chemical mixture (or chemical solution) to the material; removing the traces of the non-noble metal oxides from the material; and removing the chemical mixture from the material. The non-noble metal oxides comprise MoOx, wherein x is a positive number between 0 and 3. The chemical solution comprises any one of HNO3-based chemicals, H2SO4-based chemicals, HCl-based chemicals, or NH4OH-based chemicals.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: December 9, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Wim Deweerd, Kim Van Berkel, Hiroyuki Ode
  • Patent number: 8894867
    Abstract: Disclosed is a method for producing ZnO contact layers for solar cells. The layers are etched using hydrofluoric acid so as to generate a texture.
    Type: Grant
    Filed: August 7, 2010
    Date of Patent: November 25, 2014
    Assignee: Forschungszentrum Juelich GmbH
    Inventors: Eerke Bunte, Jorj Owen, Juergen Huepkes
  • Patent number: 8889563
    Abstract: An aspect of the invention is to provide a method and apparatus for etching the silicon oxide layer of a semiconductor substrate, whereby the processing time for cleaning or rinsing, as well as any undesired aftereffects by residual hydrofluoric acid, may be reduced, in using the dry etching method involving the use of dense carbon dioxide that contains hydrofluoric acid, during the manufacturing process of a micro-electronic device.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: November 18, 2014
    Assignee: Pukyong National University Industry-University Cooperation Foundation
    Inventor: Kwon-Taek Lim
  • Patent number: 8883652
    Abstract: A silicon etching liquid characterized by anisotropically dissolving monocrystalline silicon therein by using an aqueous solution containing a quaternary ammonium hydroxide and an aminoguanidine salt and an etching method of silicon using the instant etching liquid are an etching liquid and an etching method enabling one to perform processing at a high etching rate in etching processing of silicon, particularly in etching processing of silicon in a manufacturing process of MEMS parts or semiconductor devices.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: November 11, 2014
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kazuyoshi Yaguchi, Ryuji Sotoaka
  • Patent number: 8871550
    Abstract: A method for processing a wafer having microelectromechanical system structures at the first main surface includes applying a masking material at the second main surface and structuring the masking material to obtain a plurality of masked areas and a plurality of unmasked areas at the second main surface. The method further includes anisotropically etching the wafer from the second main surface at the unmasked areas to form a plurality of recesses. The masking material is then removed at least at some of the masked areas to obtain previously masked areas. The method further includes anisotropically etching the wafer from the second main surface at the unmasked areas and the previously masked areas to increase a depth of the recesses and reduce a thickness of the wafer at the previously masked areas.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thomas Grille, Ursula Hedenig, Martin Zgaga, Daniel Maurer
  • Patent number: 8859437
    Abstract: Disclosed herein is an aqueous alkaline etching solution comprising water and an alkaline material being selected from the group consisting of ammonium hydroxide, ammonium phosphate, ammonium carbonate, quaternary ammonium hydroxide, quaternary ammonium phosphate, quaternary ammonium carbonate, an alkali metal hydroxide, an alkaline earth metal hydroxide, or a combination comprising at least one of the foregoing alkaline materials; the aqueous alkaline solution being operative to etch aluminum oxide at a rate greater than or equal to about 2:1 over a rate at which it etches a metal oxide semiconductor to be protected; wherein the aqueous etching solution has a pH of 8 to 13.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 14, 2014
    Assignee: The Penn State Research Foundation
    Inventors: Yuanyuan Li, Kaige Sun, Thomas N. Jackson
  • Patent number: 8860125
    Abstract: According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu Sakuma, Atsuhiro Kinoshita
  • Patent number: 8853085
    Abstract: A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jassem A. Abdallah, Matthew E. Colburn, Steven J. Holmes, Chi-Chun Liu
  • Patent number: 8835329
    Abstract: Methods for combinatorially processing semiconductor substrates are provided. The methods may involve receiving a substrate into a combinatorial processing chamber and sealing a plurality of flow cells against a surface of the substrate. The plurality of flow cells is enclosed within the combinatorial processing chamber to define an enclosed external environment for the plurality of flow cells. A pressure differential is created between a reaction area of the plurality of flow cells of the combinatorial processing chamber and the external environment, wherein each flow cells of the plurality of flow cells defines a site isolating region of the substrate. The regions the substrate are then combinatorially processed.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: September 16, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sandeep Mariserla, Aaron T. Francis, Jeffrey Chih-Hou Lowe, Robert Anthony Sculac
  • Patent number: 8829629
    Abstract: A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: September 9, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Goro Nakatani, Toma Fujita
  • Patent number: 8828871
    Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Junqing Zhou, Xiaoying Meng, Haiyang Zhang
  • Patent number: 8822347
    Abstract: A system to form a wet soluble lithography layer on a semiconductor substrate includes providing the substrate, depositing a first layer comprising a first material on the substrate, and depositing a second layer comprising a second material on the substrate. In an embodiment, the first material comprises a different composition than the second material and one of the first layer and the second layer includes silicon.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Wang, Ching-Yu Chang
  • Patent number: 8815740
    Abstract: A method for forming a pattern according to an embodiment, includes forming above a first film film patterns of a second film; forming film patterns of the first film by etching the first film using the film patterns of the second film as a mask; converting the film patterns of the second film into film patterns whose width are narrower than the film patterns of the first film by performing a slimming process; forming film patterns of a third film on both sidewalls of the film patterns of the first film and the film patterns of the second film after the slimming process; and etching the first film using the film patterns of the third film as a mask after the film patterns of the second film being removed.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Horiguchi, Takashi Ohashi
  • Patent number: 8791449
    Abstract: A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 29, 2014
    Assignee: Bandgap Engineering, Inc.
    Inventors: Brent A. Buchine, Faris Modawar, Marcie R. Black
  • Patent number: 8765553
    Abstract: Nonvolatile memory has a modified channel region interface, such as a raised source and drain or a recessed channel region.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: July 1, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Yi Ying Liao
  • Patent number: 8742872
    Abstract: In a MEMS device having a substrate 1, a sealing membrane 7, and a movable portion 3 of beam and an electrode 5 which have a region wherein they overlap with a gap in perpendicular to a substrate 1 surface, a first cavity 9 is on the side of the movable portion 3 in the direction perpendicular to the surface of the substrate, and a second cavity is the other cavity, and an inner surface a of a side wall A in contact with the electrode 5, of the first cavity 9, is positioned more inside than an inner surface b of a side wall B in contact with the electrode 5, of the second cavity 10, in the direction parallel to the substrate surface, such that the movable portion 3 does not collide with the electrode 5 when mechanical stress is applied from outside to the sealing membrane 7.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: June 3, 2014
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Iwasaki, Keiji Onishi, Kunihiko Nakamura
  • Patent number: 8735207
    Abstract: The present disclosure provides one embodiment of a method. The method includes providing a semiconductor substrate having a front side and a backside, wherein the front side of the semiconductor substrate includes a plurality of backside illuminated imaging sensors; bonding a carrier substrate to the semiconductor substrate from the front side; thinning the semiconductor substrate from the backside; performing an ion implantation to the semiconductor substrate from the backside; performing a laser annealing process to the semiconductor substrate from the backside; and thereafter, performing a polishing process to the semiconductor substrate from the backside.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Chien Wang, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 8735261
    Abstract: A method and a system are described herein for applying etchant to edges of a plurality of wafers. The system includes a sump configured for holding etchant, a roller having an outer surface in fluid communication with the sump and configured to have etchant thereon, a wafer cassette configured to retain wafers positioned therein so that edges of the wafers are in contact with the roller. The cassette permits axial rotation of the wafers about an axis. A method of applying etchant to the edge of the wafer includes placing the wafer edge in contact with the roller and rotating the roller about a longitudinal axis of the roller. At least a portion of the roller contact an etchant contained in a sump during rotation so that etchant is applied to the wafer edge.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: May 27, 2014
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Robert W. Standley