Wet Cleaning Only (epo) Patents (Class 257/E21.228)
  • Patent number: 10546762
    Abstract: Methods of drying a semiconductor substrate may include applying a drying agent to a semiconductor substrate, where the drying agent wets the semiconductor substrate. The methods may include heating a chamber housing the semiconductor substrate to a temperature above an atmospheric pressure boiling point of the drying agent until a vapor-liquid equilibrium of the drying agent within the chamber has been reached. The methods may further include venting the chamber, where the venting vaporizes the liquid phase of the drying agent from the semiconductor substrate.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 28, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Eric J. Bergman, John L. Klocke, Paul McHugh, Stuart Crane, Richard W. Plavidal
  • Patent number: 10541130
    Abstract: A semiconductor structure, a method, and an apparatus for in-situ sulfur vapor passivation of an interface surface of an indium gallium arsenide layer of the semiconductor structure. A method includes elemental sulfur-vapor passivation of an interface surface of an indium gallium arsenide layer disposed on a substrate. A dielectric layer can be deposited on the sulfur-vapor passivated interface surface. An annealing process can be performed after the deposition of the dielectric layer. The annealing process anneals the indium gallium arsenide layer including the sulfur-vapor passivated interface surface and the dielectric layer disposed on the sulfur-vapor passivated interface surface. The sulfur-vapor passivation, the deposition of the dielectric layer, and the anneal, can be performed in-situ in a vacuum chamber without breaking a vacuum of the vacuum chamber following a III-V material growth process in the vacuum chamber to form the indium gallium arsenide layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yun Seog Lee, Talia S. Gershon, Joel P. De Souza, Devendra K. Sadana
  • Patent number: 10541131
    Abstract: A semiconductor structure, a method, and an apparatus for in-situ sulfur vapor passivation of an interface surface of an indium gallium arsenide layer of the semiconductor structure. A method includes elemental sulfur-vapor passivation of an interface surface of an indium gallium arsenide layer disposed on a substrate. A dielectric layer can be deposited on the sulfur-vapor passivated interface surface. An annealing process can be performed after the deposition of the dielectric layer. The annealing process anneals the indium gallium arsenide layer including the sulfur-vapor passivated interface surface and the dielectric layer disposed on the sulfur-vapor passivated interface surface. The sulfur-vapor passivation, the deposition of the dielectric layer, and the anneal, can be performed in-situ in a vacuum chamber without breaking a vacuum of the vacuum chamber following a III-V material growth process in the vacuum chamber to form the indium gallium arsenide layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yun Seog Lee, Talia S. Gershon, Joel P. De Souza, Devendra K. Sadana
  • Patent number: 10541129
    Abstract: A semiconductor structure, a method, and an apparatus for in-situ sulfur vapor passivation of an interface surface of an indium gallium arsenide layer of the semiconductor structure. A method includes elemental sulfur-vapor passivation of an interface surface of an indium gallium arsenide layer disposed on a substrate. A dielectric layer can be deposited on the sulfur-vapor passivated interface surface. An annealing process can be performed after the deposition of the dielectric layer. The annealing process anneals the indium gallium arsenide layer including the sulfur-vapor passivated interface surface and the dielectric layer disposed on the sulfur-vapor passivated interface surface. The sulfur-vapor passivation, the deposition of the dielectric layer, and the anneal, can be performed in-situ in a vacuum chamber without breaking a vacuum of the vacuum chamber following a III-V material growth process in the vacuum chamber to form the indium gallium arsenide layer.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yun Seog Lee, Talia S. Gershon, Joel P. De Souza, Devendra K. Sadana
  • Patent number: 10494715
    Abstract: Methods and apparatuses for removing photoresist patterning scum from patterning mandrel structures without damaging other features or structures on a semiconductor substrate are desirable for patterning precision. Methods involve cleaning carbon-containing features on a semiconductor substrate by an atomic layer cleaning (ALC) process to descum the carbon-containing features without substantially modifying feature critical dimensions. The ALC process involves exposing the carbon-containing features to an oxidant or reductant in absence of a plasma, or other energetic activation, to modify scum on the surface of the carbon-containing features. The modified scum on the surface of the carbon-containing features is then exposed to an inert gas along with a plasma ignited at a pressure between 0.1 Torr and 10 Torr and a power of less than 200 W to remove the modified scum from the surface of the carbon-containing features.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 3, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Pulkit Agarwal, Purushottam Kumar, Adrien LaVoie
  • Patent number: 10283345
    Abstract: Methods for processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: heating a substrate disposed within a processing volume of a substrate processing chamber to a temperature of up to about 400 degrees Celsius, wherein the substrate comprises a first surface, an opposing second surface, and an opening formed in the first surface and extending towards the opposing second surface, and wherein the second surface comprises a conductive material disposed in the second surface and aligned with the opening; and exposing the substrate to a process gas comprising about 80 to about 100 wt. % of an alcohol to reduce a contaminated surface of the conductive material.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 7, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xiangjin Xie, Feng Q. Liu, Daping Yao, Alexander Jansen, Joung Joo Lee, Adolph Miller Allen, Xianmin Tang, Mei Chang
  • Patent number: 10236261
    Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Yi-Feng Chang, Lung-Yuan Wang
  • Patent number: 10236381
    Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10224224
    Abstract: A high-pressure processing system for processing a substrate includes a first chamber, a pedestal positioned within the first chamber to support the substrate, a second chamber adjacent the first chamber, a vacuum processing system configured to lower a pressure within the second chamber to near vacuum, a valve assembly between the first chamber and the second chamber to isolate the pressure within the first chamber from the pressure within the second chamber, and a gas delivery system configured to introduce a processing gas into the first chamber and to increase the pressure within the first chamber to at least 10 atmospheres while the processing gas is in the first chamber and while the first chamber is isolated from the second chamber.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 5, 2019
    Assignee: Micromaterials, LLC
    Inventors: Qiwei Liang, Srinivas D. Nemani, Adib Khan, Venkata Ravishankar Kasibhotla, Sultan Malik, Sean S. Kang, Keith Tatseun Wong
  • Patent number: 10204793
    Abstract: A chemical mechanical polishing (CMP) slurry, a method for CMP, and a manufacturing method of a semiconductor structure are provided. The CMP slurry includes a pH-adjustor for providing an alkaline environment in the CMP slurry and a silicon inhibitor for lowering a removal rate of silicon. The CMP slurry is used in a planarization operation to remove portions of a semiconductor region and portions of a silicon region. The semiconductor region comprises at least one semiconductor material different from silicon. The semiconductor region is formed in a recess adjacent to the silicon region. The particle defect condition may be improved by applying the alkaline CMP slurry, and the silicon inhibitor may be used to modify the removal rate selectivity between the semiconductor region and the silicon region in the planarization operation.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shu-Hao Huang
  • Patent number: 9859162
    Abstract: A method for separation of semiconductor device cell units from fabricated large-area cell units, together with a corresponding tile unit structure, are provided in which the tile unit is cut along cell unit boundaries while leaving intact a set of specified tab sections distributed along the cell unit boundaries. The tile unit may be a multi-layer composite of a semiconductor layer with a conductive metallic base supported upon a polymer layer and adhered thereto by an adhesive film, wherein tab sections are cut completely through the semiconductor layer and its metallic base from above and may also be cut partially through the polymer layer from below, leaving at least a portion of the polymer layer in place at tab sections. Tile units can be handled such that component cell units are held together by the tab sections, until a physical final separation of selected cell units.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: January 2, 2018
    Assignee: ALTA DEVICES, INC.
    Inventors: Khurshed Sorabji, Daniel G. Patterson
  • Patent number: 9831081
    Abstract: In embodiment, the method includes cleaning a preceding substrate, and drying the preceding substrate and cleaning a next substrate. Drying the preceding substrate and cleaning the next substrate include determining a cleaning start time of the next substrate, and the cleaning start time corresponds to a desired time point after starting drying the preceding substrate.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jihoon Jeong, Jung-Min Oh, Kuntack Lee, Hyosan Lee
  • Patent number: 9761749
    Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Takashi Hirose, Naoto Kusumoto
  • Patent number: 9728621
    Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 9522844
    Abstract: A low temperature poly-silicon thin film preparation apparatus and a method for preparing the same are disclosed, the preparation apparatus comprises a substrate cleaning tank and an ozone generating device connected thereto, such that not only can blow off residual liquid on a surface of a glass substrate, but can also allow the glass substrate to directly contact the ozone, such that a silicon film on the surface of the glass substrate is more smooth and less impure, and an oxide film formed on the surface is more uniform since it contacts with the ozone at the first time after being cleaned by hydrofluoric acid, therefore the crystalline effect is more excellent.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: December 20, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Jia Li
  • Patent number: 8956884
    Abstract: A non-abrading method to facilitate bonding of semiconductor components, such as silicon wafers, that have micro structural defects in a bonding interface surface. In a preferred method, micro structural defects are removed by forming an oxide layer on the bonding interface surface to a depth below the level of the defect, and then removing the oxide layer to expose a satisfactory surface for bonding, thereby increasing line yield and reducing scrap triggers in fabrication facilities.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 17, 2015
    Assignee: DunAn Microstaq, Inc.
    Inventor: Parthiban Arunasalam
  • Patent number: 8815017
    Abstract: A method of manufacturing a semiconductor device includes: holding a semiconductor substrate with a surface inclined with respect to the vertical direction and the horizontal direction; and immersing the semiconductor substrate in a cleaning solution including an acid.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Masayuki Takeda, Norikazu Nakamura, Junichi Kon
  • Patent number: 8722545
    Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 13, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Hong-Gap Chua, Yee-Chung Chan, Mei-Yu Muk
  • Patent number: 8716149
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain
  • Patent number: 8703605
    Abstract: A method for forming a contact opening, such as a via hole, is provided. In the method, a sacrificial layer is deposited over a damascene feature prior to exposing a conductor formed in a substrate at a bottom of the opening. The sacrificial layer is provided to prevent damage or contamination of materials used. Even after the conductor has been exposed once or more times, the sacrificial layer can be deposited over the damascene feature to protect it from further damage or contamination by a subsequent process that will further expose the conductor at the contact opening bottom. The exposing step may form a recess in the conductor. By further forming a trench feature over the contact opening, a dual damascene feature can be fabricated.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: April 22, 2014
    Inventor: Byung Chun Yang
  • Patent number: 8623682
    Abstract: A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 7, 2014
    Assignee: Epistar Corporation
    Inventors: Chien-Kai Chung, Ta-Cheng Hsu, Jung-Min Hwang, Min-Hsun Hsieh, Ya-Lan Yang, De-Shan Kuo, Tsun-Kai Ko, Chien-Fu Shen, Ting-Chia Ko, Schang-Jing Hon
  • Patent number: 8613287
    Abstract: An apparatus for preventing stiction of a three-dimensional MEMS (microelectromechanical system) microstructure, the apparatus including: a substrate; and a plurality of micro projections formed on a top surface of the substrate with a predetermined height in such a way that a cleaning solution flowing out from the microstructure disposed thereabove is discharged.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: December 24, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chang Han Je, Myung Lae Lee, Sung Hae Jung, Gunn Hwang, Chang Auck Choi
  • Patent number: 8603899
    Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: December 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
  • Patent number: 8545640
    Abstract: In a substrate processing method according to the present invention, a cleaning liquid nozzle supplies a rinsing liquid to a central portion of a substrate and thereafter moves from a position corresponding to the central portion of the substrate to a position corresponding to a peripheral, edge portion thereof while supplying the rinsing liquid before stopping at the position corresponding to the peripheral edge portion. Next, a drying liquid nozzle moves from the position corresponding to the peripheral edge portion to the position corresponding to the central portion while supplying a drying liquid. Then, the drying liquid nozzle is kept stationary at the position corresponding to the central portion for a predetermined period of time while supplying the drying liquid. Thereafter, a gas nozzle moves from the position corresponding to the central portion to the position corresponding to the peripheral edge portion while supplying an inert gas.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 1, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Teruomi Minami, Naoyuki Okamura, Yosuke Kawabuchi
  • Patent number: 8529707
    Abstract: Provided is a liquid processing apparatus in which a target substrate is horizontally held on a substrate holding unit and rotated around a vertical shaft, and the chemicals are supplied from a chemical supplying unit to the bottom surface of the target substrate that is rotating. In particular, the liquid processing apparatus performs a first step in which the chemicals are supplied to the target substrate while rotating the target substrate at a first rotation speed, a second step in which the supply of the chemicals is halted and the chemicals are thrown off by rotating the target substrate at a second rotation speed higher than the first rotation speed, and a third step in which the rinse liquid is supplied to the target substrate while rotating the target substrate at a third rotation speed equal to or lower than the first rotation speed.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: September 10, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Hiromitsu Namba
  • Patent number: 8507387
    Abstract: Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 13, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Brian Dolan
  • Patent number: 8486742
    Abstract: A method for manufacturing a light-emitting device comprising the steps of: providing a substrate comprising a first surface and a second surface; forming a plurality of cutting lines on the substrate by a laser beam; cleaning the substrate by a chemical solution; and forming a light-emitting stack on an first surface of the substrate after cleaning the substrate.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: July 16, 2013
    Assignee: Epistar Corporation
    Inventors: Chien-Kai Chung, Ta-Cheng Hsu, Jung-Min Hwang, Min-Hsun Hsieh, Ya-Lan Yang, De-Shan Kuo, Tsun-Kai Ko, Chien-Fu Shen, Ting-Chia Ko, Schang-Jing Hon
  • Publication number: 20130164925
    Abstract: A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: June 27, 2013
    Inventors: Duk Eui LEE, Seung Cheol LEE
  • Patent number: 8431488
    Abstract: A cleaning solution is provided. The cleaning solution includes a fluorine containing compound, an inorganic acid, a chelating agent containing a carboxylic group and water for balance. The content of the fluorine containing compound is 0.01-0.5 wt % of. The content of the inorganic acid is 1-5 wt %.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: April 30, 2013
    Assignee: United Microelectronics Corp.
    Inventors: An-Chi Liu, Tien-Cheng Lan
  • Publication number: 20130084709
    Abstract: In a substrate processing apparatus, an anti-static liquid supply part supplies the anti-static liquid having electrical resistivity higher than that of an SPM liquid onto a substrate to puddle an entire upper surface of the substrate with the anti-static liquid, to thereby gradually remove static electricity from the substrate. Then, the processing liquid supply part supplies the SPM liquid onto the substrate to thereby perform an SPM process. In the SPM process, it is thereby possible to prevent a large amount of electric charges from rapidly moving from the substrate to the SPM liquid and prevent any damage to the substrate. Further, by maintaining the electrical resistivity of the anti-static liquid at the target electrical resistivity, it is possible to increase the static elimination efficiency of the substrate and shorten the time required for the static elimination process within the limits of causing no damage to the substrate.
    Type: Application
    Filed: September 27, 2012
    Publication date: April 4, 2013
    Inventors: Masahiro MIYAGI, Kazunori FUJIKAWA
  • Patent number: 8354328
    Abstract: A semiconductor device includes a vertical type semiconductor element formed by using a silicon substrate, a P type impurity diffusion layer being formed at a back surface of the silicon substrate. The surface of the P type impurity diffusion layer is wet etched to expose a single silicon crystal surface of the P type impurity diffusion layer, and a metal layer having a work function of 4.5 eV or more is disposed to the single silicon crystal surface so that an ohmic contact is made between the single silicon crystal surface of the P type impurity diffusion layer and the metal layer without making a silicon-metal alloy layer between the P type impurity diffusion layer and the metal layer.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: January 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Junji Yamasaki
  • Publication number: 20120329284
    Abstract: Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 27, 2012
    Inventors: Tadahiro Ohmi, Hitoshi Morinaga
  • Patent number: 8309472
    Abstract: A method for fabricating semiconductor devices includes providing a semiconductor substrate having a surface region containing one or more contaminants and having an overlying oxide layer. In an embodiment, the one or more contaminants are at least a carbon species. The method includes processing the surface region using at least a wet processing process to selectively remove the overlying oxide layer and expose the surface region including the one or more contaminants. The method includes subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants. The method includes removing the high energy electromagnetic radiation to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: November 13, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: David Gao, Fumitake Mieno
  • Patent number: 8304327
    Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
  • Patent number: 8303723
    Abstract: In a liquid processing apparatus configured to remove, from a substrate including a first film and a second film formed above the first film, the first film and the second film, a first chemical-liquid supply part supplies, to a substrate W, a first liquid for dissolving the first film, a second chemical-liquid supply part supplies a second chemical liquid for weakening the second film, and a fluid supply part serving also as an impact giving part gives a physical impact to the second film so as to break the second film and supplies a fluid for washing away debris of the broken second film. A control device controls the respective parts such that, after the second liquid has been supplied and then the fluid has been supplied from the fluid supply part, the first chemical liquid is supplied.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: November 6, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Teruomi Minami, Fumihiro Kamimura, Kazuki Kosai, Takashi Yabuta, Kenji Yokomizo, Shogo Mizota
  • Publication number: 20120276741
    Abstract: A back end of line cleaning process is performed using a liquid mixture containing at least two benign chemicals that can form a eutectic. In one embodiment, liquid mixtures of urea and choline chloride, at a molar ratio of 2:1, in the temperature range of 40° C. to 70° C. are used to remove etch residues on copper interconnects and dielectric layers created by g-line and DUV resists. In certain embodiments, eutectic, hypereutectic, and hypoeutectic compositions of the at least two benign chemicals are used.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 1, 2012
    Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA
    Inventors: SRINI RAGHAVAN, Dinesh Padmanabhan Ramalekshmi Thanu, Manish K. Keswani
  • Patent number: 8293653
    Abstract: A method of manufacturing a semiconductor device includes a process of removing, by dry etching, an insulating layer which is formed on the top surface of a Ni-containing silicide layer to thereby at least partially expose the Ni-containing silicide layer; and a process of cleaning the exposed portion of the Ni-containing silicide layer using reduced water having a reductive function.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoo Nakayama, Yoshiko Kasama, Eiichi Fujikura, Atsushi Kikuchi
  • Patent number: 8278186
    Abstract: The present invention relates to a wafer cleaning and a wafer bonding method using the same that can improve a yield of cleaning process and bonding property in bonding the cleaned wafer by cleaning the wafer using atmospheric pressure plasma and cleaning solution. The wafer cleaning method includes the steps of providing a process chamber with a wafer whose bonding surface faces upward, cleaning and surface-treating the bonding surface of the wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the wafer, and withdrawing out the wafer from the process chamber.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 2, 2012
    Assignee: Ltrin Co., Ltd.
    Inventors: Yong Won Cha, Dong Chul Kim
  • Patent number: 8268675
    Abstract: Methods of protecting a surface of a copper layer or a copper bonding pad on a semiconductor device against oxidation. A surface of the layer or bonding pad is cleaned by removing an oxidation layer with a plasma. A polymer layer is formed on the cleaned surface of the layer using a plasma-enhanced deposition process to protect the cleaned surface of the layer against exposure to an oxidizing gas.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: September 18, 2012
    Assignee: Nordson Corporation
    Inventors: David Keating Foote, James Donald Getty
  • Publication number: 20120225562
    Abstract: Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 6, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Fatma Arzum Simsek-Ege, Brian Dolan
  • Publication number: 20120164840
    Abstract: A substrate processing method includes a liquid processing process that supplies a processing liquid onto a substrate to process the substrate; a heating process that heats the substrate on which a liquid film of the processing liquid is formed; a supplying process that supplies a volatile processing liquid to the substrate on which the liquid film of the processing liquid is formed; a stopping process that stops the supply of the volatile processing liquid to the substrate; and a drying process that dries the substrate by removing the volatile processing liquid, in which the heating process starts before the supplying process that supplies the volatile processing liquid and the substrate is heated so that the surface temperature of the substrate is higher than a dew point before the surface of the substrate is exposed from the volatile processing liquid.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 28, 2012
    Inventors: Satoru Tanaka, Takehiko Orii, Hirotaka Maruyama, Teruomi Minami, Mitsunori Nakamori
  • Patent number: 8207060
    Abstract: The present invention provides a method of forming a contact opening, such as a via hole, in which a sacrificial layer is deposited prior to exposing a conductor formed in a substrate at a bottom side of the opening to prevent damage and contamination to the materials constituting an integrated circuit device from happening. The exposing may or may not form a recess in the conductor. The present invention also provides a method of forming a contact opening having a recess in the conductor wherein a sacrificial layer is not deposited until the conductor is exposed, but deposited before a recess is formed in the conductor so that a major damage and contamination related to the recess formation can be prevented. By forming a trench feature over a contact opening formed by using the present invention, a dual damascene feature can be fabricated.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: June 26, 2012
    Inventor: Byung Chun Yang
  • Patent number: 8148272
    Abstract: A method for fabricating semiconductor devices, e.g., strained silicon MOS device, includes providing a semiconductor substrate (e.g., silicon wafer) having a surface region, which has one or more contaminants and an overlying oxide layer. The one or more contaminants is at least a carbon species. The method also includes processing the surface region using at least a wet process to selectively remove the oxide layer and expose the surface region. The method further includes subjecting the surface region to a laser treatment process for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants provided on the surface region. The method also includes removing the laser treatment process to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: April 3, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: David Gao, Fumitake Mieno
  • Patent number: 8129212
    Abstract: Methods for surface texturing a crystalline silicon substrate are provided. In one embodiment, the method includes providing a crystalline silicon substrate, wetting the substrate with an alkaline solution comprising a wetting agent, and forming a textured surface with a structure having a depth about 1 ?m to about 10 ?m on the substrate. In another embodiment, a method of performing a substrate texture process includes providing crystalline silicon substrate, pre-cleaning the substrate in a HF aqueous solution, wetting the substrate with a KOH aqueous solution comprising polyethylene glycol (PEG) compound, and forming a textured surface with a structure having a depth about 3 ?m to about 8 ?m on the substrate.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Kapila Wijekoon, Rohit Mishra, Michael P Stewart, Timothy Weidman, Hari Ponnekanti, Tristan R. Holtam
  • Patent number: 8114773
    Abstract: A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NH4F); (d) a chelating agent containing a carboxylic group; (e) triethanolamine (TEA); (f) ethylenediaminetetraacetic acid (EDTA); and (g) water for balance.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: February 14, 2012
    Assignee: United Microelectronics Corp.
    Inventors: An-Chi Liu, Tien-Cheng Lan
  • Publication number: 20120003832
    Abstract: During the patterning of via openings in sophisticated metallization systems of semiconductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.
    Type: Application
    Filed: May 17, 2011
    Publication date: January 5, 2012
    Inventors: Christin Bartsch, Daniel Fischer, Matthias Schaller
  • Patent number: 8071480
    Abstract: Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: December 6, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Jin Lu
  • Patent number: 8058180
    Abstract: This invention provides methods of fabricating semiconductor devices, wherein an alloy layer is formed on a semiconductor substrate to form a substrate structure, which methods include using an aqueous solution diluted ammonia and peroxide mixture (APM) to perform cleaning and/or wet etching treatment steps on the substrate structure.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Won Kwon, Hyung-Ho Ko, Chang-Sup Mun, Woo-Gwan Shim, Im-Soo Park, Yu-Kyung Kim, Jeong-Nam Han
  • Patent number: 8043878
    Abstract: A method for manufacturing a light-emitting device comprising the steps of cutting a light-emitting unit by a laser beam, and cleaning the light-emitting unit by an acid solution to remove by-products resulted from the laser cutting.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: October 25, 2011
    Assignee: Epistar Corporation
    Inventors: Ta-Cheng Hsu, Jung-Min Hwang, Min-Hsun Liu, Ya-Lan Yang, De-Shan Kuo, Tsun-Kai Ko, Chien-Fu Shen, Ting-Chia Ko, Schang-Jing Hon
  • Patent number: 8043903
    Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first recess is formed in a semiconductor substrate to define an active region on the semiconductor substrate. The active region includes a protruding portion of the semiconductor substrate surrounded by the first recess. The protruding portion has a sloped side surface. A first insulating film that fills the first recess is formed. A gate recess is formed in the active region to form a thin film portion that upwardly extends. The thin film portion is positioned between the gate recess and the first insulating film. The thin film portion is a part of the protruding portion. An upper part of the thin film portion is removed by wet-etching to adjust a height of the thin film portion.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: October 25, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Katsumi Koge, Teruyuki Mine, Yasushi Yamazaki