Wet Cleaning Only (epo) Patents (Class 257/E21.228)
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Patent number: 8623682Abstract: A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature.Type: GrantFiled: September 14, 2012Date of Patent: January 7, 2014Assignee: Epistar CorporationInventors: Chien-Kai Chung, Ta-Cheng Hsu, Jung-Min Hwang, Min-Hsun Hsieh, Ya-Lan Yang, De-Shan Kuo, Tsun-Kai Ko, Chien-Fu Shen, Ting-Chia Ko, Schang-Jing Hon
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Patent number: 8613287Abstract: An apparatus for preventing stiction of a three-dimensional MEMS (microelectromechanical system) microstructure, the apparatus including: a substrate; and a plurality of micro projections formed on a top surface of the substrate with a predetermined height in such a way that a cleaning solution flowing out from the microstructure disposed thereabove is discharged.Type: GrantFiled: April 14, 2008Date of Patent: December 24, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Chang Han Je, Myung Lae Lee, Sung Hae Jung, Gunn Hwang, Chang Auck Choi
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Patent number: 8603899Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.Type: GrantFiled: October 25, 2012Date of Patent: December 10, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
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Patent number: 8545640Abstract: In a substrate processing method according to the present invention, a cleaning liquid nozzle supplies a rinsing liquid to a central portion of a substrate and thereafter moves from a position corresponding to the central portion of the substrate to a position corresponding to a peripheral, edge portion thereof while supplying the rinsing liquid before stopping at the position corresponding to the peripheral edge portion. Next, a drying liquid nozzle moves from the position corresponding to the peripheral edge portion to the position corresponding to the central portion while supplying a drying liquid. Then, the drying liquid nozzle is kept stationary at the position corresponding to the central portion for a predetermined period of time while supplying the drying liquid. Thereafter, a gas nozzle moves from the position corresponding to the central portion to the position corresponding to the peripheral edge portion while supplying an inert gas.Type: GrantFiled: June 16, 2011Date of Patent: October 1, 2013Assignee: Tokyo Electron LimitedInventors: Teruomi Minami, Naoyuki Okamura, Yosuke Kawabuchi
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Patent number: 8529707Abstract: Provided is a liquid processing apparatus in which a target substrate is horizontally held on a substrate holding unit and rotated around a vertical shaft, and the chemicals are supplied from a chemical supplying unit to the bottom surface of the target substrate that is rotating. In particular, the liquid processing apparatus performs a first step in which the chemicals are supplied to the target substrate while rotating the target substrate at a first rotation speed, a second step in which the supply of the chemicals is halted and the chemicals are thrown off by rotating the target substrate at a second rotation speed higher than the first rotation speed, and a third step in which the rinse liquid is supplied to the target substrate while rotating the target substrate at a third rotation speed equal to or lower than the first rotation speed.Type: GrantFiled: June 13, 2011Date of Patent: September 10, 2013Assignee: Tokyo Electron LimitedInventor: Hiromitsu Namba
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Patent number: 8507387Abstract: Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun.Type: GrantFiled: May 14, 2012Date of Patent: August 13, 2013Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Brian Dolan
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Patent number: 8486742Abstract: A method for manufacturing a light-emitting device comprising the steps of: providing a substrate comprising a first surface and a second surface; forming a plurality of cutting lines on the substrate by a laser beam; cleaning the substrate by a chemical solution; and forming a light-emitting stack on an first surface of the substrate after cleaning the substrate.Type: GrantFiled: July 26, 2011Date of Patent: July 16, 2013Assignee: Epistar CorporationInventors: Chien-Kai Chung, Ta-Cheng Hsu, Jung-Min Hwang, Min-Hsun Hsieh, Ya-Lan Yang, De-Shan Kuo, Tsun-Kai Ko, Chien-Fu Shen, Ting-Chia Ko, Schang-Jing Hon
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Publication number: 20130164925Abstract: A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer.Type: ApplicationFiled: August 31, 2012Publication date: June 27, 2013Inventors: Duk Eui LEE, Seung Cheol LEE
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Patent number: 8431488Abstract: A cleaning solution is provided. The cleaning solution includes a fluorine containing compound, an inorganic acid, a chelating agent containing a carboxylic group and water for balance. The content of the fluorine containing compound is 0.01-0.5 wt % of. The content of the inorganic acid is 1-5 wt %.Type: GrantFiled: November 10, 2011Date of Patent: April 30, 2013Assignee: United Microelectronics Corp.Inventors: An-Chi Liu, Tien-Cheng Lan
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Publication number: 20130084709Abstract: In a substrate processing apparatus, an anti-static liquid supply part supplies the anti-static liquid having electrical resistivity higher than that of an SPM liquid onto a substrate to puddle an entire upper surface of the substrate with the anti-static liquid, to thereby gradually remove static electricity from the substrate. Then, the processing liquid supply part supplies the SPM liquid onto the substrate to thereby perform an SPM process. In the SPM process, it is thereby possible to prevent a large amount of electric charges from rapidly moving from the substrate to the SPM liquid and prevent any damage to the substrate. Further, by maintaining the electrical resistivity of the anti-static liquid at the target electrical resistivity, it is possible to increase the static elimination efficiency of the substrate and shorten the time required for the static elimination process within the limits of causing no damage to the substrate.Type: ApplicationFiled: September 27, 2012Publication date: April 4, 2013Inventors: Masahiro MIYAGI, Kazunori FUJIKAWA
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Patent number: 8354328Abstract: A semiconductor device includes a vertical type semiconductor element formed by using a silicon substrate, a P type impurity diffusion layer being formed at a back surface of the silicon substrate. The surface of the P type impurity diffusion layer is wet etched to expose a single silicon crystal surface of the P type impurity diffusion layer, and a metal layer having a work function of 4.5 eV or more is disposed to the single silicon crystal surface so that an ohmic contact is made between the single silicon crystal surface of the P type impurity diffusion layer and the metal layer without making a silicon-metal alloy layer between the P type impurity diffusion layer and the metal layer.Type: GrantFiled: December 6, 2010Date of Patent: January 15, 2013Assignee: Renesas Electronics CorporationInventor: Junji Yamasaki
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Publication number: 20120329284Abstract: Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved.Type: ApplicationFiled: August 31, 2012Publication date: December 27, 2012Inventors: Tadahiro Ohmi, Hitoshi Morinaga
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Patent number: 8309472Abstract: A method for fabricating semiconductor devices includes providing a semiconductor substrate having a surface region containing one or more contaminants and having an overlying oxide layer. In an embodiment, the one or more contaminants are at least a carbon species. The method includes processing the surface region using at least a wet processing process to selectively remove the overlying oxide layer and expose the surface region including the one or more contaminants. The method includes subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants. The method includes removing the high energy electromagnetic radiation to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.Type: GrantFiled: August 26, 2010Date of Patent: November 13, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: David Gao, Fumitake Mieno
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Patent number: 8304327Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.Type: GrantFiled: February 25, 2010Date of Patent: November 6, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
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Patent number: 8303723Abstract: In a liquid processing apparatus configured to remove, from a substrate including a first film and a second film formed above the first film, the first film and the second film, a first chemical-liquid supply part supplies, to a substrate W, a first liquid for dissolving the first film, a second chemical-liquid supply part supplies a second chemical liquid for weakening the second film, and a fluid supply part serving also as an impact giving part gives a physical impact to the second film so as to break the second film and supplies a fluid for washing away debris of the broken second film. A control device controls the respective parts such that, after the second liquid has been supplied and then the fluid has been supplied from the fluid supply part, the first chemical liquid is supplied.Type: GrantFiled: December 10, 2009Date of Patent: November 6, 2012Assignee: Tokyo Electron LimitedInventors: Teruomi Minami, Fumihiro Kamimura, Kazuki Kosai, Takashi Yabuta, Kenji Yokomizo, Shogo Mizota
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Publication number: 20120276741Abstract: A back end of line cleaning process is performed using a liquid mixture containing at least two benign chemicals that can form a eutectic. In one embodiment, liquid mixtures of urea and choline chloride, at a molar ratio of 2:1, in the temperature range of 40° C. to 70° C. are used to remove etch residues on copper interconnects and dielectric layers created by g-line and DUV resists. In certain embodiments, eutectic, hypereutectic, and hypoeutectic compositions of the at least two benign chemicals are used.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONAInventors: SRINI RAGHAVAN, Dinesh Padmanabhan Ramalekshmi Thanu, Manish K. Keswani
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Patent number: 8293653Abstract: A method of manufacturing a semiconductor device includes a process of removing, by dry etching, an insulating layer which is formed on the top surface of a Ni-containing silicide layer to thereby at least partially expose the Ni-containing silicide layer; and a process of cleaning the exposed portion of the Ni-containing silicide layer using reduced water having a reductive function.Type: GrantFiled: February 22, 2010Date of Patent: October 23, 2012Assignee: Renesas Electronics CorporationInventors: Tomoo Nakayama, Yoshiko Kasama, Eiichi Fujikura, Atsushi Kikuchi
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Patent number: 8278186Abstract: The present invention relates to a wafer cleaning and a wafer bonding method using the same that can improve a yield of cleaning process and bonding property in bonding the cleaned wafer by cleaning the wafer using atmospheric pressure plasma and cleaning solution. The wafer cleaning method includes the steps of providing a process chamber with a wafer whose bonding surface faces upward, cleaning and surface-treating the bonding surface of the wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the wafer, and withdrawing out the wafer from the process chamber.Type: GrantFiled: October 31, 2007Date of Patent: October 2, 2012Assignee: Ltrin Co., Ltd.Inventors: Yong Won Cha, Dong Chul Kim
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Patent number: 8268675Abstract: Methods of protecting a surface of a copper layer or a copper bonding pad on a semiconductor device against oxidation. A surface of the layer or bonding pad is cleaned by removing an oxidation layer with a plasma. A polymer layer is formed on the cleaned surface of the layer using a plasma-enhanced deposition process to protect the cleaned surface of the layer against exposure to an oxidizing gas.Type: GrantFiled: February 11, 2011Date of Patent: September 18, 2012Assignee: Nordson CorporationInventors: David Keating Foote, James Donald Getty
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Publication number: 20120225562Abstract: Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun.Type: ApplicationFiled: May 14, 2012Publication date: September 6, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Fatma Arzum Simsek-Ege, Brian Dolan
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Publication number: 20120164840Abstract: A substrate processing method includes a liquid processing process that supplies a processing liquid onto a substrate to process the substrate; a heating process that heats the substrate on which a liquid film of the processing liquid is formed; a supplying process that supplies a volatile processing liquid to the substrate on which the liquid film of the processing liquid is formed; a stopping process that stops the supply of the volatile processing liquid to the substrate; and a drying process that dries the substrate by removing the volatile processing liquid, in which the heating process starts before the supplying process that supplies the volatile processing liquid and the substrate is heated so that the surface temperature of the substrate is higher than a dew point before the surface of the substrate is exposed from the volatile processing liquid.Type: ApplicationFiled: December 21, 2011Publication date: June 28, 2012Inventors: Satoru Tanaka, Takehiko Orii, Hirotaka Maruyama, Teruomi Minami, Mitsunori Nakamori
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Patent number: 8207060Abstract: The present invention provides a method of forming a contact opening, such as a via hole, in which a sacrificial layer is deposited prior to exposing a conductor formed in a substrate at a bottom side of the opening to prevent damage and contamination to the materials constituting an integrated circuit device from happening. The exposing may or may not form a recess in the conductor. The present invention also provides a method of forming a contact opening having a recess in the conductor wherein a sacrificial layer is not deposited until the conductor is exposed, but deposited before a recess is formed in the conductor so that a major damage and contamination related to the recess formation can be prevented. By forming a trench feature over a contact opening formed by using the present invention, a dual damascene feature can be fabricated.Type: GrantFiled: December 18, 2008Date of Patent: June 26, 2012Inventor: Byung Chun Yang
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Patent number: 8148272Abstract: A method for fabricating semiconductor devices, e.g., strained silicon MOS device, includes providing a semiconductor substrate (e.g., silicon wafer) having a surface region, which has one or more contaminants and an overlying oxide layer. The one or more contaminants is at least a carbon species. The method also includes processing the surface region using at least a wet process to selectively remove the oxide layer and expose the surface region. The method further includes subjecting the surface region to a laser treatment process for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants provided on the surface region. The method also includes removing the laser treatment process to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.Type: GrantFiled: July 22, 2010Date of Patent: April 3, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: David Gao, Fumitake Mieno
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Patent number: 8129212Abstract: Methods for surface texturing a crystalline silicon substrate are provided. In one embodiment, the method includes providing a crystalline silicon substrate, wetting the substrate with an alkaline solution comprising a wetting agent, and forming a textured surface with a structure having a depth about 1 ?m to about 10 ?m on the substrate. In another embodiment, a method of performing a substrate texture process includes providing crystalline silicon substrate, pre-cleaning the substrate in a HF aqueous solution, wetting the substrate with a KOH aqueous solution comprising polyethylene glycol (PEG) compound, and forming a textured surface with a structure having a depth about 3 ?m to about 8 ?m on the substrate.Type: GrantFiled: March 23, 2009Date of Patent: March 6, 2012Assignee: Applied Materials, Inc.Inventors: Kapila Wijekoon, Rohit Mishra, Michael P Stewart, Timothy Weidman, Hari Ponnekanti, Tristan R. Holtam
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Patent number: 8114773Abstract: A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NH4F); (d) a chelating agent containing a carboxylic group; (e) triethanolamine (TEA); (f) ethylenediaminetetraacetic acid (EDTA); and (g) water for balance.Type: GrantFiled: July 6, 2010Date of Patent: February 14, 2012Assignee: United Microelectronics Corp.Inventors: An-Chi Liu, Tien-Cheng Lan
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Publication number: 20120003832Abstract: During the patterning of via openings in sophisticated metallization systems of semiconductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.Type: ApplicationFiled: May 17, 2011Publication date: January 5, 2012Inventors: Christin Bartsch, Daniel Fischer, Matthias Schaller
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Patent number: 8071480Abstract: Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other.Type: GrantFiled: June 17, 2010Date of Patent: December 6, 2011Assignee: Micron Technology, Inc.Inventor: Jin Lu
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Patent number: 8058180Abstract: This invention provides methods of fabricating semiconductor devices, wherein an alloy layer is formed on a semiconductor substrate to form a substrate structure, which methods include using an aqueous solution diluted ammonia and peroxide mixture (APM) to perform cleaning and/or wet etching treatment steps on the substrate structure.Type: GrantFiled: February 15, 2008Date of Patent: November 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-Won Kwon, Hyung-Ho Ko, Chang-Sup Mun, Woo-Gwan Shim, Im-Soo Park, Yu-Kyung Kim, Jeong-Nam Han
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Patent number: 8043903Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first recess is formed in a semiconductor substrate to define an active region on the semiconductor substrate. The active region includes a protruding portion of the semiconductor substrate surrounded by the first recess. The protruding portion has a sloped side surface. A first insulating film that fills the first recess is formed. A gate recess is formed in the active region to form a thin film portion that upwardly extends. The thin film portion is positioned between the gate recess and the first insulating film. The thin film portion is a part of the protruding portion. An upper part of the thin film portion is removed by wet-etching to adjust a height of the thin film portion.Type: GrantFiled: October 1, 2010Date of Patent: October 25, 2011Assignee: Elpida Memory, Inc.Inventors: Katsumi Koge, Teruyuki Mine, Yasushi Yamazaki
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Patent number: 8043878Abstract: A method for manufacturing a light-emitting device comprising the steps of cutting a light-emitting unit by a laser beam, and cleaning the light-emitting unit by an acid solution to remove by-products resulted from the laser cutting.Type: GrantFiled: February 25, 2009Date of Patent: October 25, 2011Assignee: Epistar CorporationInventors: Ta-Cheng Hsu, Jung-Min Hwang, Min-Hsun Liu, Ya-Lan Yang, De-Shan Kuo, Tsun-Kai Ko, Chien-Fu Shen, Ting-Chia Ko, Schang-Jing Hon
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Patent number: 7994063Abstract: Disclosed is a method for cleaning a semiconductor substrate that can solve a problem of a conventional cleaning method which should include at least five steps for cleaning a substrate such as a semiconductor substrate. The method for cleaning a semiconductor substrate comprises a first step of cleaning a substrate with ultrapure water containing ozone, a second step of cleaning the substrate with ultrapure water containing a surfactant, and a third step of removing an organic compound derived from the surfactant, with a cleaning liquid containing ultrapure water and 2-propanol. After the third step, plasma of noble gas such as krypton is applied to the substrate to further remove the organic compound derived from the surfactant.Type: GrantFiled: April 10, 2009Date of Patent: August 9, 2011Assignees: National University Corporation Tohoku University, Stella Chemifa CorporationInventors: Tadahiro Ohmi, Akinobu Teramoto, Rui Hasebe, Masayuki Miyashita
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Publication number: 20110183522Abstract: A method is provided for processing a wafer used in fabricating semiconductor devices. The method can comprise forming high-aspect ratio features on the wafer, which is followed by wet processing and drying. During drying, pattern collapse can occur. This pattern collapse can be repaired to allow for additional processing of the wafer. In some instance, pattern collapse can be repaired via etching where the etching breaks bonds that can have formed during pattern collapse.Type: ApplicationFiled: January 26, 2010Publication date: July 28, 2011Applicant: LAM RESEARCH CORPORATIONInventors: Katrina Mikhaylichenko, Denis Syomin, Qian Fu, Glenn W. Gale, Shenjian Liu, Mark H. Wilcoxson
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Patent number: 7985683Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.Type: GrantFiled: May 26, 2010Date of Patent: July 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Tomita, Tatsuhiko Koide, Hisashi Okuchi, Kentaro Shimayama, Hiroyasu Iimori, Linan Ji
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Patent number: 7968506Abstract: After trench line pattern openings and via pattern openings are formed in a inter-metal dielectric insulation layer of a semiconductor wafer using trench-first dual damascene process, the wafer is wet cleaned in a single step wet clean process using a novel wet clean solvent composition. The wet clean solvent effectively cleans the dry etch residue from the plasma etching of the dual damascene openings, etches back the TiN hard mask layer along the dual damascene openings and forms a recessed surface at the conductor metal from layer below exposed at the bottom of the via openings of the dual damascene openings.Type: GrantFiled: September 3, 2008Date of Patent: June 28, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Li Chou, Syun-Ming Jang, Jyu-Horng Shieh, Chih-Yuan Ting
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Patent number: 7955440Abstract: After a water film is formed on a wafer front surface in a chamber, the water film is supplied sequentially with an oxidizing component of an oxidation gas, an organic acid component of an organic acid mist, an HF component of an HF gas, the organic acid mist, and the oxidizing component of the oxidation gas. As a result, the HF component and the organic acid component provide cleaning effect on the wafer surface, and a concentration of the cleaning components in the water film within a wafer surface can be even.Type: GrantFiled: November 21, 2008Date of Patent: June 7, 2011Assignee: Sumco CorporationInventors: Shigeru Okuuchi, Kazushige Takaishi
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Publication number: 20110117751Abstract: Composition and method to remove undoped silicon-containing materials from microelectronic devices at rates greater than or equal to the removal of doped silicon-containing materials.Type: ApplicationFiled: March 6, 2009Publication date: May 19, 2011Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.Inventors: Prerna Sonthalia, Emanuel I. Cooper, David Minsek, Peng Zhang, Melissa A. Petruska, Brittany Serke, Trace Quentin Hurd
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Patent number: 7939436Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.Type: GrantFiled: January 14, 2009Date of Patent: May 10, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Min-Sang Kim, Keun-Hwi Cho, Ji-Myoung Lee
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Patent number: 7935554Abstract: Provided are a semiconductor light emitting device having a nano pattern and a method of manufacturing the semiconductor light emitting device. The semiconductor light emitting device includes: a semiconductor layer comprising a plurality of nano patterns, wherein the plurality of nano patterns are formed inside the semiconductor layer; and an active layer formed on the semiconductor layer. The optical output efficiency is increased and inner defects of the semiconductor light emitting device are reduced.Type: GrantFiled: March 19, 2009Date of Patent: May 3, 2011Assignee: Samsung LED Co., Ltd.Inventors: Jeong-wook Lee, Youn-joon Sung, Ho-sun Paek, Hyun-soo Kim, Joo-sung Kim, Suk-ho Yoon
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Publication number: 20110086499Abstract: A method for removing a photoresist is disclosed. First, a substrate including a patterned photoresist is provided. Second, an ion implantation is carried out on the substrate. Then, a non-oxidative pre-treatment is carried out on the substrate. The non-oxidative pre-treatment provides hydrogen, a carrier gas and plasma. Later, a photoresist-stripping step is carried out so that the photoresist can be completely removed.Type: ApplicationFiled: October 13, 2009Publication date: April 14, 2011Inventors: Chin-Cheng Chien, Chan-Lon Yang, Chiu-Hsien Yeh
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Patent number: 7879724Abstract: A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing.Type: GrantFiled: March 20, 2008Date of Patent: February 1, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Naoki Idani
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Publication number: 20110018105Abstract: There is provided a method of producing a nitride-based compound semiconductor device that suppresses the adhesion of foreign matters including impurity, fine particles and the like on a surface of a compound semiconductor. The method of producing a nitride-based compound semiconductor device in accordance with the present invention includes the steps of: preparing a nitride-based compound semiconductor (or a substrate preparation step); and cleaning. In the step of cleaning, the nitride-based compound semiconductor is cleaned with a cleaning liquid having a pH of 7.1 or higher ultrasonically.Type: ApplicationFiled: September 24, 2010Publication date: January 27, 2011Inventors: Akihiro Hachigo, Takayuki Nishiura
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Publication number: 20110021028Abstract: Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the steps of providing a partially-completed semiconductor device including a first feature formed in a porous material, wet cleaning the partially-completed semiconductor device with an aqueous cleaning solvent, exposing the partially-completed semiconductor device to a liquid chemical that forms an azeotropic mixture with water, and inducing evaporation of the azeotropic mixture to remove residual water from within the porous material absorbed during the wet cleaning step.Type: ApplicationFiled: July 23, 2009Publication date: January 27, 2011Applicant: GLOBALFOUNDRIES INC.Inventor: E. Todd Ryan
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Patent number: 7838425Abstract: A method of treating the surface of a semiconductor substrate has cleaning the semiconductor substrate having a pattern formed thereon by using a chemical solution, removing the chemical solution by using pure water, forming a water repellent protective film on the surface of the semiconductor substrate, rinsing the semiconductor substrate by using pure water, and drying the semiconductor substrate.Type: GrantFiled: October 24, 2008Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Tomita, Hiroyasu Iimori, Hisashi Okuchi, Tatsuhiko Koide, Linan Ji
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Patent number: 7838431Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include providing a substrate having at least one of a defect or a contaminant disposed on or near a surface of the substrate; and selectively annealing a portion of the substrate with a laser beam in the presence of a process gas comprising hydrogen. The laser beam may be moved over the substrate or continuously, or in a stepwise fashion. The laser beam may be applied in a continuous wave or pulsed mode. The process gas may further comprise an inert gas, such as, at least one of helium, argon, or nitrogen. A layer of material may be subsequently deposited atop the annealed substrate.Type: GrantFiled: June 20, 2008Date of Patent: November 23, 2010Assignee: Applied Materials, Inc.Inventor: Errol Sanchez
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Patent number: 7811936Abstract: A method produces a semiconductor device having an interconnection structure disposed above a substrate, wherein the interconnection structure has an interconnection and an insulator layer including a low-permittivity layer. The method includes an etching step forming openings in the insulator layer to expose a surface of the interconnection by dry etching, a cleaning step cleaning the surface of the interconnection and the openings in the insulator layer, and a forming step forming another interconnection by filling a conductor material into the openings. The cleaning step includes a first cleaning process using a cleaning liquid, a rinsing process using a rinsing liquid including water and carbonic acid or organic acid, and a second cleaning process using a neutral or alkaline hydrogen aqueous solution that is supplied to the surface of the interconnection and the openings in the insulator layer.Type: GrantFiled: January 31, 2008Date of Patent: October 12, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Yukio Takigawa
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Publication number: 20100248477Abstract: It is disclosed a cleaning liquid used in a process for forming a dual damascene structure comprising steps of etching a low dielectric layer (low-k layer) accumulated on a substrate having thereon a metallic layer to form a first etched-space; charging a sacrifice layer in the first etched-space; partially etching the low dielectric layer and the sacrifice layer to form a second etched-space connected to the first etched-space; and removing the sacrifice layer remaining in the first etched-space with the cleaning liquid, wherein the cleaning liquid comprises (a) 1-25 mass % of a quaternary ammonium hydroxide, such as TMAH and choline (b) 30-70 mass % of a water soluble organic solvent, and (c) 20-60 mass % of water.Type: ApplicationFiled: June 9, 2010Publication date: September 30, 2010Inventors: Shigeru Yokoi, Kazumasa Wakiya
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Patent number: 7803721Abstract: A semiconductor device includes a deposited-type insulating film disposed on a substrate; a coating-type insulating film disposed on a surface of the deposited-type insulating film and having a film density which is lower than a film density of the deposited-type insulating film; and an intermediate insulating film disposed between the deposited-type insulating film and the coating-type insulating film and having a film density which is intermediate between the film density of the deposited-type insulating film and the film density of the coating-type insulating film.Type: GrantFiled: March 14, 2007Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Iwasawa
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Publication number: 20100233854Abstract: Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication.Type: ApplicationFiled: October 15, 2009Publication date: September 16, 2010Applicant: UTAC Thai LimitedInventors: Woraya Benjavasukul, Thipyaporn Somrubpornpinan, Panikan Charapaka
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Patent number: 7776757Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F-] concentration greater than 0.01M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than ?1.4 volts.Type: GrantFiled: January 15, 2009Date of Patent: August 17, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Simon Su-Horng Lin, Yu-Ming Lee, Shao-Yen Ku, Chi-Ming Yang, Chyi-Shyuan Chern, Chin-Hsiang Lin
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Patent number: 7776754Abstract: This disclosure is concerned a method of manufacturing a semiconductor device which includes providing an dielectric film on a substrate; providing a mask material on the dielectric film; etching the dielectric film using the mask material; performing a first treatment of removing a metal residue generated by etching the dielectric film; performing a second treatment of making a sidewall of the dielectric film formed by etching the dielectric film hydrophobic; and performing a third treatment of removing a silicon residue generated by etching the dielectric film.Type: GrantFiled: October 11, 2006Date of Patent: August 17, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Uozumi, Kazuhiko Takase, Tsuyoshi Matsumura