Composed Of Alternated Layers Or Of Mixtures Of Nitrides And Oxides Or Of Oxynitrides, E.g., Formation Of Oxynitride By Oxidation Of Nitride Layer (epo) Patents (Class 257/E21.267)
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Patent number: 7446000Abstract: A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.Type: GrantFiled: July 18, 2007Date of Patent: November 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-hak Lee, Kwang-dong Yoo, Sang-bae Yi, Soo-cheol Lee, Mueng-ryul Lee
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Patent number: 7435674Abstract: Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.Type: GrantFiled: March 27, 2006Date of Patent: October 14, 2008Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Louis C. Hsu, Rajiv V. Joshi
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Patent number: 7435640Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.Type: GrantFiled: November 8, 2005Date of Patent: October 14, 2008Assignee: United Microelectronics Corp.Inventors: Yun-Ren Wang, Ying-Wei Yen, Shu-Yen Chan, Kuo-Tai Huang
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Publication number: 20080246125Abstract: The present invention is a semiconductor device characterized by including a substrate, an insulating film consisting of a fluorine added carbon film formed on the substrate, a barrier layer consisting of a silicon nitride film and a film containing silicon, carbon, and nitride formed on the insulating film, and a hard mask layer having a film containing silicon and oxygen formed on the barrier layer, wherein the barrier layer consists of a silicon nitride film and a film containing silicon, carbon, and nitride that are laminated from the bottom in that order, and functions to prevent the fluorine in the fluorine added carbon film from moving to the hard mask layer.Type: ApplicationFiled: June 13, 2008Publication date: October 9, 2008Applicant: TOKYO ELECTRON LIMITEDInventor: Yoshiyuki Kikuchi
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Patent number: 7432548Abstract: Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The silicon lanthanide oxynitride film may be arranged as a layered structure having one or more monolayers. Metal electrodes may be disposed on a dielectric containing a silicon lanthanide oxynitride film.Type: GrantFiled: August 31, 2006Date of Patent: October 7, 2008Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
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Patent number: 7432216Abstract: The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm?2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm?2 or more.Type: GrantFiled: August 15, 2006Date of Patent: October 7, 2008Assignee: Hitachi, Ltd.Inventors: Yasuhiro Shimamoto, Shinichi Saito, Shimpei Tsujikawa
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Publication number: 20080242109Abstract: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber. The wet process gas and the nitriding gas form a processing ambient that reacts with the substrate such that an oxynitride film grows on the substrate. In yet another embodiment, the method further comprises flowing a diluting gas into the process chamber while flowing the wet process gas to control a growth rate of the oxynitride film. In another embodiment, the method further comprises annealing the substrate and the oxynitride film in an annealing gas. According to embodiments of the method where the substrate is silicon, a silicon oxynitride film forms that exhibits a nitrogen peak concentration of at least approximately 6 atomic % and an interface state density of less than approximately 1.5×1012 per cc.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Kimberly G. Reid, Anthony Dip
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Patent number: 7416987Abstract: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.Type: GrantFiled: June 22, 2006Date of Patent: August 26, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Masahiro Kiyotoshi
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Patent number: 7405125Abstract: Methods for forming a tunnel oxide structure device and methods for forming the structure are described. A structure comprising nitrogen is formed on a semiconductor substrate. The structure is oxidized. Nitrogen of the oxide structure is redistributed to form a region of concentrated nitrogen. Oxidizing the structure and redistributing the nitrogen is performed via radical oxidation. Nitrogen is added to the oxide structure. The region of concentrated nitrogen helps to regulate the depth of the added nitrogen.Type: GrantFiled: June 1, 2004Date of Patent: July 29, 2008Assignee: Macronix International Co., Ltd.Inventor: Szu-Yu Wang
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Patent number: 7405482Abstract: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.Type: GrantFiled: January 27, 2006Date of Patent: July 29, 2008Assignee: Infineon Technologies AGInventors: Kil-Ho Lee, Chan Lim
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Patent number: 7393731Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.Type: GrantFiled: June 21, 2005Date of Patent: July 1, 2008Assignee: Renesas Technology Corp.Inventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
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Patent number: 7371636Abstract: A method for fabricating a storage node contact hole of a semiconductor device includes: forming an inter-layer insulation layer over a substrate; forming a hard mask over the inter-layer insulation layer; etching the inter-layer insulation layer to form a storage node contact hole; forming a passivation layer to fill the storage node contact hole; removing the hard mask with an etch rate of the hard mask faster than that of the inter-layer insulation layer; and removing the passivation layer.Type: GrantFiled: October 12, 2006Date of Patent: May 13, 2008Assignee: Hynix Semiconductor Inc.Inventor: Ki-Won Nam
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Patent number: 7368381Abstract: The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the chamber. The mixture includes a precursor of a desired material within a supercritical fluid. The precursor is relatively reactive under one set of conditions and is relatively non-reactive under another set of conditions. The precursor and supercritical fluid mixture is initially provided in the chamber under the conditions at which the precursor is relatively non-reactive. Subsequently, and while maintaining the supercritical state of the supercritical fluid, the conditions within the reaction chamber are changed to the conditions under which the precursor is relatively reactive. The precursor reacts to form the desired material, and at least some of the desired material forms a film on the substrate.Type: GrantFiled: April 28, 2006Date of Patent: May 6, 2008Assignee: Micron Technology, Inc.Inventors: Demetrius Sarigiannis, Garo J Derderian, Cem Basceri
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Patent number: 7366026Abstract: A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an ONO layer on the semiconductor substrate; a first control gate on the ONO layer; second and third control gates on the ONO layer at both sides of the first control gate; and source and drain regions in the surface of the semiconductor substrate at both sides of the second and third control gates.Type: GrantFiled: June 30, 2004Date of Patent: April 29, 2008Assignee: Dongbu Hitek Co., Ltd.Inventor: Sang Bum Lee
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Patent number: 7358198Abstract: A method is provided with: arranging nitrogen atoms on a surface of a silicon substrate; performing a heat treatment in a hydrogen atmosphere so that the nitrogen atoms and silicon atoms existing on the surface of the silicon substrate are brought into a three-coordinate bond state; and forming a silicon oxide film on the silicon substrate with the three-coordinate bond state of nitrogen atoms and the silicon atoms being maintained.Type: GrantFiled: October 17, 2005Date of Patent: April 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Nobutoshi Aoki, Koichi Kato, Katsuyuki Sekine, Ichiro Mizushima
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Publication number: 20080073701Abstract: A nonvolatile semiconductor memory device includes an array of nonvolatile memory cell transistors, each of which is configured such that a tunnel insulation film, a floating gate electrode, a floating gate insulation film and a control gate electrode are stacked on a surface of a semiconductor substrate. A mean roughness of an interface between a polysilicon, of which the floating gate electrode is formed, and the floating gate insulation film is 1.5 nm or less.Type: ApplicationFiled: September 20, 2007Publication date: March 27, 2008Inventors: Hiroshi Akahori, Wakako Takeuchi
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Patent number: 7348278Abstract: A method of making a nitride-based compound semiconductor crystal has the step of growing a nitride-based compound semiconductor crystal with a predetermined thickness by using a nitride-based compound semiconductor substrate as a seed crystal. The nitride-based compound semiconductor substrate as the seed crystal is polished at both surfaces thereof.Type: GrantFiled: July 13, 2005Date of Patent: March 25, 2008Assignee: Hitachi Cable, Ltd.Inventor: Yuichi Oshima
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Patent number: 7344954Abstract: A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.Type: GrantFiled: January 3, 2006Date of Patent: March 18, 2008Assignee: United Microelectonics Corp.Inventors: Ta-Chuan Yeh, Ni-Min Chung, Kao-Su Huang, Yung-Chang Lin, Ruey-Chyr Lee, Chien-Kuo Wang
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Patent number: 7335940Abstract: A method for manufacturing flash memory is provided. A tunneling dielectric layer, a conductive layer and a patterned mask layer that exposes a portion of the conductive layer are formed on a substrate. An oxide layer is formed on the exposed conductive layer so that the conductive layer is partitioned through the oxide layer into blocks. The oxide layer is removed and an inter-gate dielectric layer is formed in the opening. A control gate that completely fills the opening is formed. A cap layer is formed over the control gate. The mask layer is then removed. Using the cap layer as a mask, a portion of the conductive layer is removed to form two floating gates under the control gate. An insulating layer is formed on the substrate. Source/drain regions are formed in the substrate on the respective sides of the control gate.Type: GrantFiled: January 19, 2006Date of Patent: February 26, 2008Assignee: Powerchip Semiconductor Corp.Inventors: I-Chun Chuang, Cheng-Yuan Hsu, Jui-Yu Pan
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Publication number: 20080032509Abstract: A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitride layer by using an atomic layer deposition process, to obtain a gate insulating film having a higher nitrogen concentration, while suppressing the nitrogen concentration in the vicinity of the gate insulating film and the silicon substrate.Type: ApplicationFiled: August 3, 2007Publication date: February 7, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Takuo OHASHI, Taishi KUBOTA
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Publication number: 20070284657Abstract: In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.Type: ApplicationFiled: May 17, 2007Publication date: December 13, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Wataru Sumida
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Patent number: 7300855Abstract: In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to protect it against oxidation, an insulation layer is applied to the silicon nitride layer, and a reoxidation process is carried out. In the reoxidation process are generated oxygen radicals which are passed through the insulation layer to the silicon nitride layer in order to convert silicon nitride of the nitride layer into silicon dioxide.Type: GrantFiled: November 9, 2005Date of Patent: November 27, 2007Assignee: Infineon Technologies AGInventor: Uwe Wellhausen
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Patent number: 7297641Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.Type: GrantFiled: July 18, 2003Date of Patent: November 20, 2007Assignee: ASM America, Inc.Inventors: Michael A. Todd, Keith D. Weeks, Christiaan J. Werkhoven, Christophe F. Pomarede
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Patent number: 7294582Abstract: Sequential processes are conducted in a batch reaction chamber to form ultra high quality silicon-containing compound layers, e.g., silicon nitride layers, at low temperatures. Under reaction rate limited conditions, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. Trisilane flow is interrupted. A silicon nitride layer is then formed by nitriding the silicon layer with nitrogen radicals, such as by pulsing the plasma power (remote or in situ) on after a trisilane step. The nitrogen radical supply is stopped. Optionally non-activated ammonia is also supplied, continuously or intermittently. If desired, the process is repeated for greater thickness, purging the reactor after each trisilane and silicon compounding step to avoid gas phase reactions, with each cycle producing about 5-7 angstroms of silicon nitride.Type: GrantFiled: August 25, 2005Date of Patent: November 13, 2007Assignee: ASM International, N.V.Inventors: Ruben Haverkort, Yuet Mei Wan, Marinus J. De Blank, Cornelius A. van der Jeugd, Jacobus Johannes Beulens, Michael A. Todd, Keith D. Weeks, Christian J. Werkhoven, Christophe F. Pomarede
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Publication number: 20070161175Abstract: Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.Type: ApplicationFiled: December 26, 2006Publication date: July 12, 2007Inventor: Young Seong Lee
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Publication number: 20070128887Abstract: Integrated circuits and methods of making an integrated circuit are disclosed. The disclosed methods include providing a substrate having at least one device structure thereon; providing a first barrier layer over the substrate and the at least one device structure; providing a dielectric layer formed by a spin-on-glass process; and providing a second barrier layer over the dielectric layer, wherein the second barrier layer is a compressive layer. Integrated circuits described herein include a first barrier layer over the substrate and the at least one device structure; a dielectric layer formed by a spin-on-glass process; and a second barrier layer over the dielectric layer, wherein the second barrier layer is a compressive layer.Type: ApplicationFiled: December 7, 2005Publication date: June 7, 2007Inventors: Lee-Jen Chen, Chin-Ta Su
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Patent number: 7226874Abstract: A substrate processing method forming an oxynitride film by nitriding an oxide film formed on a silicon substrate includes a nitridation processing step that nitrides a surface of the oxide film by radicals or ions formed by exciting a nitrogen gas by microwave-excited plasma, the nitridation processing is conducted at a substrate temperature of 500° C. or less by setting an electron temperature of the microwave-excited plasma to 2 eV or less, and by setting the resident time of oxygen in the processing space in which the substrate to be processed is held, to two seconds or less.Type: GrantFiled: November 12, 2004Date of Patent: June 5, 2007Assignee: Tokyo Electron LimitedInventors: Seiji Matsuyama, Takuya Sugawara, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki
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Patent number: 7217614Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition using feed gases comprising a silicon hydride, H2 and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In one implementation, the chemical vapor depositing comprises feed gases of a silicon hydride and ammonia, with the depositing comprising increasing internal reactor temperature from below 500° C.Type: GrantFiled: January 7, 2003Date of Patent: May 15, 2007Assignee: Micron Technology, Inc.Inventor: Randhir P.S. Thakur
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Publication number: 20070093070Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Kouros Ghandehari, Hirokazu Tokuno, David Matsumoto, Christopher Raeder, Christopher Foster, Weidong Qian, Minh Ngo
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Publication number: 20070066087Abstract: According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device having active regions including a SONOS device region, a high voltage device region, and a logic device region, includes defining the active regions by forming a device isolation region on a semiconductor substrate; performing ion-implantation in the SONOS device region to control a threshold voltage of a SONOS device; performing ion-implantation in the high voltage device region to form a well; performing ion-implantation in the SONOS device region and the logic device region to form a well; and forming an ONO pattern on the SONOS device region, generally by performing a photolithography and etching process on the ONO layer.Type: ApplicationFiled: December 29, 2005Publication date: March 22, 2007Inventor: Jin-Hyo Jung
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Publication number: 20070048926Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of electronic systems. The lanthanum aluminum oxynitride film may be structured as one or more monolayers. The lanthanum aluminum oxynitride film may be formed by atomic layer deposition.Type: ApplicationFiled: August 31, 2005Publication date: March 1, 2007Inventors: Kie Ahn, Leonard Forbes
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Publication number: 20070034974Abstract: A semiconductor device comprises a semiconductor region including silicon, and an insulating film including silicon, oxygen, nitrogen, and helium, the dielectric film provided on the semiconductor region, and the dielectric film having a concentration distribution with respect to a film thickness direction, the concentration distribution having a maximal value of concentration of the helium in a surface portion on the semiconductor region side and a maximal value of concentration of the nitrogen in a surface portion on a side opposite to the semiconductor region.Type: ApplicationFiled: October 25, 2006Publication date: February 15, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Seiji Inumiya, Ichiro Mizushima
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Publication number: 20070029626Abstract: A silicon oxynitride film is manufactured using SiH4, N2O and H2 by plasma CVD, and it is applied to the gate insulating film (1004 in FIG. 1A) of a TFT. The characteristics of the silicon oxynitride film are controlled chiefly by changing the flow rates of N2O and H2. A hydrogen concentration and a nitrogen concentration in the film can be increased by the increase of the flow rate of H2. Besides, the hydrogen concentration and the nitrogen concentration in the film can be decreased to heighten an oxygen concentration by the increase of the flow rate of N2O. The gate insulating film ensures the stability and reliability of the characteristics of the TFT, such as the threshold voltage (Vth) and sub-threshold constant (S value) thereof.Type: ApplicationFiled: October 10, 2006Publication date: February 8, 2007Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsunori Sakama, Noriko Ishimaru, Taketomi Asami, Shunpei Yamazaki
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Patent number: 7169715Abstract: In one embodiment, the present invention includes introducing a conventional precursor and an organic precursor having an organic porogen into a vapor deposition apparatus; and forming a dielectric layer having the organic porogen on a substrate within the vapor deposition apparatus from the precursors. In certain embodiments, at least a portion of the organic porogen may be removed after subsequent processing, such as dual damascene processing.Type: GrantFiled: March 21, 2003Date of Patent: January 30, 2007Assignee: Intel CorporationInventors: Andrew W. Ott, Grant M. Kloster, Robert P. Meagley, Michael D. Goodner
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Patent number: 7166899Abstract: A silicon oxynitride film is manufactured using SiH4, N2O and H2 by plasma CVD, and it is applied to the gate insulating film (1004 in FIG. 1A) of a TFT. The characteristics of the silicon oxynitride film are controlled chiefly by changing the flow rates of N2O and H2. A hydrogen concentration and a nitrogen concentration in the film can be increased by the increase of the flow rate of H2. Besides, the hydrogen concentration and the nitrogen concentration in the film can be decreased, to heighten an oxygen concentration by the increase of the flow rate of N2O. The gate insulating film ensures the stability and reliability of the characteristics of the TFT, such as the threshold voltage (Vth) and sub-threshold constant (S value) thereof.Type: GrantFiled: July 15, 2005Date of Patent: January 23, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsunori Sakama, Noriko Ishimaru, Taketomi Asami, Shunpei Yamazaki
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Patent number: 7138692Abstract: A gate insulating film and a gate electrode are formed on a silicon substrate. The gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen. The fluorine concentration is high in the vicinity of an interface with the silicon substrate and progressively decreases with decreasing distance from the gate electrode. The nitrogen concentration is high in the vicinity of an interface with the gate electrode and progressively decreases with decreasing distance from the silicon substrate. The fluorine concentration in the vicinity of the interface with the silicon substrate is preferably 1×1019 cm?3 or more. The nitrogen concentration in the vicinity of the interface with the gate electrode is preferably 1×1020 cm?3 or more.Type: GrantFiled: December 17, 2004Date of Patent: November 21, 2006Assignee: Fujitsu LimitedInventors: Yasuyuki Tamura, Takaoki Sasaki
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Patent number: 7091128Abstract: A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains.Type: GrantFiled: November 4, 2005Date of Patent: August 15, 2006Assignee: International Business Machines CorporationInventors: Atul C. Ajmera, Andres Bryant, Percy V. Gilbert, Michael A. Gribelyuk, Edward P. Maciejewski, Renee T. Mo, Shreesh Narasimha