Abstract: A method for forming a silicon nitride film to cover a stepped portion formed by exposed surfaces of first and second base films in a substrate, includes: forming a nitride film or a seed layer to cover the stepped portion, wherein the nitride film is formed by supplying, to the substrate, a nitrogen-containing base-film nitriding gas for nitriding the base films, exposing the substrate to plasma and nitriding the surface of the stepped portion, and the seed layer is composed of a silicon-containing film formed by supplying a raw material gas of silicon to the substrate and is configured such that the silicon nitride film uniformly grows on the surfaces of the base films; and forming the silicon nitride film on the seed layer by supplying, to the substrate, a second raw material gas of silicon and a silicon-nitriding gas for nitriding silicon.

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

Abstract: An optical filter has a layer of silicon film deposited onto a metallic substrate surface at a silicon film thickness corresponding to a wavelength of light to be filtered from incoming light. The critical coupling of light to the optical cavity formed by the silicon film on metal surface results in a strong and near perfect absorption of the light at a resonance wavelength and strong absorption in the wavelength region near the peak absorption wavelength. Other wavelengths of the incoming wave are reflected by the device so the spectral content of light is changed. By controlling the thickness of the silicon film and/or other factors, such as the extent to which the silicon film is annealed or the type of metal beneath the silicon film, the wavelength of the light absorbed by the silicon film can be precisely controlled.

Abstract: A spin coating method according to an embodiment includes forming a first material film on an underlying material. The underlying material is rotated while a solution of a second material film is supplied onto an upper surface of the first material film to make the solution stay on the upper surface of the first material film. Rotating of the underlying material is stopped or a rotational speed of the underlying material is reduced to 10 rpm or less. The underlying material is rotated after a first period elapses after the stopping of the rotating of the underlying material, or the rotational speed of the underlying material is increased after the first period elapses after the reducing of the rotational speed of the underlying material to spin off the solution from the upper surface of the first material film.

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor feature, a passivation layer that includes indium sulfide formed over a surface of the semiconductor feature. More particularly, the surface of the semiconductor feature comprises indium-based III-V compound semiconductor material.

Abstract: A step of preparing a silicon carbide substrate, a step of forming a first silicon carbide semiconductor layer on the silicon carbide substrate using a first source material gas, and a step of forming a second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer using a second source material gas are provided. In the step of forming a first silicon carbide semiconductor layer and the step of forming a second silicon carbide semiconductor layer, ammonia gas is used as a dopant gas, and the first source material gas has a C/Si ratio of not less than 1.6 and not more than 2.2, the C/Si ratio being the number of carbon atoms to the number of silicon atoms.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.

Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.

Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.

Abstract: Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen diffusion, which can lead to increasing an effective oxide thickness of the gate dielectric and preventing hafnium-silicon reactions that may lead to higher leakage current.

Abstract: A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided.

Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

Abstract: A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.

Abstract: A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided.

Abstract: A method is provided for depositing a dielectric barrier film including a precursor with silicon, carbon, oxygen, and hydrogen with improved barrier dielectric properties including lower dielectric constant and superior electrical properties. This method will be important for barrier layers used in a damascene or dual damascene integration for interconnect structures or in other dielectric barrier applications. In this example, specific structural properties are noted that improve the barrier performance.

Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.

Abstract: Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface.

Abstract: Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen diffusion, which can lead to increasing an effective oxide thickness of the gate dielectric and preventing hafnium-silicon reactions that may lead to higher leakage current.

Abstract: In some embodiments, the present invention discloses a two-step deposition process for forming hafnium oxide gate dielectric, comprising an interface layer deposition followed by a bulk layer deposition. In the interface layer deposition process, water is used as an oxidizer precursor together with a hafnium-containing precursor. In the bulk layer deposition process, oxygen or ozone is used as an oxidizer precursor together with a hafnium-containing precursor.

Abstract: The present invention discloses a method for replacing chlorine atoms on a film layer. More particularly, sufficient replacement ions for replacing the chlorine atoms are formed in a plasma process by reducing a volume ratio of a gas in a gas mixture (i.e. the film layer may be etched with the ions formed by dissociation of the gas) and dissociation of the gas mixture further decreases the etching reaction to the film layer in a process for replacing the chlorine atoms. In comparison to a conventional process by pure oxygen, the present invention can improve the prior art re-etching problem to avoid affecting an electric property of a thin film transistor, also has an advantage of manufacturing time reduction for an increased production yield.

Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

Abstract: Disclosed herein is a solid-state image pickup device including: a trench formed in an insulating film above a light-receiving portion; a first waveguide core portion provided on an inner wall side of the trench; a second waveguide core portion filled in the trench via the first waveguide core portion; and a rectangular lens formed of the same material as that of the second waveguide core portion and provided integrally with the second waveguide core portion.

Abstract: The beam bending of a MEMS device is minimized by reducing interfacial strength between a sacrificial layer and a MEMS structure.

Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: A vapor deposition method and apparatus including at least two vessels containing a same first source chemical. A controller is programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels, each of the doses having a substantially consistent concentration of the first source chemical. The apparatus may also include at least two vessels containing a same second source chemical. The controller can be programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels containing the second source chemical, each of the doses having a substantially consistent concentration of the second source chemical. The second source chemical can be pulsed to the reaction space after the reaction space is purged of an excess of the first source chemical.

Abstract: Methods for processing substrates are provided herein. In some embodiments, a method for processing a substrate includes providing a substrate having an oxide layer disposed thereon, the oxide layer including one or more defects; and exposing the oxide layer to a plasma formed from a process gas comprising an oxygen-containing gas to repair the one or more defects. In some embodiments, the oxide layer may be formed on the substrate. In some embodiments, forming the oxide layer further comprises depositing the oxide layer atop the substrate. In some embodiments, forming the oxide layer further comprises thermally oxidizing the surface of the substrate to form the oxide layer. In some embodiments, a processing temperature is maintained at about 700 degrees Celsius or below during the thermal oxidation of the surface.

Abstract: A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.

Abstract: A multiphase ultra low k dielectric process is described incorporating a first precursor comprising at least one of carbosilane and alkoxycarbosilane molecules containing the group Si—(CH2)n—Si where n is an integer 1, 2 or 3 and a second precursor containing the group Si—R* where R* is an embedded organic porogen, a high frequency radio frequency power in a PECVD chamber and an energy post treatment including ultraviolet radiation. An ultra low k porous SiCOH dielectric material having at least one of a k in the range from 2.2 to 2.3, 2.3 to 2.4, 2.4 to 2.5, and 2.5 to 2.55 and a modulus of elasticity greater than 5, 6, 7.8 and 9 GPa, respectively and a semiconductor integrated circuit comprising interconnect wiring having porous SiCOH dielectric material as described above.

Abstract: The method is adapted for forming an aluminum nitride thin film having a high density and a high resistance to thermal shock by a chemical vapor deposition process and includes steps of mixing a gas containing aluminum atoms (Al) and a gas containing nitrogen atoms (N) with a gas containing oxygen atoms (O) and feeding the mixture to a member to be covered by an aluminum nitride thin film.

Abstract: Provided are low temperature methods of depositing hafnium or zirconium containing films using a Hf(BH4)4 precursor, or Zr(BH4)4 precursor, respectively, as well as a co-reactant. The co-reactant can be selected to obtain certain film compositions. Co-reactants comprising an oxidant can be used to deposit oxygen into the film. Accordingly, also provided are films comprising a metal, boron and oxygen, wherein the metal comprises hafnium where a Hf(BH4)4 precursor is used, or zirconium, where a Zr(BH4)4 precursor is used.

Abstract: Methods for forming a film on a substrate in a semiconductor manufacturing process. A reaction chamber a substrate in the chamber are provided. A ruthenium based precursor, which includes ruthenium tetroxide dissolved in a mixture of at least two non-flammable fluorinated solvents, is provided and a ruthenium containing film is produced on the substrate.

Abstract: A method of forming a high-k dielectric material including forming at least two portions of titanium dioxide, the at least two portions of titanium dioxide comprising a first portion comprising amorphous titanium dioxide and a second portion comprising rutile titanium dioxide. A method of forming a high-k dielectric material including forming a first portion of titanium dioxide at a temperature of from about 150° C. to about 350° C. and forming a second portion of titanium dioxide at a temperature of from about 350° C. to about 600° C. A high-k dielectric material is also disclosed.

Abstract: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.

Abstract: Provided are processes for the low temperature deposition of silicon-containing films using carbosilane precursors containing a carbon atom bridging at least two silicon atoms. Certain methods comprise providing a substrate; in a PECVD process, exposing the substrate surface to a carbosilane precursor containing at least one carbon atom bridging at least two silicon atoms; exposing the carbosilane precursor to a low-powered energy sourcedirect plasma to provide a carbosilane at the substrate surface; and densifying the carbosilanestripping away at least some of the hydrogen atoms to provide a film comprising SiC. The SiC film may be exposed to the carbosilane surface to a nitrogen source to provide a film comprising SiCN.

Abstract: The disclosure relates to integrated circuit fabrication and, more particularly, to a semiconductor device with a high-k gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate and a gate structure disposed over the substrate. The gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion, and the dielectric portion comprises a carbon-doped high-k dielectric layer on the substrate and a carbon-free high-k dielectric layer adjacent to the electrode portion.

Abstract: The present invention provides a thin film deposition method, comprising: seasoning a first deposition chamber; seasoning a second deposition chamber; pre-processing the first deposition chamber, depositing a thin film in the first deposition chamber, cleaning the first deposition chamber, post-processing and withdrawing the wafers; pre-processing the second deposition chamber, depositing a thin film in the second deposition chamber, cleaning the second deposition chamber, post-processing and withdrawing the wafers; characterized in that there is a time interval between the step of seasoning the second deposition chamber and the step of seasoning the first deposition chamber. The method of stabilizing the thin film thickness of the present invention can well solve the problem that the thin film on the first pair of wafers of each batch of products becomes thinner or thicker during the deposition.

Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.

Abstract: A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule.

Abstract: Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface.

Abstract: Provided are methods for depositing a cerium doped hafnium containing high-k dielectric film on a substrate. The reagents of specific methods include hafnium tetrachloride, an organometallic complex of cerium and water.

Abstract: A deposition process for coating a substrate with films of a different thickness on front and rear surface of a substrate can be achieve in one growth. The thickness of the film deposition can be controlled by the separation between the substrates. Different separation distances between the substrates in the same chemical bath will result in different film thicknesses on the substrate. Substrates may be arranged to have different separation distances between front and back surfaces, a V-shaped arrangement, or placed next to a curtain with varying separation distances between a substrate and the curtain.

Abstract: Compounds comprising a ligand having a quinoline or isoquinoline moiety and a phenyl moiety, e.g., (iso)pq ligands. In particular, the ligand is further substituted with electron donating groups. The compounds may be used in organic light emitting devices, particularly devices with emission in the deep red part of the visible spectrum, to provide devices having improved properties.

Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

Abstract: A method for fabricating a carbon hard mask layer includes: loading a substrate with a pattern target layer into a chamber; performing a primary thermal treatment on the substrate; depositing a carbon hard mask layer over the pattern target layer by using CxHy gas to perform the primary thermal treatment; performing a secondary thermal treatment on the substrate on which the carbon hard mask layer is deposited; and performing an oxygen treatment on the carbon hard mask layer.

Abstract: Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about 120 ? over the layer of porous aluminum oxide.

Abstract: A dielectric containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric produce a reliable dielectric for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium aluminum oxide film.

Abstract: A semiconductor device manufacturing method includes: forming a first insulating film over the surface of a semiconductor substrate having at least two adjacent protrusions in such a manner that the film thickness between the two protrusions is not less than 1.2 times the height of at least one of the two protrusions; and forming a second insulating film over the first insulating film, the second insulating film being harder than the first insulating film.