Carbon Layer, E.g., Diamond-like Layer (epo) Patents (Class 257/E21.27)
  • Patent number: 10249871
    Abstract: A composite including: at least one selected from a silicon oxide of the formula SiO2 and a silicon oxide of the formula SiOx wherein 0<x<2; and graphene, wherein the silicon oxide is disposed in a graphene matrix.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inhyuk Son, Jonghwan Park, Jaejun Chang, Junhwan Ku, Xiangshu Li, Jaeman Choi
  • Patent number: 9875894
    Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: January 23, 2018
    Assignee: UChicago Argonne, LLC
    Inventors: Anirudha V. Sumant, Diana Berman
  • Patent number: 9512541
    Abstract: There is provided a selective growth method of selectively growing a thin film on exposed surfaces of an underlying insulation film and an underlying metal film, which includes: selectively growing a film whose thickness is decreased by combustion on the underlying metal film using metal of the underlying metal film as a catalyst; and selectively growing a silicon oxide film on the underlying insulation film while combusting the film whose thickness is decreased by combustion.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: December 6, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Akira Shimizu, Masayuki Kitamura
  • Patent number: 8710628
    Abstract: An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and ferroelectric semiconductor material is provided between first and second electrodes. The various embodiments may be part of a memory array.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: April 29, 2014
    Assignee: Spansion LLC
    Inventor: Juri H. Krieger
  • Patent number: 8652946
    Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: February 18, 2014
    Assignee: Uchicago Argonne, LLC.
    Inventors: Anirudha V. Sumant, Alexander Balandin
  • Patent number: 8637413
    Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: January 28, 2014
    Assignees: Sandisk 3D LLC, Kabushiki Kaisha Toshiba
    Inventors: Charlene Chen, Dipankar Pramanik
  • Patent number: 8455366
    Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. M. Fuller, Pratik P. Joshi, Mahmoud Khojasteh, Rajiv M. Ranade, George G. Totir
  • Patent number: 8426309
    Abstract: Embodiments of the present invention provide methods for fabricating graphene nanoelectronic devices with semiconductor compatible processes, which allow wafer scale fabrication of graphene nanoelectronic devices. Embodiments of the present invention also provide methods for passivating graphene nanoelectronic devices, which enable stacking of multiple graphene devices and the creation of high density graphene based circuits. Other embodiments provide methods for producing devices with graphene layer segments having multiple thicknesses.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: April 23, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: Jonathan W. Ward, Michael J. O'Connor
  • Patent number: 8399366
    Abstract: A method is provided for forming a semiconductor device. The method includes providing a substrate on a substrate holder in a process chamber, where the substrate contains a raised feature having a top surface and a sidewall surface, and flowing a process gas into the process chamber, where the process gas contains a hydrocarbon gas, an oxygen-containing gas, and optionally argon or helium. The method further includes maintaining a process gas pressure of at least 1 Torr in the process chamber, forming a plasma from the process gas using a microwave plasma source, and exposing the substrate to the plasma to deposit a conformal amorphous carbon film over the surfaces of the raised feature.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: March 19, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Hiroyuki Takaba
  • Patent number: 8367556
    Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. M. Fuller, Pratik P. Joshi, Mahmoud Khojasteh, Rajiv M. Ranade, George G. Totir
  • Patent number: 8309424
    Abstract: Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of spaced apart electrically conductive lines, and to have sacrificial material between the electrically conductive lines. The sacrificial material may be removed. Subsequently, electrically insulative material may be deposited over and between the lines. The deposition of the insulative material may occur under conditions in which bread-loafing of the insulative material creates bridges of the insulative material across gas-filled gaps between the lines. The gas-filled gaps may be considered to correspond to low k dielectric regions between the electrically conductive lines. In some embodiments the sacrificial material may be carbon. In some embodiments, the deposited insulative material may be a low k dielectric material, and in other embodiments the deposited insulative material may not be a low k dielectric material.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: November 13, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Alex J. Schrinsky
  • Publication number: 20120276743
    Abstract: A method of forming a carbon type hard mask layer using induced coupled plasma includes loading a substrate onto a lower electrode in a process chamber of an induced coupled plasma (ICP) deposition apparatus, the process chamber including an upper electrode and the lower electrode therein, generating a plasma in the process chamber, injecting a reactive gas into the process chamber such that the reactive gas is activated by colliding with the plasma, the reactive gas including a hydrocarbon compound gas, and applying a bias power to the lower electrode to form a diamond-like carbon layer on the substrate from the activated reactive gas.
    Type: Application
    Filed: April 26, 2012
    Publication date: November 1, 2012
    Inventors: Jai-Hyung Won, Se-Jun Park
  • Patent number: 8299565
    Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lidija Sekaric, Tymon Barwicz, Dureseti Chidambarrao
  • Patent number: 8264046
    Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: September 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 8217513
    Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: July 10, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: George Andrew Antonelli, Jennifer O'Loughlin, Tony Xavier, Mandyam Sriram, Bart van Schravendijk, Vishwanathan Rangarajan, Seshasayee Varadarajan, Bryan L. Buckalew
  • Publication number: 20120115334
    Abstract: Embodiments of the invention describe a method for forming dielectric films for semiconductor devices. The method includes providing a substrate in a process chamber containing a microwave plasma source, introducing into the process chamber a non-metal-containing process gas including a deposition gas having a carbon-nitrogen intermolecular bond, forming a plasma from the process gas, and exposing the substrate to the plasma to deposit carbon-nitrogen-containing film on the substrate. In some embodiments, the carbon-nitrogen-containing film can include a CN film, a CNO film, a Si-doped CN film, or a Si-doped CNO film.
    Type: Application
    Filed: March 28, 2011
    Publication date: May 10, 2012
    Inventor: Hiroyuki Takaba
  • Patent number: 8084339
    Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: December 27, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: George Andrew Antonelli, Jennifer O'Loughlin, Tony Xavier, Mandyam Sriram, Bart Van Schravendijk, Vishwanathan Rangarajan, Seshasayee Varadarajan, Bryan L. Buckalew
  • Patent number: 8084371
    Abstract: Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10?11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: December 27, 2011
    Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Leland Stanford Junior University
    Inventors: David Seo, Jai-kwang Shin, Sun-ae Seo
  • Patent number: 8008668
    Abstract: LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: August 30, 2011
    Inventor: Chien-Min Sung
  • Patent number: 8008669
    Abstract: In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, David V. Horak, Takeshi Nogami, Shom Ponoth
  • Publication number: 20110121409
    Abstract: Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10?11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.
    Type: Application
    Filed: September 10, 2010
    Publication date: May 26, 2011
    Inventors: David Seo, Jai-kwang Shin, Sun-ae Seo
  • Patent number: 7939367
    Abstract: The invention is a method for growing a critical adherent diamond layer on a substrate by Chemical Vapor Deposition (CVD) and the article produced by the method. The substrate can be a compound semiconductor coated with an adhesion layer. The adhesion layer is preferably a dielectric, such as silicon nitride, silicon carbide, aluminum nitride or amorphous silicon, to name some primary examples. The typical thickness of the adhesion layer is one micrometer or less. The resulting stack of layers, (e.g. substrate layer, adhesion layer and diamond layer) is structurally free of plastic deformation and the diamond layer is well adherent to the dielectric adhesion layer such that it can be processed further, such as by increasing the thickness of the diamond layer to a desired level, or by subjecting it to additional thin film fabrication process steps. In addition to preventing plastic deformation of the layer stack, the process also reduces the formation of soot during the CVD process.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: May 10, 2011
    Assignee: Crystallume Corporation
    Inventors: Firooz Nasser-Faili, Niels Christopher Engdahl
  • Patent number: 7927964
    Abstract: Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of spaced apart electrically conductive lines, and to have sacrificial material between the electrically conductive lines. The sacrificial material may be removed. Subsequently, electrically insulative material may be deposited over and between the lines. The deposition of the insulative material may occur under conditions in which bread-loafing of the insulative material creates bridges of the insulative material across gas-filled gaps between the lines. The gas-filled gaps may be considered to correspond to low k dielectric regions between the electrically conductive lines. In some embodiments the sacrificial material may be carbon. In some embodiments, the deposited insulative material may be a low k dielectric material, and in other embodiments the deposited insulative material may not be a low k dielectric material.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: April 19, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Alex J. Schrinsky
  • Patent number: 7923377
    Abstract: An amorphous carbon film forming apparatus includes a supporting electrode that is connected to ground and supports a substrate, a counter electrode that is disposed so as to face the supporting electrode and has a mixed-gas injection orifice, a chamber containing the supporting electrode and the counter electrode, and a DC pulse generator having a pulse source that applies a DC pulse voltage between the supporting electrode and the counter electrode. An amorphous carbon film is formed by supplying a mixed gas between the supporting electrode and the counter electrode such that the percentage of the acetylene gas relative to the carrier gas is 0.05% by volume or more and 10% by volume or less, and by generating plasma while a DC pulse voltage having a pulse width of 0.1 ?sec or more and 5.0 ?sec or less is applied to the counter electrode.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: April 12, 2011
    Assignee: NGK Insulators, Ltd.
    Inventors: Takao Saito, Tatsuya Terazawa
  • Patent number: 7851288
    Abstract: A stress liner for use within a semiconductor structure that includes a field effect device has a dielectric constant less than about 7 and a compressive stress greater than about 5 GPa. The stress liner may be formed of a carbon based material, preferably a tetrahedral amorphous carbon (ta-C) material including at least about 60 atomic percent carbon and no greater than C about 40 atomic percent hydrogen. The carbon based material may be either a dielectric material, or given appropriate additional dielectric isolation structures, a semiconductor material. In particular, a ta-C stress liner may be formed using a filtered cathodic vacuum arc (FCVA) physical vapor deposition (PVD) method.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: December 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Son Nguyen, Katherine L. Saenger
  • Patent number: 7842622
    Abstract: A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer on the irregular surface of the semiconductor substrate by plasma CVD; and controlling the deposition of the conformal ratio of the depositing conformal amorphous hydrogenated carbon layer. The controlling includes (a) adjusting a step coverage of the conformal amorphous hydrogenated carbon layer to about 30% or higher as a function of substrate temperature, and (b) adjusting a conformal ratio of the conformal amorphous hydrogenated carbon layer to about 0.9 to about 1.1 as a function of RF power and/or argon gas flow rate.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: November 30, 2010
    Assignee: ASM Japan K.K.
    Inventors: Woo-Jin Lee, Atsuki Fukazawa
  • Patent number: 7842537
    Abstract: A stressed semiconductor using carbon is provided. At least one carbon layer containing diamond is formed either below a semiconductor layer or above a semiconductor device. The carbon layer induces stress in the semiconductor layer, thereby increasing carrier mobility in the device channel region. The carbon layer may be selectively formed or patterned to localize the induced stress.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Kramadhati V. Ravi, Brian S. Doyle
  • Patent number: 7811906
    Abstract: An in-place bonding method in which a metal template layer under a carbon layer is removed while the carbon layer is still attached to a substrate is described for forming a carbon-on-insulator substrate. In one embodiment of the in-place bonding method, at least one layered metal/carbon (M/C) region is formed on an insulating surface layer of an initial substrate structure. The at least one layered M/C region has edges that are bordered by exposed regions of the insulating surface layer. Some edges of the at least one layered M/C region are then secured to a base substrate of the initial structure via a securing structure, while other edges are left exposed. A selective metal etchant removes the metal layer under the carbon layer using the exposed edges for access. After metal etching, the now-unsupported carbon layer bonds to the underlying insulating surface layer by attraction.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: October 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ageeth A. Bol, Jack O. Chu, Alfred Grill, Conal E. Murray, Katherine L. Saenger
  • Patent number: 7799600
    Abstract: LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: September 21, 2010
    Inventor: Chien-Min Sung
  • Patent number: 7790630
    Abstract: A silicone-doped carbon interlayer dielectric (ILD) and its method of formation are disclosed. The ILD's dielectric constant and/or its mechanical strength can be tailored by varying the ratio of carbon-to-silicon in the silicon-doped carbon matrix.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, George A. Antonelli
  • Patent number: 7781267
    Abstract: A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotube and a top side of the first electrically conductive member. A second insulating layer is formed over the electrically conductive nanotube. A second gap exists between a top side of the electrically conductive nanotube and a first portion of the second insulating layer. A first via opening and a second via opening each extend through the second insulating layer and into the second gap.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Peter Gambino, Son Van Nguyen
  • Patent number: 7781256
    Abstract: Semiconductor devices and methods for making such devices are provided. One such method may include forming an epitaxial layer of single crystal SiC on a single crystal Si growth substrate, forming an epitaxial diamond layer on the layer of SiC, forming a Si layer on the diamond layer, bonding a SiO2 surface of a Si carrier substrate to the Si layer, and removing the Si growth substrate to expose the SiC layer. In yet another aspect, a semiconductor layer may be deposited onto the SiC layer. The semiconductor layer may further be deposited epitaxially.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: August 24, 2010
    Inventor: Chien-Min Sung
  • Patent number: 7737049
    Abstract: In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: June 15, 2010
    Assignee: Qimonda AG
    Inventors: Dirk Manger, Stephan Wege, Rolf Weis, Christoph Noelscher
  • Patent number: 7718081
    Abstract: A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: May 18, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Wei Liu, Jim Zhongyi He, Sang H. Ahn, Meihua Shen, Hichem M'Saad, Wendy H. Yeh, Christopher D. Bencher
  • Patent number: 7718544
    Abstract: A method for fabricating a semiconductor device includes: forming on a substrate a silicon-containing insulation film having a diffusion coefficient of about 250 ?m2/min or less as measured using isopropyl alcohol, by plasma reaction using a reaction gas comprising (i) a source gas comprising a silicon-containing hydrocarbon compound containing plural cross-linkable groups, (ii) a cross-linking gas, (iii) an inert gas, and optionally (iv) an oxygen-supplying gas, wherein a flow rate of the oxygen-supplying gas is no more than 25% of that of the source gas; and subjecting the insulation film to an integration process to fabricate a semiconductor device.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: May 18, 2010
    Assignee: ASM Japan K.K.
    Inventors: Naoto Tsuji, Kiyohiro Matsushita, Satoshi Takahashi, Nathan Kameling
  • Patent number: 7696106
    Abstract: A film formation method for a semiconductor process includes placing a plurality of target objects at intervals in a vertical direction inside a process container of a film formation apparatus. Then, the method includes setting the process container to have a first vacuum state therein, and supplying a first film formation gas containing a hydrocarbon gas into the process container, thereby forming a carbon film by CVD on the target objects. Then, the method includes setting the process container to have a second vacuum state therein, while maintaining the process container to have a vacuum state therein from the first vacuum state, and supplying a second film formation gas containing an organic silicon source gas into the process container, thereby forming an Si-containing inorganic film by CVD on the carbon film.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: April 13, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Okada, Kazumi Kubo
  • Publication number: 20100085713
    Abstract: A device and associated method of heat removal from electronic optoelectronic and photonic devices via incorporation of extremely high thermally conducting channels or embedded layers made of single-layer graphene (SLG), bi-layer graphene (BLG), or few-layer graphene (FLG).
    Type: Application
    Filed: April 3, 2009
    Publication date: April 8, 2010
    Inventors: Alexander A. Balandin, Dmitri Kotchetkov, Suchismita Ghosh
  • Patent number: 7682991
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a trench for a MOS gate in an SiC substrate by dry etching. Thereafter, the substrate with the trench is heat treated. The heat treatment includes heating the substrate in an Ar gas atmosphere or in a mixed gas atmosphere containing SiH4 and Ar at a temperature between 1600° C. and 1800° C., and thereafter in a hydrogen gas atmosphere at a temperature between 1400° C. and 1500° C. The present manufacturing method smoothens the trench inner surface and rounds the corners in the trench to prevent the electric field from localizing thereto.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: March 23, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Yasuyuki Kawada, Takeshi Tawara, Tae Tawara
  • Publication number: 20100032838
    Abstract: Provided is an amorphous carbon film having a high elastic modulus and a low thermal contraction rate with a suppressed low dielectric constant, a semiconductor device including the amorphous carbon film and a technology for forming the amorphous carbon film. Since the amorphous carbon film is formed by controlling an additive amount of Si (silicon) during film formation, it is possible to form the amorphous carbon film having a high elastic modulus and a low thermal contraction rate with a suppressed dielectric constant as low as 3.3 or less. Accordingly, when the amorphous carbon film is used as a film in the semiconductor device, troubles such as a film peeling can be suppressed.
    Type: Application
    Filed: November 30, 2007
    Publication date: February 11, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yoshiyuki Kikuchi, Yasuo Kobayashi, Kohei Kawamura, Toshihisa Nozawa, Hiraku Ishikawa
  • Patent number: 7648922
    Abstract: The major objective is to provide a fluorocarbon film wherein fine voids are formed by a step (SA1) for introducing a mixed gas containing a first carbon fluoride gas and a second carbon fluoride gas on a substrate placed inside a chamber, and depositing a fluorocarbon film on the substrate; and a step (SA2) for forming voids in the fluorocarbon film by selectively removing volatile components contained in the fluorocarbon film are included and especially in the step (SA2) for forming voids, it is preferable to include a step for cleaning the fluorocarbon film with a supercritical fluid.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: January 19, 2010
    Assignees: Kyoto University, Zeon Corporation
    Inventors: Tatsuru Shirafuji, Kunihide Tachibana
  • Patent number: 7642189
    Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: January 5, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 7638441
    Abstract: A method forms a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (C?H?X?, wherein ? and ? are natural numbers of 5 or more; ? is an integer including zero; X is O, N or F) having a boiling point of about 20° C. to about 350° C.; introducing the vaporized gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas. The liquid monomer is unsaturated and has no benzene structure.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: December 29, 2009
    Assignee: ASM Japan K.K.
    Inventors: Yoshinori Morisada, Nobuo Matsuki, Kamal Kishore Goundar
  • Patent number: 7582499
    Abstract: A photo sensor has an insulator layer for covering a diode stack, and the insulator layer is made of photoresist to reduce a side leakage current.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: September 1, 2009
    Assignee: Prime View International Co., Ltd.
    Inventors: Henry Wang, Wei-Chou Lan, Lee-Tyng Chen
  • Patent number: 7575948
    Abstract: A method for operating a photosensitive device is provided. At first, the photosensitive device is provided, which comprising a photo sensor circuit and a photo sensor, where the photo sensor is located above and electrically coupled with the photo sensor circuit, and where the photo sensor comprises a bottom electrode; a photosensitive layer located on the bottom electrode; and a transparent electrode located on the photosensitive layer. Then, a first electrical potential is supplied to the transparent electrode, and a second electrical potential is supplied to the bottom electrode, where the first electrical potential is greater than the second electrical potential.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: August 18, 2009
    Assignee: Art Talent Industrial Limited
    Inventors: Chrong-Jung Lin, Ya-Chin King
  • Patent number: 7557378
    Abstract: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1?x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: July 7, 2009
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, William E. Hoke, Steven D. Bernstein, Ralph Korenstein
  • Patent number: 7504344
    Abstract: A method of forming a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (C?H?X?, wherein ? and ? are natural numbers of 5 or more; ? is an integer including zero; X is O, N or F) having a boiling point of about 20° C. to about 350° C. which is not substituted by a vinyl group or an acetylene group; introducing the vaporized gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: March 17, 2009
    Assignee: ASM Japan K.K.
    Inventors: Nobuo Matsuki, Yoshinori Morisada, Seijiro Umemoto, Jea Sik Lee
  • Publication number: 20090033362
    Abstract: In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 5, 2009
    Inventors: Dirk Manger, Stephan Wege, Rolf Weis, Christoph Noelscher
  • Patent number: 7470633
    Abstract: A method forms a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (C?H?X?, wherein ? and ? are natural numbers of 5 or more; ? is an integer including zero; X is O, N or F) having a boiling point of about 20° C. to about 350° C.; introducing the vaporized gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: December 30, 2008
    Assignee: ASM Japan K.K.
    Inventors: Nobuo Matsuki, Yoshinori Morisada, Seijiro Umemoto, Jea Sik Lee
  • Patent number: 7439177
    Abstract: In manufacturing a semiconductor device, a metal film is formed on a semiconductor substrate, and a high-temperature amorphous carbon film pattern for defining a wiring forming area is formed on the metal film. The metal film is etched by using the high-temperature amorphous carbon film pattern as an etching barrier to form a metal wiring. A low-temperature amorphous carbon film as an IMD is formed on the resultant structure so as to cover the metal wiring including the high-temperature amorphous carbon film pattern. The low-temperature amorphous carbon film and the high-temperature amorphous carbon film pattern are etched to form a contact hole, which has greater width in an upper portion than in a lower portion thereof. Finally, a plug metal film is formed on the low-temperature amorphous carbon film to fill the contact hole.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: October 21, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chan Bae Kim, Chai O Chung
  • Publication number: 20080246125
    Abstract: The present invention is a semiconductor device characterized by including a substrate, an insulating film consisting of a fluorine added carbon film formed on the substrate, a barrier layer consisting of a silicon nitride film and a film containing silicon, carbon, and nitride formed on the insulating film, and a hard mask layer having a film containing silicon and oxygen formed on the barrier layer, wherein the barrier layer consists of a silicon nitride film and a film containing silicon, carbon, and nitride that are laminated from the bottom in that order, and functions to prevent the fluorine in the fluorine added carbon film from moving to the hard mask layer.
    Type: Application
    Filed: June 13, 2008
    Publication date: October 9, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Yoshiyuki Kikuchi