Deposition Of Porous Oxide Or Porous Glassy Oxide Or Oxide Based Porous Glass (epo) Patents (Class 257/E21.273)
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Patent number: 7674390Abstract: A method for forming a sol gel-zeolite composite dielectric material is herein described. Zeolite particles may be dispersed in a sol creating a liquid sol-zeolite colloid. The liquid sol-zeolite colloid may be deposited on an underlying layer. The liquid sol-zeolite colloid may be formed into a wet gel-zeolite composite. All of the liquid may be extracted from the wet gel-zeolite composite to form an aerogel-zeolite composite. Then the wet gel-zeolite composite or the aerogel-zeolite composite may be calcined to freeze the structure of the composite material.Type: GrantFiled: November 17, 2003Date of Patent: March 9, 2010Assignee: Intel CorporationInventor: Hai Deng
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Patent number: 7633163Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.Type: GrantFiled: June 16, 2006Date of Patent: December 15, 2009Assignee: Applied Materials, Inc.Inventor: Robert P. Mandal
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Patent number: 7629224Abstract: Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.Type: GrantFiled: November 28, 2006Date of Patent: December 8, 2009Assignee: Novellus Systems, Inc.Inventors: Willibrordus Gerardus Maria van den Hoek, Nerissa S. Draeger, Raashina Humayun, Richard S. Hill, Jianing Sun, Gary Ray
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Patent number: 7629272Abstract: Processes for forming porous low k dielectric materials from low k dielectric films containing a porogen material include exposing the low k dielectric film to ultraviolet radiation. In one embodiment, the film is exposed to broadband ultraviolet radiation of less than 240 nm for a period of time and intensity effective to remove the porogen material. In other embodiments, the low k dielectric film is exposed to a first ultraviolet radiation pattern effective to increase a crosslinking density of the film matrix while maintaining a concentration of the porogen material substantially the same before and after exposure to the first ultraviolet radiation pattern. The low k dielectric film can be then be processed to form a metal interconnect structure therein and subsequently exposed to a second ultraviolet radiation pattern effective to remove the porogen material from the low k dielectrics film and form a porous low k dielectric film.Type: GrantFiled: June 7, 2005Date of Patent: December 8, 2009Assignee: Axcelis Technologies, Inc.Inventors: Carlo Waldfried, Qingyuan Han, Orlando Escorcia, Ivan Berry, III
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Patent number: 7615498Abstract: A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.Type: GrantFiled: January 19, 2007Date of Patent: November 10, 2009Assignee: NEC Electronics CorporationInventors: Yoichi Sasaki, Koichi Ohto, Noboru Morita, Tatsuya Usami, Hidenobu Miyamoto
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Patent number: 7598166Abstract: A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on the first and second devices and the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material; (d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material; (e) a second dielectric layer on top of the first dielectric layer; and (f) a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers. The first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer. A dielectric constant of the first dielectric material is less than that of the device cap dielectric material.Type: GrantFiled: September 8, 2006Date of Patent: October 6, 2009Assignee: International Business Machines CorporationInventors: Zhong-Xiang He, Ning Lu, Anthony Kendall Stamper
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Patent number: 7579271Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.Type: GrantFiled: May 3, 2006Date of Patent: August 25, 2009Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Ting Cheong Ang
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Patent number: 7566976Abstract: A semiconductor device has a porous low-dielectric-constant film formed on a substrate and having an opening and a fine particle film composed of a plurality of aggregately deposited fine particles each having a diameter of not less than 1 nm and not more than 2 nm and formed on a surface of the portion of the porous low-dielectric-constant film which is formed with the opening. The fine particles are filled in voids exposed at the surface of the portion of the porous low-dielectric-constant film which is formed with the opening.Type: GrantFiled: January 7, 2008Date of Patent: July 28, 2009Assignee: Panasonic CorporationInventor: Shinichi Ogawa
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Patent number: 7563727Abstract: A method for forming a high mechanical strength, low k, interlayer dielectric material with aluminosilicate precursors so that aluminum is facilely incorporated into the silicon matrix of the material, and an integrated circuit device comprising one or more high-strength, low-k interlayer dielectric layers so formed.Type: GrantFiled: November 8, 2004Date of Patent: July 21, 2009Assignee: Intel CorporationInventor: Michael D. Goodner
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Patent number: 7554200Abstract: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.Type: GrantFiled: September 1, 2004Date of Patent: June 30, 2009Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Tongbi Jiang
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Patent number: 7544536Abstract: (1) A metal oxide dispersion for a dye-sensitized solar cell, which contains metal oxide fine particles, a binder composed of a polymer compound having an action to bind to the fine particles and a solvent; (2) a method for producing a photoactive electrode for a dye-sensitized solar cell by coating a dispersion containing the above-mentioned binder and metal oxide fine particles on a sheet-shaped electrode; (3) a photoactive electrode for a dye-sensitized solar cell, obtained by the method, which electrode has metal oxide containing the above-mentioned binder and metal oxide fine particles; and (4) a dye-sensitized solar cell with the above-mentioned photoactive electrode.Type: GrantFiled: November 28, 2006Date of Patent: June 9, 2009Assignee: Showa Denko K.K.Inventors: Katsumi Murofushi, Kunio Kondo, Ryusuke Sato
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Patent number: 7531457Abstract: A method of fabricating a suspended structure. First, a substrate including a photoresist layer hardened by heat is provided. Subsequently, the hardened photoresist layer is etched so as to turn the photoresist layer into a predetermined edge profile. Thereafter, a structure layer is formed on parts of the substrate and parts of the photoresist layer. Next, a dry etching process is performed so as to remove the photoresist layer, and to turn the structure layer into a suspended structure.Type: GrantFiled: November 21, 2006Date of Patent: May 12, 2009Assignee: Touch Micro-System Technology Inc.Inventors: Yu-Fu Kang, Chen-Hsiung Yang
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Patent number: 7514347Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.Type: GrantFiled: January 26, 2006Date of Patent: April 7, 2009Assignee: United Microelectronics Corp.Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
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Patent number: 7510982Abstract: Porous dielectric layers are produced by embedding and removing nanoparticles in composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.Type: GrantFiled: June 6, 2005Date of Patent: March 31, 2009Assignee: Novellus Systems, Inc.Inventors: Nerissa S. Draeger, Gary William Gray
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Patent number: 7501353Abstract: Disclosed is a method for the formation of features in a damascene process. According to the method, vias are formed in a dielectric layer and then covered by a layer of high molecular weight polymer. The high molecular weight polymer covers the vias but does not enter the vias. A trench is then etched through the high molecular weight polymer and the dielectric layer. Any remaining high molecular weight polymer is then removed.Type: GrantFiled: December 22, 2006Date of Patent: March 10, 2009Assignee: International Business Machines CorporationInventors: Wai-Kin Li, Wu-Song Huang
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Patent number: 7491658Abstract: A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having the molecular formula R4R5R6—Si—O—Si—R7R8R9, and trisiloxane derivatives having the molecular formula R10R11R12—Si—O—Si—R13R14—O—Si—R15R16R17 where R and R1-17 may or may not be identical and are selected from H, alkyl, alkoxy, epoxy, phenyl, vinyl, allyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. In addition to the method, the present application also provides SiCOH dielectrics made from the inventive method as well as electronic structures that contain the same.Type: GrantFiled: October 13, 2004Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Son Van Nguyen, Stephen McConnell Gates, Deborah A. Neumayer, Alfred Grill
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Patent number: 7482676Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.Type: GrantFiled: July 11, 2006Date of Patent: January 27, 2009Assignee: Air Products and Chemicals, Inc.Inventors: Brian Keith Peterson, John Francis Kirner, Scott Jeffrey Weigel, James Edward MacDougall, Lisa Deis, Thomas Albert Braymer, Keith Douglas Campbell, Martin Devenney, C. Eric Ramberg, Konstantinos Chondroudis, Keith Cendak
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Patent number: 7459793Abstract: A method for forming a contact hole, a method for manufacturing a circuit board and a method for manufacturing an electro-optical device that increase the reliability of electrical coupling via a conductive part and prevent wire-breaking due to projections when forming a contact hole in an interlayer film by using a needle, and burying a conductive material in the contact hole is provided.Type: GrantFiled: July 31, 2006Date of Patent: December 2, 2008Assignee: Seiko Epson CorporationInventors: Mitsuaki Harada, Soichi Moriya
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Patent number: 7456116Abstract: A method to form a silicon oxide layer, where the method includes the step of providing a continuous flow of a silicon-containing precursor to a chamber housing a substrate, where the silicon-containing precursor is selected from TMOS, TEOS, OMTS, OMCTS, and TOMCATS. The method may also include the steps of providing a flow of an oxidizing precursor to the chamber, and causing a reaction between the silicon-containing precursor and the oxidizing precursor to form a silicon oxide layer. The method may further include varying over time a ratio of the silicon-containing precursor:oxidizing precursor flowed into the chamber to alter a rate of deposition of the silicon oxide on the substrate.Type: GrantFiled: December 20, 2004Date of Patent: November 25, 2008Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Shan Wong, Xinyun Xia, Vikash Banthia, Won B. Bang, Yen-Kun V. Wang, Zheng Yuan
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Patent number: 7456112Abstract: A method of fabricating a micro-needle array is provided. The method of fabricating a micro-needle array having a substrate having a first surface and a second surface spaced in a predetermined interval apart from the first surface, includes patterning on the first surface, thereby forming a shape of micro-needle bodies. Further, micro-passageways are formed that penetrate the first surface of the substrate from the second surface by a porous silicon process, and integrates the micro-passageways, thereby forming the bodies and channels of micro-needles.Type: GrantFiled: January 9, 2006Date of Patent: November 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Chang-seung Lee
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Publication number: 20080265381Abstract: A porous composite material useful in semiconductor device manufacturing, in which the diameter (or characteristic dimension) of the pores and the pore size distribution (PSD) is controlled in a nanoscale manner and which exhibits improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking, Cu ingress, and other critical properties is provided. The porous composite material is fabricating utilizing at least one bifunctional organic porogen as a precursor compound.Type: ApplicationFiled: June 4, 2008Publication date: October 30, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Afzali-Ardakani, Stephen M. Gates, Alfred Grill, Deborah A. Neumayer, Son Nguyen, Vishnubhai V. Patel
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Patent number: 7429789Abstract: A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like, the composition including at least two fluoropolymers and two inorganic fillers. A circuitized substrate including at least one such dielectric layer and at least one conductive layer thereon is also provided.Type: GrantFiled: March 28, 2006Date of Patent: September 30, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas
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Patent number: 7422975Abstract: A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on the first and second spacer layers, respectively, such that each of the first and second dielectric layers is separated by one of the spacer layers. The first and second dielectric layers each include a first and second dielectric component. The second dielectric component is a sacrificial dielectric material. At least a portion of the second dielectric component is removed to thereby form voids in the first and second dielectric layers. At least a portion of the sacrificial dielectric material in the first and second spacer layers is also removed to thereby form voids in the first and/or second spacer layers.Type: GrantFiled: August 18, 2005Date of Patent: September 9, 2008Assignees: Sony Corporation, Sony Electronics Inc.Inventors: Takeshi Nogami, Kensaku Ida
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Patent number: 7413998Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated using processes performed on a reactor according to the present invention.Type: GrantFiled: September 16, 2005Date of Patent: August 19, 2008Assignee: SpringWorks, LLCInventors: Hongmei Zhang, Mukundan Narasimhan, Ravi B. Mullapudi, Richard E. Demaray
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Patent number: 7411275Abstract: It is an object to provide an insulating film having a very low dielectric constant and a great mechanical strength. Moreover, it is another object to provide a semiconductor device capable of reducing both a capacity between wiring layers and a capacity between wirings also in microfabrication and an increase in integration in the semiconductor device. In order to attain the objects, there is provided an inorganic insulating film comprising a porous structure having a skeletal structure in which a vacancy is arranged periodically and a large number of small holes are included.Type: GrantFiled: June 27, 2002Date of Patent: August 12, 2008Assignee: Rohm Co., Ltd.Inventor: Yoshiaki Oku
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Patent number: 7385276Abstract: The invention is characterized by attaining a lower dielectric constant and including an inorganic dielectric film which is formed on the surface of a substrate and has a cyclic porous structure having a pore ratio of 50% or higher.Type: GrantFiled: April 7, 2006Date of Patent: June 10, 2008Assignee: Rohm Co., Ltd.Inventors: Yoshiaki Oku, Norikazu Nishiyama, Korekazu Ueyama
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Patent number: 7345351Abstract: The present invention relates to a coating composition for insulating film production, a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same, and more particularly to a coating composition for insulating film production having a low dielectric constant and that is capable of producing an insulating film with superior mechanical strength (elasticity), a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same. The coating composition of the present invention comprises an organic siloxane resin having a small molecular weight, and water, and significantly improves low dielectricity and mechanical strength of an insulating film.Type: GrantFiled: March 31, 2004Date of Patent: March 18, 2008Assignee: LG Chem, Ltd.Inventors: Myung-Sun Moon, Min-Jin Ko, Hye-Yeong Nam, Jung-Won Kang, Bum-Gyu Choi, Byung-Ro Kim, Gwi-Gwon Kang, Young-Duk Kim, Sang-Min Park
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Patent number: 7345000Abstract: A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to an alkyl silane, an alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an aryl silane, an acyl silane, a cyclo siloxane, a polysilsesquioxane (PSS), an aryl siloxane, an acyl siloxane, or a halo siloxane, or any combination thereof. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue.Type: GrantFiled: February 18, 2005Date of Patent: March 18, 2008Assignee: Tokyo Electron LimitedInventors: Robert Kevwitch, Brandon Hansen, Dorel Ioan Toma, Jianhong Zhu
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Method for preventing the formation of a void in a bottom anti-reflective coating filling a via hole
Patent number: 7335585Abstract: A method for manufacturing a semiconductor device which, on performing a via first Dual Damascene process, inhibits or prevents the formation of a void in a bottom anti-reflective coating filling a via hole. The method typically includes the steps of forming a bottom anti-reflective coating (BARC) in a via hole in an interlayer dielectric on a semiconductor substrate sufficiently to fill the via hole; disposing an acid diffusion material on the BARC; forming a cross-link layer between the BARC and the acid diffusion material; removing the remaining acid diffusion material; and etching the cross-link layer, the BARC and the interlayer dielectric to form a trench extending from an upper portion of the via hole.Type: GrantFiled: October 20, 2004Date of Patent: February 26, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Yong Jun Choi -
Patent number: 7332446Abstract: According to the invention, the thin film having the thickness controlled desirably can be easily formed using common semiconductor processes. Provided is a coating liquid for forming the porous film having an excellent dielectric property and mechanical property. Specifically, the coating liquid for forming a porous film comprises the condensation product obtained by condensation of one or more silicate compounds represented by the formula (X2O) i(SiO2)j(H2O)k and one more organosilate compounds represented by the formula (X2O)a(RSiO1.5)b(H2O)c. Thus, the porous insulating film having sufficient mechanical strength and dielectric properties for use in the semiconductor manufacturing process can be manufactured.Type: GrantFiled: March 25, 2004Date of Patent: February 19, 2008Assignees: Shin-Etsu Chemical Co., Ltd., Matsushita Electric Industrial Co., Ltd.Inventors: Tsutomu Ogihara, Fujio Yagihashi, Yoshitaka Hamada, Takeshi Asano, Motoaki Iwabuchi, Hideo Nakagawa, Masaru Sasago
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Patent number: 7294585Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.Type: GrantFiled: July 11, 2006Date of Patent: November 13, 2007Assignee: Air Products and Chemicals, Inc.Inventors: Brian Keith Peterson, John Francis Kirner, Scott Jeffrey Weigel, James Edward MacDougall, Lisa Deis, legal representative, Thomas Albert Braymer, Keith Douglas Campbell, Martin Devenney, C. Eric Ramberg, Konstantinos Chondroudis, Keith Cendak, Thomas Alan Deis, deceased
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Patent number: 7294909Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.Type: GrantFiled: April 5, 2005Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Jon A. Casey, James G. Balz, Michael Berger, Jerome Cohen, Charles Hendricks, Richard Indyk, Mark LaPlante, David C. Long, Lori A. Maiorino, Arthur G. Merryman, Glenn A. Pomerantz, Robert A. Rita, Krystyna W. Semkow, Patrick E. Spencer, Brian R. Sundlof, Richard P. Surprenant, Donald R. Wall, Thomas A. Wassick, Kathleen M. Wiley
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Patent number: 7273821Abstract: The present invention relates to a process for producing a porous layer adhering to a substrate, which comprises the steps: a. preparation of a composition comprising an organic polymer constituent and an inorganic-organic constituent and/or an inorganic constituent, b. application of this composition to a substrate and formation of a layer on the substrate, and c. removal of the inorganic-organic constituent and/or the inorganic constituent from the layer to form a porous layer adhering to the substrate.Type: GrantFiled: March 14, 2002Date of Patent: September 25, 2007Assignee: Infineon Technologies AGInventor: Recai Sezi
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Patent number: 7265062Abstract: A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution.Type: GrantFiled: August 7, 2003Date of Patent: September 4, 2007Assignees: Applied Materials, Inc., Air Products and Chemicals, Inc.Inventors: Robert P. Mandal, Alexandros T. Demos, Timothy Weidman, Michael P. Nault, Nikolaos Bekiaris, Scott Jeffrey Weigel, Lee A. Senecal, James E. Mac Dougall, Hareesh Thridandam
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Patent number: 7256146Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1?v?0.9, 0?w?0.5, 0.01?x?0.9, 0?y?0.7, 0.01?z?0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1<v<0.8, 0<w<0.8, 0.05<x<0.8, 0<y<0.3, 0.05<z<0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.Type: GrantFiled: May 13, 2005Date of Patent: August 14, 2007Assignee: International Business Machines CorporationInventors: Stephan A. Cohen, Stephen McConnell Gates, Jeffrey C. Hedrick, Elbert E. Huang, Dirk Pfeiffer
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Publication number: 20070164358Abstract: A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.Type: ApplicationFiled: January 17, 2006Publication date: July 19, 2007Applicant: International Business Machines CorporationInventors: Joel de Souza, Keith Fogel, Brian Greene, Devendra Sadana, Haining Yang
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Publication number: 20070161131Abstract: Disclosed is a method for measuring a low-k material. A surface of the low-k material is changed into oxide by an oxygen plasma used in an ashing process (e.g., to remove a photoresist film after an etching process). A thickness of the low-k material is measured using an optical measurement system, and then the low-k material is treated with plasma in an ashing process to change the surface of the low-k material into oxide. The substrate is wet-cleaned with an inorganic or organic cleaning solution after the ashing process to remove the surface oxide. Then, a subsequent thickness of the low-k material is measured using the optical measurement system, and a thickness of the oxide is calculated by comparing the measured values. The thickness of a damaged low-k material is thereby measured in an easy and rapid manner since optical measurement system typically installed in the semiconductor fabrication facility (fab) is utilized.Type: ApplicationFiled: December 26, 2006Publication date: July 12, 2007Inventor: Cheon Shim
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Patent number: 7241691Abstract: Methods for fabricating high work function p-MOS device metal electrodes are provided. In one embodiment, a method is provided for producing a metal electrode including the steps of: providing a high k dielectric stack with an exposed surface; contacting the exposed surface of the high k dielectric stack with a vapor of a metal oxide wherein the metal oxide is selected from the group consisting of RuOx, IrOx, ReOx, MoOx, WOx, VOx, and PdOx; and contacting the exposed surface of the dielectric stack with a vapor of an additive selected from the group consisting of SiO2, Al2O3, HfO2, ZrO2, MgO, SrO, BaO, Y2O3, La2O3, and TiO2, whereby contacting the exposed surface of the dielectric stack with the vapor of the metal oxide and the vapor of the additive forms an electrode and wherein the additive is present at an amount between about 1% to about 50% by atomic weight percent in the electrode.Type: GrantFiled: March 28, 2005Date of Patent: July 10, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Yong Liang, Clarence J. Tracy
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Patent number: 7239018Abstract: Provided is a composition formed by hydrolysis and condensation composition of the alkoxysilane, the composition comprising a reduced amount of metallic and halogen impurities and being applicable as electronic material. Also provided is an insulating film having low dielectric constant produced by applying the composition and sintering it. More specifically, a method for manufacturing a composition for forming a film, comprising a step of hydrolysis and condensation of alkoxysilane or a partial hydrolysis product of the alkoxysilane in an organic solvent in the presence of trialkylmethylammonium hydroxide as catalyst, wherein the alkoxysilane is selected from the groups consisting of compounds represented by formulae (1) to (4) below, and the trialkylmethylammonium hydroxide is represented by formula (5) below.Type: GrantFiled: March 9, 2004Date of Patent: July 3, 2007Assignees: Shin-Etsu Chemical Co., Ltd., Matsushita Electric Industrial Co., Ltd.Inventors: Yoshitaka Hamada, Fujio Yagihashi, Hideo Nakagawa, Masaru Sasago
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Patent number: 7229933Abstract: A mounting substrate includes an imprinted structure on one side for containing electrical bumps. The imprinted structure is imprinted and also cured under conditions that allow retention of significant features of the cured polymer film. A chip package is also made of the imprinted structure. A computing system is also disclosed that includes the imprinted structure.Type: GrantFiled: March 31, 2004Date of Patent: June 12, 2007Assignee: Intel CorporationInventor: Paul A. Koning
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Patent number: 7223705Abstract: A method of modifying the porosity of a thickness of a layer of porous dielectric material having a surface and formed on a semiconductor substrate is provided by exposing the porous dielectric material to a sufficient temperature in the presence of a first gas to drive moisture particles out of the pores. Modifying also includes, exposing the porous dielectric material to a radio frequency stimulus of sufficient power in the presence of a second gas to densify a thickness of the porous dielectric material to reduce or prohibit subsequent absorption of moisture or reactant gas particles by the thickness or porous dielectric material.Type: GrantFiled: May 6, 2003Date of Patent: May 29, 2007Assignee: Intel CorporationInventors: Mandyam A. Sriram, Jennifer O'Loughlin
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Patent number: 7220684Abstract: There is included an inorganic insulating film having a porous structure including a cylindrical vacancy oriented in parallel with the surface of a substrate subjected to a hydrophilic treatment or a hydrophobic treatment.Type: GrantFiled: June 28, 2002Date of Patent: May 22, 2007Assignee: ROHM Co., Ltd.Inventors: Norikazu Nishiyama, Korekazu Ueyama, Yoshiaki Oku
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Patent number: 7208389Abstract: Methods of preparing a porous low-k dielectric material on a substrate are provided. The methods involve the use of ultraviolet radiation to react with and remove porogen from a porogen containing precursor film, leaving a porous low-k dielectric matrix. Methods using oxidative conditions and non-oxidative conditions are described. The methods described may be used to remove porogen from porogen-containing precursor films. The porogen may be a hydrocarbon such as a terpene (e.g., alpha-terpinene) or a norbornene (e.g., ENB). The resulting porous low-k dielectric matrix can then be annealed to remove water and remaining silanols capped to protect it from degradation by ambient conditions, which methods will also be described.Type: GrantFiled: September 26, 2003Date of Patent: April 24, 2007Assignee: Novellus Systems, Inc.Inventors: Adrianne K. Tipton, Brian G. Lu, Patrick A. Van Cleemput, Michelle T. Schulberg, Qingguo Wu, Haiying Fu, Feng Wang
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Patent number: 7176144Abstract: Methods of preparing a low-k dielectric material on a substrate are provided. The methods involve using plasma techniques to remove porogen from a precursor layer comprising porogen and a dielectric matrix and to protect the dielectric matrix with a silanol capping agent, resulting in a low-k dielectric matrix. Porogen removal and silanol capping can occur concurrently or sequentially. If performed sequentially, silanol capping is performed without first exposing the dielectric matrix to moisture or ambient conditions.Type: GrantFiled: February 23, 2004Date of Patent: February 13, 2007Assignee: Novellus Systems, Inc.Inventors: Feng Wang, Michelle T. Schulberg, Jianing Sun, Raashina Humayun, Patrick A. Van Cleemput
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Patent number: 7169716Abstract: A photosensitive resist (100) for coating on a semiconductor substrate or a mask comprises a photo acid generator (D), a solvent (E) and at least two different base polymers, of which a first base polymer comprises cycloaliphatic parent structures (A) which substantially absorb incident light at 248 nm and are substantially transparent to incident light at 193 nm, and a second base polymer comprises aromatic parent structures (B) which substantially absorb incident light at 193 nm and are substantially transparent to incident light at 248 nm. If such a resist (100) is applied in a coat thickness of from 50 to 400 nm to a substrate and the proportion of the second base polymer having the aromatic parent structure is between 1 and 25 mol %, a relatively high structure contrast, better stability to etching and a reduction of defects are advantageously achieved in an exposure at a wavelength of 193 nm. Exposure over the entire depth range of the resist (100) is ensured thereby.Type: GrantFiled: November 29, 2004Date of Patent: January 30, 2007Assignee: Infineon Technologies AGInventors: Michael Rogalli, Lars Völkel
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Patent number: 7122880Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.Type: GrantFiled: May 20, 2003Date of Patent: October 17, 2006Assignee: Air Products and Chemicals, Inc.Inventors: Brian Keith Peterson, John Francis Kirner, Scott Jeffrey Weigel, James Edward MacDougall, Lisa Deis, Thomas Albert Braymer, Keith Douglas Campbell, Martin Devenney, C. Eric Ramberg, Konstantinos Chondroudis, Keith Cendak
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Patent number: 7075187Abstract: There is disclosed a coating material formulation for layering a plurality of electrodes to provide a substrate for the electrochemical synthesis of organic oligomers. Specifically, there is disclosed a coating layer of from about 0.5 to about 100 microns thick and is composed of a mixture of controlled porosity glass (CPG) particles having an average particle size of from about 0.25 to about 25 microns, and a thickening agent.Type: GrantFiled: November 9, 2001Date of Patent: July 11, 2006Assignee: CombiMatrix CorporationInventor: Karl Maurer
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Patent number: 6899857Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of preparing a microemulsion. The method of the present embodiment then recites applying the microemulsion to a surface above which it is desired to form a region of low dielectric constant nanoporous material. Next, the present method recites subjecting the microemulsion, which has been applied to the surface, to a thermal process such that the region of low dielectric constant nanoporous material is formed above the surface.Type: GrantFiled: November 13, 2001Date of Patent: May 31, 2005Assignee: Chartered Semiconductors Manufactured LimitedInventors: Soo Choi Pheng, Lap Chan, Wang Cui Yang, Siew Yong Kong, Alex See