Composed Of Oxide Or Glassy Oxide Or Oxide Based Glass (epo) Patents (Class 257/E21.271)
  • Patent number: 12207471
    Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 21, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hae-Min Lee, Kwang-Soo Kim, Sun-Il Shim
  • Patent number: 12080599
    Abstract: Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: September 3, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Junling Sun, Lior Huli, Andrew Metz, Angelique Raley
  • Patent number: 12057300
    Abstract: Systems and methods for cleaning a processing chamber include supplying a pre-activated cleaning gas through a collar surrounding a showerhead stem into the processing chamber to clean the processing chamber. In other embodiments, a cleaning gas is supplied to the collar, and RF power is supplied to the showerhead or to a pedestal to generate plasma in the processing chamber to clean the processing chamber. In still other embodiments, an inert gas is supplied to the collar, a pre-activated cleaning gas is supplied to the showerhead stem, and RF power is supplied to the showerhead or to the pedestal to generate plasma in the processing chamber to clean the processing chamber.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 6, 2024
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Adrien Lavoie, Pulkit Agarwal, Frank Loren Pasquale, Purushottam Kumar
  • Patent number: 12046506
    Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hsin Chan, Cai-Ling Wu, Chang-Wen Chen, Po-Hsiang Huang, Yu-Yu Chen, Kuan-Wei Huang, Jr-Hung Li, Jay Chiu, Ting-Kui Chang
  • Patent number: 11920256
    Abstract: In an embodiment method for growing a rare earth oxide crystal, a surface of a Si substrate is cleaned by carrying out treatments using chemical solutions such as a mixed sulfuric acid-hydrogen peroxide solution, hot nitric acid, or diluted hydrofluoric acid several times to remove impurities on the surface of the Si substrate. A silicon oxide layer including amorphous SiOx is formed on the Si substrate. A metal layer including a rare earth metal is formed in contact with an upper surface of the silicon oxide layer. The silicon oxide layer is reacted with the metal layer through heating to form a first crystal layer including a rare earth oxide crystal obtained by oxidizing the rare earth metal on the Si substrate.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: March 5, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tomohiro Inaba, Takehiko Tawara, Hiroo Omi
  • Patent number: 11915914
    Abstract: A film forming method includes: preparing a substrate having a surface on which a first film containing boron and a second film made of a material different from that of the first film are formed; supplying a raw material gas, which contains halogen and an element X other than halogen, to the surface of the substrate; and supplying a plasmarized reaction gas, which contains oxygen, to the surface of the substrate, wherein a third film as an oxide film of the element X is selectively formed on the second film with respect to the first film by alternately supplying the raw material gas and the plasmarized reaction gas.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: February 27, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Sena Fujita, Hiroki Murakami
  • Patent number: 11877475
    Abstract: A display panel and a method for manufacturing the same are provided. The display panel comprises a thin film transistor array substrate, a storage capacitor, and a light-emitting element, wherein the thin film transistor array substrate comprises a driving thin film transistor and a switching thin film transistor, the driving thin film transistor and the switching thin film transistor are electrically connected, the driving thin film transistor and the light-emitting element are electrically connected, and the storage capacitor comprises a conductive portion of a first active layer of the switching thin film transistor and an anode of the light-emitting element.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: January 16, 2024
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Chuanbao Luo
  • Patent number: 11869806
    Abstract: Methods for forming a semiconductor structure are described. The method includes cleaning a substrate to form a substrate surface substantially free of oxide, exposing the substrate surface to a first molybdenum precursor, and exposing the substrate surface to a reactant to selectively deposit a first molybdenum film on the substrate surface. The method may be performed in a processing chamber without breaking vacuum. The method may also include forming one or more of a cap layer and a liner and annealing the substrate. The method may also include depositing a second molybdenum film on the substrate surface.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: January 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Jacqueline S. Wrench, Yixiong Yang, Yong Yang, Srinivas Gandikota
  • Patent number: 11851758
    Abstract: Methods of manufacturing a semiconductor processing chamber showerheads may include forming a melted aluminum alloy composition, cooling the melted aluminum alloy composition at a rate of at least 103 K/sec to form solid aluminum alloy particles, and forming a core region of a showerhead from the solid aluminum alloy particles. The core region of the showerhead may include an inner core region and an outer core region that may be coupled together. The inner core region may define a plurality of apertures. The outer core region may define a channel that receives a heating element. The methods may include coating the core region with one of aluminum or aluminum oxide and joining a peripheral edge of the outer core region with an inner edge of a metallic annular liner. The metallic annular liner may have a lower thermal conductivity than the core region of the showerhead.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: December 26, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Sumit Agarwal, Katherine Woo, Shawyon Jafari, Jian Li, Chidambara A. Ramalingam
  • Patent number: 11846024
    Abstract: Disclosed herein are laser-assisted metal-organic chemical vapor deposition devices and methods of use thereof for suppressing background carbon incorporation.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: December 19, 2023
    Assignee: Ohio State Innovation Foundation
    Inventors: Hongping Zhao, Zhaoying Chen, Yuxuan Zhang
  • Patent number: 11651963
    Abstract: A method for forming features over a wafer with a carbon based deposition is provided. The carbon based deposition is pretuned, wherein the pretuning causes a non-uniform removal of some of the carbon based deposition. An oxide deposition is deposited through an atomic layer deposition process, wherein the depositing the oxide deposition causes a non-uniform removal of some of the carbon based deposition. At least one additional process is provided, wherein the at least one additional process completes formation of features over the wafer, wherein the features are more uniform than features that would be formed without pretuning.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: May 16, 2023
    Assignee: Lam Research Corporation
    Inventors: Ishtak Karim, Pulkit Agarwal, Joseph R. Abel, Purushottam Kumar, Adrien Lavoie
  • Patent number: 11575101
    Abstract: An organic light emitting diode display device includes a substrate. A first protective layer is disposed on the substrate. A conductive line is disposed on the first protective layer. A second protective layer is disposed on the conductive line. A first electrode is disposed on the second protective layer. An organic light emitting layer is disposed on the first electrode. A second electrode is disposed on the light emitting layer. The first electrode is symmetric with respect to a center of the conductive line.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 7, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Moojong Kim
  • Patent number: 10654070
    Abstract: The present application relates to a method for preparing a barrier film. The present application can provide a method for preparing a barrier film having excellent barrier characteristics and optical performances. The barrier film produced by the method of the present application can be effectively used not only for packaging materials of as foods or medicines, and the like, but also for various applications, such as members for FPDs (flat panel displays) such as LCDs (Liquid Crystal Displays) or solar cells, substrates for electronic papers or OLEDs (Organic Light Emitting Diodes), or sealing films.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 19, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Hee Wang Yang, Jang Yeon Hwang, Seong Hwan Lee
  • Patent number: 10613076
    Abstract: Optoelectronic control of solid-state nanopores and applications thereof. Nanopores are extremely sensitive single-molecule sensors. Electron beams have been used to fabricate synthetic nanopores in thin solid-state membranes with sub-nanometer resolution. Methods for controlling the translocation speed of biopolymers through solid-state nanopores and methods for unblocking clogged pores by illuminating nanopores are described.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: April 7, 2020
    Assignee: THE TRUSTEES OF BOSTON UNIVERSITY
    Inventors: Amit Meller, Nicolas Di Fiori
  • Patent number: 10424517
    Abstract: A method for manufacturing a dual work function semiconductor device includes forming a first silicon oxide layer on a substrate and forming a first hafnium-containing dielectric material layer on the first silicon oxide layer. The method further includes forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer and performing a thermal treatment to intermix the silicon oxide layer, the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layers. This results in an intermixing dielectric layer containing hafnium, aluminum, silicon, and oxygen. The method further includes forming a first metal-containing conductive layer on the intermixing dielectric layer and patterning the first metal-containing conductive layer and the intermixing dielectric layer, thereby forming a first gate stack in a first region.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: September 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Joshua Tseng, Yasutoshi Okuno, Lars-Ake Ragnarsson, Tom Schram, Stefan Kubicek, Thomas Y Hoffman, Naohisa Sengoku
  • Patent number: 10324232
    Abstract: A method is provided for production of a module, including the steps of: providing a substrate (1) having a first surface (5) in the form of a translucent carrier; providing an open casting mold (6), wherein the formation of at least one optical element (4, 4?) is provided in the casting mold (6); covering the surface (5) with a polymeric casting compound (3) in the open casting mold, while forming the optical element from the casting compound (3); and curing the casting compound in the casting mold, wherein the translucent carrier and the casting compound (3) together form an optical system (10).
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: June 18, 2019
    Assignee: Heraeus Noblelight GmbH
    Inventors: Michael Peil, Susanne Schadt, Harald Maiweg, Marcus Helmling
  • Patent number: 9941157
    Abstract: A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first layer includes a trench. The method further includes applying a first material over the first layer and filling in the trench, wherein the first material contains a matrix and a porogen that is chemically bonded with the matrix. The method further includes curing the first material to form a porous material layer. The porous material layer has a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed over the first layer. The first and second portions contain substantially the same percentage of each of Si, O, and C. The first and second portions contain substantially the same level of porosity.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9875892
    Abstract: A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wei Chang, Chih-Chien Wang, Wang-Pen Mo, Hung-Chang Hsieh
  • Patent number: 9746349
    Abstract: An opto-electronic sensor module (e.g., an optical proximity sensor module) includes a substrate, a light emitter mounted on a first surface of the substrate, the light emitter being operable to emit light at a first wavelength, and a light detector mounted on the first surface of the substrate, the light detector being operable to detect light at the first wavelength. The module includes an optics member disposed substantially parallel to the substrate, and a separation member disposed between the substrate and the optics member. The separation member may surround the light emitter and the light detector, and may include a wall portion that extends from the substrate to the optics member and that separates the light emitter and the light detector from one another.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: August 29, 2017
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventors: Hartmut Rudmann, Alexander Bietsch, Susanne Westenhöfer, Simon Gubser, Samuele Laffranchini
  • Patent number: 9685375
    Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: June 20, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Dave Pratt, Andy Perkins
  • Patent number: 9666902
    Abstract: A solid electrolyte includes a plurality of particles having lithium ionic conductivity and a matrix which is interposed among the particles so as to be in contact with each of the particles and is formed from an amorphous material containing the following (a) and (b): (a) lithium atoms; and (b) an oxide of at least one element selected from the group consisting of boron, a Group 14 element in period 3 or lower, and a Group 15 element in period 3 or lower.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: May 30, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Tomofumi Yokoyama, Tsutomu Teraoka
  • Patent number: 9564309
    Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: February 7, 2017
    Assignee: ASM IP Holding B.V.
    Inventors: Antti J. Niskanen, Shang Chen, Viljami Pore, Atsuki Fukazawa, Hideaki Fukuda, Suvi P. Haukka
  • Patent number: 9263685
    Abstract: A thin film transistor is provided. The thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, a transition layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The transition layer is sandwiched between the insulating layer and the semiconductor layer. The transition layer is a silicon-oxide cross-linked polymer layer including a plurality of Si atoms. The plurality of Si atoms is bonded with atoms of the insulating layer and atoms of the semiconductor layer.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: February 16, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Qun-Qing Li, Zhen-Dong Zhu, Shou-Shan Fan
  • Patent number: 9245740
    Abstract: Provided are a novel amino-silyl amine compound, a method for preparing the same, and a silicon-containing thin-film using the same, wherein the amino-silyl amine compound has thermal stability and high volatility and is maintained in a liquid state at room temperature and under a pressure where handling is easy to thereby form a silicon-containing thin-film having high purity and excellent physical and electrical properties by various deposition methods.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: January 26, 2016
    Assignee: DNF Co., Ltd.
    Inventors: Se Jin Jang, Sang Do Lee, Sung Gi Kim, Jong Hyun Kim, Byeong Il Yang, Jang Hyeon Seok, Sang Ick Lee, Myong Woon Kim
  • Patent number: 8901016
    Abstract: A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 2, 2014
    Assignee: ASM Japan K.K.
    Inventors: Jeongseok Ha, Hideaki Fukuda, Shintaro Kaido
  • Patent number: 8883641
    Abstract: The present invention relates to a solution and a method for activating the oxidized surface of a substrate, in particular of a semiconducting substrate, for its subsequent coating by a metal layer deposited by the electroless method. According to the invention, this composition contains: A) an activator consisting of one or more palladium complexes; B) a bifunctional organic binder consisting one or more organosilane complexes; C) a solvent system consisting one or more solvents for solubilizing the said activator and the said binder.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 11, 2014
    Assignee: Alchimer
    Inventors: Vincent Mevellec, Dominique Suhr
  • Patent number: 8865529
    Abstract: A thin-film transistor device manufacturing method and others according to the present disclosure includes: forming a plurality of gate electrodes above a substrate; forming a gate insulating layer on the plurality of gate electrodes; forming an amorphous silicon layer on the gate insulating layer; forming a buffer layer and a light absorbing layer above the amorphous silicon layer; forming a crystalline silicon layer by crystallizing the amorphous silicon layer with heat generated by heating the light absorbing layer using a red or near infrared laser beam; and forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes, and film thicknesses of the gate insulating layer, the amorphous silicon layer, the buffer layer, and the light absorbing layer satisfy predetermined expressions.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: October 21, 2014
    Assignee: Panasonic Corporation
    Inventor: Yuta Sugawara
  • Patent number: 8853850
    Abstract: A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen, Venkata Ramana Yogi Mallela
  • Patent number: 8736014
    Abstract: A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Ching-Yu Lo, Hai-Ching Chen, Tien-I Bao, Chen-Hua Yu
  • Patent number: 8728832
    Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 20, 2014
    Assignee: ASM IP Holdings B.V.
    Inventors: Petri Raisanen, Michael Givens, Mohith Verghese
  • Publication number: 20140097469
    Abstract: Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device and methods of fabrication thereof are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Inventors: Helmut Hagleitner, Zoltan Ring
  • Publication number: 20140065838
    Abstract: A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A second inorganic thin film dielectric material layer is deposited on the treated surface of the first inorganic thin film dielectric material layer using an atomic layer deposition process.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Inventors: Carolyn R. Ellinger, David H. Levy, Shelby F. Nelson
  • Publication number: 20130292807
    Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Applicant: ASM IP HOLDINGS B.V.
    Inventors: Petri Raisanen, Michael Givens, Mohith Verghese
  • Patent number: 8557716
    Abstract: A thin film can be formed on a substrate at a low temperature with a practicable film-forming rate. There is provided a semiconductor device manufacturing method for forming an oxide or nitride film on a substrate. The method comprises: exposing the substrate to a source gas; exposing the substrate to a modification gas comprising an oxidizing gas or a nitriding gas, wherein an atom has electronegativity different from that of another atom in molecules of the oxidizing gas or the nitriding gas; and exposing the substrate to a catalyst. The catalyst has acid dissociation constant pKa in a range from 5 to 7, but a pyridine is not used as the catalyst.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 15, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Norikazu Mizuno
  • Publication number: 20130196515
    Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Robert D. Clark
  • Publication number: 20130109199
    Abstract: By depositing a layer of oxidizing metal on the semiconductor surface first and then depositing a layer of the high-k oxide material over the layer of oxidizing metal by an atomic layer deposition, a high-k metal oxide is formed at the interface between the semiconductor substrate and the high-k oxide and prevents formation of the undesirable low-k semiconductor oxide layer at the semiconductor/high-k oxide interface.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 2, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Georgios VELLIANITIS
  • Publication number: 20130093029
    Abstract: A process for creating a beryllium oxide film on the surface of a semiconductor material is disclosed. The process is useful for making gate dielectric layers for metal-oxide-semiconductor (MOS) devices, particularly III-V semiconductor devices.
    Type: Application
    Filed: October 12, 2011
    Publication date: April 18, 2013
    Applicant: SEMATECH, INC.
    Inventors: Jung Hwan YUM, Gennadi Bersuker, K. Sanjay Banerjee
  • Publication number: 20130078819
    Abstract: The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning & passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.
    Type: Application
    Filed: June 20, 2012
    Publication date: March 28, 2013
    Inventors: Qingqing Sun, Runchen Fang, Wen Yang, Pengfei Wang, Wei Zhang
  • Patent number: 8405202
    Abstract: A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: March 26, 2013
    Assignee: STMicroelectronics, Inc.
    Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen, Venkata Ramana Yogi Mallela
  • Patent number: 8389421
    Abstract: When an object to be processed is transferred into a process chamber capable of keeping a vacuum and an interior of the process chamber is kept in a vacuum state, the film formation method includes performing forming a first ZrO film on the object to be processed by supplying a zirconium material and an oxidizing agent in the order listed above into the process chamber and forming a second ZrO film doped with Si on the object to be processed by supplying the zirconium material, a silicon material, and the oxidizing agent in the order listed above into the process chamber, in such a way that a number of times the forming the first ZrO film is performed and a number of times the forming the second ZrO film is performed are adjusted, respectively, to form a zirconia-based film having a predetermined film thickness while controlling a Si concentration in the film.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: March 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Katsushige Harada, Yuichiro Morozumi, Shingo Hishiya
  • Publication number: 20130023124
    Abstract: Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer.
    Type: Application
    Filed: July 20, 2011
    Publication date: January 24, 2013
    Inventors: Srinivas D. Nemani, Yifeng Zhou, Dmitry Lubomirsky, Ellie Yieh
  • Publication number: 20130017683
    Abstract: A silicon carbide substrate is prepared. By exposing the silicon carbide substrate to an atmosphere having a nitrogen dioxide concentration greater than or equal to 2 ?g/m3, an oxide film is formed on the silicon carbide substrate.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 17, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Tsubasa HONKE, Shin HARADA, Kyoko OKITA
  • Publication number: 20130012034
    Abstract: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer can be formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20130011990
    Abstract: There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishwanath Bhat, Rishikesh Krishnan, Daniel Gealy
  • Publication number: 20120319252
    Abstract: A method for manufacturing a semiconductor device includes performing a cycle a predetermined number of times to form a film on a substrate. The cycle includes feeding a first material containing a first element, to be adsorbed on a substrate surface, to a processing chamber where the substrate is accommodated; feeding a second material containing a second element, adsorbed on the substrate surface, to the processing chamber after the adsorption of the first material; feeding a third material containing a third element to the processing chamber, so that the substrate surface is modified; and removing an atmosphere in the processing chamber. A content of the second element in the film is controlled by adjusting an adsorption quantity of the first material and an adsorption quantity of the second material with respect to a saturated adsorption quantity of the first material adsorbed on the substrate surface.
    Type: Application
    Filed: January 20, 2011
    Publication date: December 20, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Hirohisa Yamazaki
  • Patent number: 8318613
    Abstract: The present invention relates to compositions, which are useful for the generation of patterned or structured SiO2-layers or of SiO2-lines during the manufacturing process of semiconductor devices, and which are suitable for the application in inkjet operations. The present invention also relates to a modified process of manufacturing semiconductor devices taking advantage of these new compositions.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: November 27, 2012
    Assignee: Merck Patent GmbH
    Inventors: Werner Stockum, Ingo Koehler, Arjan Meijer, Paul Craig Brookes, Katie Patterson, Mark James
  • Patent number: 8318584
    Abstract: The formation of a gap-filling silicon oxide layer with reduced volume fraction of voids is described. The deposition involves the formation of an oxygen-rich less-flowable liner layer before an oxygen-poor more-flowable gapfill layer. However, the liner layer is deposited within the same chamber as the gapfill layer. The liner layer and the gapfill layer may both be formed by combining a radical component with an unexcited silicon-containing precursor (i.e. not directly excited by application of plasma power). The liner layer has more oxygen content than the gapfill layer and deposits more conformally. The deposition rate of the gapfill layer may be increased by the presence of the liner layer. The gapfill layer may contain silicon, oxygen and nitrogen and be converted at elevated temperature to contain more oxygen and less nitrogen. The presence of the gapfill liner provides a source of oxygen underneath the gapfill layer to augment the gas phase oxygen introduced during the conversion.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: November 27, 2012
    Assignee: Applied Materials, Inc.
    Inventors: DongQing Li, Jingmei Liang, Nitin K. Ingle
  • Patent number: 8310053
    Abstract: A micro-device with a cavity, the micro-device including a substrate. A method of forming the micro-device includes the steps of: A) providing the substrate having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant; and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity , i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: November 13, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Publication number: 20120267603
    Abstract: Disclosed are a method for fabricating a quantum dot. The method includes the steps of (a) preparing a compound semiconductor layer including a quantum well structure formed by sequentially stacking a first barrier layer, a well layer and a second barrier layer; (b) forming a dielectric thin film pattern including a first dielectric thin film having a thermal expansion coefficient higher than a thermal expansion coefficient of the second barrier layer and a second dielectric thin film having a thermal expansion coefficient lower than the thermal expansion coefficient of the second barrier layer on the second barrier layer; and (c) heat-treating the compound semiconductor layer formed thereon with the dielectric thin film pattern to cause an intermixing between elements of the well layer and elements of the barrier layers at a region of the compound semiconductor layer under the second dielectric thin film.
    Type: Application
    Filed: December 14, 2011
    Publication date: October 25, 2012
    Applicant: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventor: Hong Seok LEE
  • Patent number: 8278165
    Abstract: Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: October 2, 2012
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Rohit Pal, Janice Monzet