Abstract: This invention pertains to slurries, methods and systems that can be used in chemical mechanical planarization (CMP) of tungsten containing semiconductor device. Using the CMP slurries with additives to counter lowering of pH by tungsten polishing byproducts and maintain pH 4 or higher, the erosion of dense metal (such as tungsten) structures can be greatly diminished.

Abstract: There are provided a polishing composition that gives, in the step of polishing a wafer, a flat polished surface having a reduced height difference between a central region and a peripheral region (laser mark region) of the wafer, and a method for producing a wafer using the polished composition. A polishing composition comprising water, silica particles, an alkaline substance, and an amphoteric surfactant of formula (1): wherein R1 is a C10-20 alkyl group, or a C1-5 alkyl group containing an amide group; R2 and R3 are each independently a C1-9 alkyl group; and X?is a C1-5 anionic organic group containing a carboxylate ion or a sulfonate ion. Silica particles in the form of an aqueous dispersion of silica particles having a mean primary particle diameter of 5 to 100 nm may be used. A method for producing a wafer, wherein in the step of polishing a wafer, polishing is performed until a height difference between a central region and a peripheral region of the wafer becomes 100 nm or less.

Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) an abrasive comprising colloidal silica, (b) a compound of formula (I), (c) a compound of formula (II), (d) hydrogen peroxide, and (e) water, wherein the polishing composition has a pH of about 1 to about 5. The invention also provides a method of chemically-mechanically polishing a substrate, especially a nickel-phosphorous substrate, by contacting the substrate with the inventive chemical-mechanical polishing composition.

Abstract: Provided is a polishing composition that can effectively improve a polishing removal rate. According to the present invention, a polishing composition for polishing a polishing target material is provided. The polishing composition contains water, an oxidant, and a polishing removal accelerator, and does not contain abrasive. At least one metal salt selected from the group consisting of an alkali metal salt and an alkaline earth metal salt is contained as the polishing removal accelerator.

Abstract: A removal composition and process for cleaning post-chemical mechanical polishing (CMP) contaminants and ceria particles from a microelectronic device having said particles and contaminants thereon. The composition achieves highly efficacious removal of the ceria particles and CMP contaminant material from the surface of the microelectronic device without compromising the low-k dielectric, silicon nitride, or tungsten-containing materials.

Abstract: Metal compound chemically anchored colloidal particles wherein the metal compound is in molecular form are disclosed. A facile and fast process to chemically anchor metal compounds uniformly onto colloidal particle surfaces via chemical bonding has been developed. Metal compounds are chemically anchored to the surface of colloidal particles via an organic linking agent. Uniformly distributed metal compounds remain in molecular form after the process. The metal compound chemically anchored colloidal particles can be used as solid catalyst in metal chemical-mechanical planarization process.

Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.

Abstract: The present invention relates to a polishing composition, and more particularly, to a chemical mechanical polishing (CMP) composition used to chemically and mechanically polish a semiconductor wafer. The polishing composition of the present invention, by comprising anion-modified silica polishing particles in which the zeta potential (?) is ??10 mV, can exhibit excellent polishing performance, and more specifically, which can achieve a high polishing rate with respect to an indium-containing polishing substrate, while improving the dispersibility of the composition and reducing residual defects on the substrate.

Abstract: A semiconductor device production method includes forming a first recess portion in a first insulating film formed on a first substrate and a first conductive layer on the front surface of the first insulating film located inside and outside the first recess portion. In the first recess portion, a first pad is formed having a width of 3 ?m or less and including the first conductive layer by performing a first polishing the first conductive layer at a first polishing rate and, after the first polishing, a second polishing the first conductive layer at a second polishing rate lower than the first polishing rate. The first pad of the first substrate and a second pad of a second substrate are joined together by annealing the first substrate and the second substrate. The selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4.

Abstract: In an embodiment, a FinFET device includes a semiconductor substrate and forming fins of a first height and a second height. A dielectric layer extends a fin of the first height to the fin of a second height. The dielectric layer is disposed on the top surface of the fin of the second height.

Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where a dummy gate structure is formed on the base, an interlayer dielectric layer is formed on the base the dummy gate structure exposes, and the interlayer dielectric layer exposes the top of the dummy gate structure; forming an isolation structure in the interlayer dielectric layer between adjacent dummy gate structures, where the isolation structure further extends into the base; after forming the isolation structure, removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; filling a gate electrode material into the gate opening, where the gate electrode material further covers the top of the interlayer dielectric layer; and performing at least one polishing treatment to remove the gate electrode material above the top of the interlayer dielectric layer and retaining the gate electrode material in the gate opening as a gate electrode layer, where the step of the

Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.

Abstract: A multilayer capacitor includes: a body including dielectric layers and internal electrodes alternately disposed therein; and external electrodes disposed on the body and connected to the internal electrodes. The internal electrodes include a first internal electrode and a second internal electrode. A thickness of the second internal electrode is less than a thickness of the first internal electrode, and an area fraction of ceramics included in the first internal electrode with respect to the first internal electrode is greater than that of ceramics included in the second internal electrode with respect to the second internal electrode.

Abstract: In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, “first” layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a second layer covering a first layer on a first region of a semiconductor substrate. The semiconductor substrate includes the first region and a second region. The first layer covers the second region and a portion of the first region. First openings are formed. The method can include removing the first layer on the second region using the second layer as a mask. The method can include forming an impurity region including an n-type impurity in the second region. The method can include removing the second layer, and growing silicon layers inside the first openings and on the second region. In addition, the method can include polishing a portion of each of the silicon layers using the first layer as a stopper.

Abstract: A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

Abstract: The present invention relates to a powder composed of spherical noble-metal particles having a particle size distribution with a d10 value of ?10.0 ?m and a d90 value of ?80.0 ?m.

Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.

Abstract: A chemical-mechanical planarization device and a method for using a chemical-mechanical planarization device in conjunction with a semiconductor substrate is provided. In accordance with some embodiments, the device includes: a pad disposed over a rotatable platen; a carrier head disposed over the pad and configured to retain a semiconductor substrate between the pad and the carrier head; a tank configured to retain a liquid containing composition; at least one tube fluidly coupled with the tank, the at least one tube comprising a photocatalyst therein; a nozzle fluidly coupled with the tank through the at least one tube and configured to supply the liquid containing composition onto the pad; and a light source configured to provide light to irradiate the photocatalyst, and the liquid containing composition passing through the at least one tube.

Abstract: A multilayer capacitor includes: a body including dielectric layers and internal electrodes alternately disposed therein; and external electrodes disposed on the body and connected to the internal electrodes, respectively. Each of the internal electrodes includes a Ni grain, ceramics distributed in the Ni grain, a first coating layer surrounding the Ni grain, and second coating layers surrounding the ceramics.

Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.

Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.

Abstract: A resistive memory, a manufacturing method thereof, and a chemical mechanical polishing process are provided. The resistive memory includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is disposed on a substrate. The variable resistance layer is disposed on the first electrode. The second electrode is disposed on the variable resistance layer. The first electrode includes a first Ti layer, a Ti oxide layer, and a conductive layer sequentially disposed on the substrate.

Abstract: A multilayer ceramic capacitor and a method of manufacturing the same are disclosed. A base part of the multilayer ceramic capacitor includes ceramic dielectric and inner electrodes formed inside the ceramic dielectric, and a terminal of each of the inner electrodes is exposed out of one of the two opposite sides of the base part, to form inner electrode terminals. First outer electrodes are formed on the two sides of the base part and the outside of the inner electrode terminals, and second outer electrodes are formed on the first outer electrodes. The first outer electrodes and the base part are formed together by sintering manner, and the second outer electrodes are formed by metal powder and resin material, thereby solving the problem that the vitreous component diffuses around, or solving the problem that plating solution permeates into the base part or the ceramic dielectric during plating process.

Abstract: A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a semiconductor device including the transistor are achieved. A semiconductor and a conductor are formed over a substrate, a sacrificial layer is formed over the conductor, and an insulator is formed to cover the sacrificial layer. After that, a top surface of the insulator is removed to expose a top surface of the sacrificial layer. The sacrificial layer and a region of the conductor overlapping with the sacrificial layer are removed, whereby a source region, a drain region, and an opening are formed. Next, a gate insulator and a gate electrode are formed in the opening.

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

Abstract: Semi-aqueous compositions useful for the selective removal of titanium nitride and/or photoresist etch residue materials relative to metal conducting, e.g., tungsten and copper, and insulating materials from a microelectronic device having same thereon. The semi-aqueous compositions contain at least one oxidant, at least one etchant, and at least one organic solvent, may contain various corrosion inhibitors to ensure selectivity.

Abstract: A planarization process is performed to a wafer. In various embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. A byproduct generated by the planarization process is collected and analyzed. Based on the analysis, one or more process controls are performed for the planarization process. In some embodiments, the process controls include but are not limited to process endpoint detection or halting the planarization process based on detecting an error associated with the planarization process.

Abstract: A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.

Abstract: In a method of processing a thin layer according to an embodiment, a substrate having a processing target layer is provided into a polishing module of a thin layer processing apparatus. A chemical mechanical polishing process using a polishing slurry is performed on the processing target layer. The substrate is cleaned using a cleaning slurry.

Abstract: Compositions for use in CMP processing and methods of CMP processing. The composition utilizes low levels of particulate material, in combination with at least one amino acid, at least one oxidizer, and water to remove a metal layer such as one containing copper to a stop layer with high selectivity.

Abstract: A multilayer ceramic capacitor and a method of manufacturing the same are disclosed. A base part of the multilayer ceramic capacitor includes ceramic dielectric and inner electrodes formed inside the ceramic dielectric, and a terminal of each of the inner electrodes is exposed out of one of the two opposite sides of the base part, to form inner electrode terminals. First outer electrodes are formed on the two sides of the base part and the outside of the inner electrode terminals, and second outer electrodes are formed on the first outer electrodes. The first outer electrodes and the base part are formed together by sintering manner, and the second outer electrodes are formed by metal powder and resin material, thereby solving the problem that the vitreous component diffuses around, or solving the problem that plating solution permeates into the base part or the ceramic dielectric during plating process.

Abstract: Semiconductor structures and methods for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a sacrificial layer over the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a trench through the sacrificial layer and the dielectric layer and forming a conductive structure in the trench. The method for manufacturing a semiconductor structure further includes removing the sacrificial layer. In addition, a top surface of the conductive feature is not level with a top surface of the dielectric layer after the sacrificial layer is removed.

Abstract: A chemical mechanical polishing (CMP) apparatus includes a processing chamber, a platen, a wafer heater and a carrier head. The platen is disposed in the processing chamber and is configured to allow a polishing pad to be disposed thereon. The wafer heater is disposed in the processing chamber and is configured to heat a wafer. The carrier head is disposed in the processing chamber and is configured to hold the heated wafer against the polishing pad.

Abstract: A sizing device in a polishing apparatus for measuring a thickness of a wafer in course of polishing by laser beam interference, includes: a light-source for irradiating the wafer in course of polishing with a laser beam, a light-receiving portion for receiving reflected light from the wafer in course of polishing irradiated with the laser beam from the light-source, a calculating part for calculating a measured value of the thickness of the wafer in course of polishing irradiated with the laser beam based on the reflected light received through the light-receiving portion. The calculating part can calculate the wafer thickness in course of polishing by calculating a measuring error value of the wafer thickness in course of polishing from resistivity of the wafer in course of polishing based on a previously determined correlation between wafer resistivity and measuring error value of wafer thickness, and by compensating the measuring error value.

Abstract: Disclosed herein is a grinding wheel including an annular wheel base and a plurality of grinding stones fixed to an outer circumferential portion of the lower end of the annular wheel base. Each of the grinding stones is made of a mixture of abrasive grains and photocatalytic particles which are held together by a binder. The abrasive grains are diamond abrasive grains, and the photocatalytic particles are titanium oxide (TiO2) particles.

Abstract: To provide an electroconductive thin film, containing: a metal oxide containing indium and tin; and gold.

Abstract: The invention provides a chemical-mechanical polishing composition including (a) an abrasive comprising alumina particles, silica particles, or a combination thereof, (b) a rate accelerator comprising a phosphonic acid, an N-heterocyclic compound, or a combination thereof, (c) a corrosion inhibitor comprising an amphoteric surfactant, a sulfonate, a phosphonate, a carboxylate, a fatty acid amino acid, an amine, an amide, or a combination thereof, (d) an oxidizing agent, and (e) an aqueous carrier. The invention also provides a method of polishing a substrate, especially a substrate comprising a cobalt layer, with the polishing composition.

Abstract: Disclosed is a polishing agent for synthetic quartz glass substrates, which is characterized by containing a colloidal solution of a colloidal silica or the like having a colloid concentration of 20-50% by mass, and a polycarboxylic acid polymer, an acidic amino acid, a phenol or a glycosaminoglycan.

Abstract: A process for the production of a carbon supported catalyst, which comprises the following steps: (a) precipitation of at least one metal oxide onto a surface of a carbon-comprising support by preparing an initial mixture, comprising the carbon-comprising support, at least one metal oxide precursor and an organic solvent, and spray-drying of the initial mixture to obtain an intermediate product, (b) loading of noble-metal-comprising particles onto the surface of the intermediate product in a liquid medium by deposition, precipitation and/or reduction of a noble-metal-comprising precursor with a reducing agent, (c) heat treatment of the catalyst precursor resulting from step (b) at a temperature higher than 400° C.

Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) abrasive particles, (b) a cobalt corrosion inhibitor, (c) a cobalt dishing control agent, wherein the cobalt dishing control agent comprises an anionic head group and a C13-C20 aliphatic tail group, (d) an oxidizing agent that oxidizes cobalt, and (e) water, wherein the polishing composition has a pH of about 3 to about 8.5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains cobalt.

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.

Abstract: The invention provides a chemical-mechanical polishing composition comprising: (a) colloidal silica particles that are surface modified with metal ions selected from Mg, Ca, Al, B, Be, and combinations thereof, and wherein the colloidal silica particles have a surface hydroxyl group density of from about 1.5 hydroxyls per nm2 to about 8 hydroxyls per nm2 of a surface area of the particles, (b) an anionic surfactant, (c) a buffering agent, and (d) water, wherein the polishing composition has a pH of about 2 to about 7, and wherein the polishing composition is substantially free of an oxidizing agent that oxidizes a metal. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains silicon nitride, silicon oxide, and/or polysilicon.

Abstract: Provided is a method of etching a copper layer. The method includes generating plasma of a processing gas within a processing container which accommodates an object to be processed that includes the copper layer and a metal mask formed on the copper layer. The metal mask contains titanium. In addition, the processing gas includes CH4 gas, oxygen gas, and a noble gas. In an exemplary embodiment, the metal mask may include a layer made of TiN.

Abstract: An integrated circuit is provided. The integrated circuit includes a continuous resistor body having first and second distal terminals, and a group of electrically-floating dummy conductors that are formed above the continuous resistor body, and between the first and second distal terminals of the continuous resistor body. Each of the group of dummy conductors is coupled to the continuous resistor body through a respective via structure. The group of dummy conductors serves to dissipate heat for the continuous resistor body. If desired, an active conductor is interposed in the dummy conductors and serves as a center-tap for the continuous resistor body. The active conductor is connected to a contact node on the substrate.

Abstract: An etchant composition is provided comprising a persulfate from 0.5 to 20 wt %; a fluoride compound from 0.01 to 2 wt %; an inorganic acid from 1 to 10 wt %; a N (nitrogen atom)-containing heterocyclic compound from 0.5 to 5 wt %; a chloride compound from 0.1 to 5 wt %; a copper salt from 0.05 to 3 wt %; an organic acid or an organic acid salt from 0.1 to 10 wt %; an electron-donating compound from at 0.1 to 5 wt %; and a solvent of the residual amount. Also provided is a method of manufacturing a display device by using the same.

Abstract: The invention provides a polishing composition comprising (a) silica, (b) one or more compounds that increases the removal rate of silicon, (c) one or more tetraalkylammonium salts, and (d) water, wherein the polishing composition has a pH of about 7 to about 11. The invention further provides a method of polishing a substrate with the polishing composition.

Abstract: This invention provides a production process in which in a process for producing a magnetoresistive effect element, noble metal atoms in a re-deposited film adhered to a side wall after element isolation are efficiently removed to prevent short-circuiting due to the re-deposited film. The noble metal atoms are selectively removed from the re-deposited film by applying an ion beam, formed using a plasma of a Kr gas or a Xe gas, to the re-deposited film formed on the side wall of the magnetoresistive effect element after the element isolation.

Abstract: The present invention relates to a CMP slurry composition for polishing copper, comprising: polishing particles; a complexing agent; a corrosion inhibitor; and deionized water. The complexing agent comprises one or more organic acids selected from oxalic acid, malic acid, malonic acid, and formic acid, and glycine.

Abstract: An adaptive feedback control method is provided for a chemical mechanical polish process to minimize a dielectric layer clearing time difference between two annular regions on a substrate. An optical system with an optical window passes below the polishing pad and detects reflected light interference signals from at least two annular regions. A pre-clearing time difference is determined and is used to calculate an adjustment to one or both of a CMP head membrane pressure and a retaining ring pressure. The pressure adjustment is applied before the end of the polish cycle to avoid the need for a second polish cycle and to reduce a dishing difference and a resistance difference in a metal layer in the at least two annular regions. In some embodiments, a second pressure adjustment is performed before the end of the cycle and different CMP head membrane pressure adjustments are made in different pressure zones.