By Chemical Mechanical Polishing (cmp) (epo) Patents (Class 257/E21.304)
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Patent number: 9567493Abstract: A method for performing a Chemical Mechanical Polishing (CMP) process includes applying a CMP slurry solution to a surface of a hardened fluid material on a substrate, the solution comprising an additive to change a bonding structure on the surface of the hardened fluid material. The method further includes polishing the surface of the hardened fluid material with a polishing head.Type: GrantFiled: April 25, 2014Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
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Patent number: 9567492Abstract: A chemical mechanical polishing (CMP) includes providing a slurry including composite particles dispersed in a water-based carrier that comprise a plurality of hard particles on an outer surface of a soft-core particle. The hard particles have a Mohs hardness at least 1 greater than a Mohs hardness of the soft core particle and/or a Vickers hardness at least 500 Kg/mm2 greater than the soft-core particle. A substrate having a substrate surface with a hardness greater than a Mohs number of 6 or a Vickers hardness greater than 1,000 kg/mm2 is placed into a CMP apparatus having a rotating polishing pad, and CMP is performed with the rotating polishing pad and the slurry to polish the substrate surface.Type: GrantFiled: August 28, 2014Date of Patent: February 14, 2017Assignees: Sinmat, Inc., University of Florida Research Foundation, Inc.Inventors: Rajiv K. Singh, Arul Chakkaravarthi Arjunan, Kannan Balasundaram, Deepika Singh, Wei Bai
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Patent number: 9558998Abstract: In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.Type: GrantFiled: March 10, 2016Date of Patent: January 31, 2017Assignee: Tessera, Inc.Inventors: Cyprian Uzoh, Vage Oganesian, Ilyas Mohammed
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Patent number: 9548250Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate, and at least one metal gate stack formed on the upper surface of the semiconductor substrate. One or more pairs of source/drain contact structures are formed on the upper surface of the semiconductor fin. Each source/drain contact structure includes a metal contact stack, a spacer, and a cap spacer. The metal contact stack is formed on the upper surface of the fin. The spacer is interposed between a contact sidewall of the metal contact stack and a gate sidewall of the at least one metal gate stack. The cap spacer is formed on an upper surface of the metal contact stack and has a cap portion disposed against the spacer such that the metal gate stack is interposed between the opposing source/drain contact structures.Type: GrantFiled: November 25, 2015Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Tenko Yamashita
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Patent number: 9525022Abstract: Various embodiments provide an MIM capacitor and fabrication method thereof. An exemplary MIM capacitor can include a dielectric layer disposed over a substrate containing a conductive layer. The dielectric layer can include a groove to expose the conductive layer in the substrate. A first metal layer can be disposed on a bottom surface and a bottom portion of a sidewall surface of the groove. A top surface of the first metal layer on the sidewall surface of the groove can be lower than a top surface of the dielectric layer. A dielectric material layer can be disposed on the first metal layer and on a top portion of the sidewall surface of the groove. A second metal layer can be disposed on the dielectric material layer; and a third metal layer can be disposed on the second metal layer to fill the groove.Type: GrantFiled: December 4, 2015Date of Patent: December 20, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Zhongshan Hong
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Patent number: 9425105Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate, and at least one metal gate stack formed on the upper surface of the semiconductor substrate. One or more pairs of source/drain contact structures are formed on the upper surface of the semiconductor fin. Each source/drain contact structure includes a metal contact stack, a spacer, and a cap spacer. The metal contact stack is formed on the upper surface of the fin. The spacer is interposed between a contact sidewall of the metal contact stack and a gate sidewall of the at least one metal gate stack. The cap spacer is formed on an upper surface of the metal contact stack and has a cap portion disposed against the spacer such that the metal gate stack is interposed between the opposing source/drain contact structures.Type: GrantFiled: September 15, 2015Date of Patent: August 23, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Tenko Yamashita
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Patent number: 9375822Abstract: A polishing pad is provided herein, which may include a plurality of soluble fibers having a diameter in the range of about 5 to 80 micrometers, and an insoluble component. The pad may also pad include a first surface having a plurality of micro-grooves, wherein the soluble fibers form the micro-grooves in the pad. The micro-grooves may have a width and/or depth up to about 150 micrometers. In addition, a method of forming the polishing pad and a method of polishing a surface with the polishing pad is disclosed.Type: GrantFiled: November 4, 2014Date of Patent: June 28, 2016Assignee: FNS TECH CO., LTD.Inventors: Oscar K. Hsu, Marc C. Jin, David Adam Wells, John Erik Aldeborgh
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Patent number: 9373581Abstract: Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.Type: GrantFiled: February 5, 2015Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng Shih, Joung-Wei Liou, Chih-Hung Sun, Chia-Cheng Chou, Kuang-Yuan Hsu
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Patent number: 9242337Abstract: A method for controlling the residue clearing process of a chemical mechanical polishing (“CMP”) process is provided. Dynamic in-situ profile control (“ISPC”) is used to control polishing before residue clearing starts, and then a new polishing recipe is dynamically calculated for the clearing process. Several different methods are disclosed for calculating the clearing recipe. First, in certain implementations when feedback at T0 or T1 methods are used, a post polishing profile and feedback offsets are generated in ISPC software. Based on the polishing profile and feedback generated from ISPC before the start of the clearing process, a flat post profile after clearing is targeted. The estimated time for the clearing step may be based on the previously processed wafers (for example, a moving average of the previous endpoint times). The calculated pressures may be scaled to a lower (or higher) baseline pressure for a more uniform clearing.Type: GrantFiled: February 20, 2014Date of Patent: January 26, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Jun Qian, Sivakumar Dhandapani, Benjamin Cherian, Thomas H. Osterheld, Charles C. Garretson
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Patent number: 9041111Abstract: A flat panel detector includes a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element includes: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor includes a first electrode and a second electrode. The first electrode includes an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode.Type: GrantFiled: December 16, 2013Date of Patent: May 26, 2015Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Zhenyu Xie
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Patent number: 9018629Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.Type: GrantFiled: October 5, 2012Date of Patent: April 28, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sachiaki Tezuka, Atsuo Isobe, Takehisa Hatano, Kazuya Hanaoka
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Patent number: 8981441Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.Type: GrantFiled: September 30, 2013Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Noma, Hiroshi Watanabe, Shinya Kobayashi
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Patent number: 8969134Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.Type: GrantFiled: May 10, 2013Date of Patent: March 3, 2015Assignee: Intel CorporationInventors: Xavier F. Brun, Takashi Kumamoto, Sufi Ahmed
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Patent number: 8951878Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.Type: GrantFiled: December 5, 2013Date of Patent: February 10, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiro Jinbo, Hironobu Shoji, Hideto Ohnuma, Shunpei Yamazaki
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Patent number: 8952452Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.Type: GrantFiled: December 3, 2012Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Seong Kang, Yoon-Hae Kim, Jong-Shik Yoon
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Patent number: 8937020Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.Type: GrantFiled: June 20, 2013Date of Patent: January 20, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Keiji Sato
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Patent number: 8921174Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.Type: GrantFiled: June 14, 2012Date of Patent: December 30, 2014Assignee: Peking UniversityInventors: Ru Huang, Qianqian Huang, Zhan Zhan, Yingxin Qiu, Yangyuan Wang
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Patent number: 8912098Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.Type: GrantFiled: April 15, 2013Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
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Patent number: 8912092Abstract: A method of forming a semiconductor device may include, but is not limited to, the following processes. A multi-layered structure is prepared over a semiconductor substrate. The multi-layered structure may include, but is not limited to, first and second patterns of a first insulating film, a second insulating film covering the first pattern of the first insulating film, and a first conductive film covering the second pattern of the first insulating film. The second insulating film and the first conductive film are polished under conditions that the first and second insulating films are greater in polishing rate than the first conductive film, to expose the first and second patterns of the first insulating film.Type: GrantFiled: October 19, 2011Date of Patent: December 16, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Kyoko Miyata
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Patent number: 8906772Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.Type: GrantFiled: May 25, 2012Date of Patent: December 9, 2014Assignee: UChicago Argonne, LLCInventor: Anirudha V. Sumant
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Patent number: 8895446Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.Type: GrantFiled: February 18, 2013Date of Patent: November 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
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Patent number: 8883020Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.Type: GrantFiled: January 30, 2013Date of Patent: November 11, 2014Assignee: Globalfoundries, Inc.Inventors: Xunyuan Zhang, Xiuyu Cai
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Patent number: 8884441Abstract: The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.Type: GrantFiled: February 18, 2013Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hung Hsueh, Wei-Te Wang, Shao-Yu Chen, Chun-Liang Fan, Kuan-Chi Tsai
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Methods of forming trench/hole type features in a layer of material of an integrated circuit product
Patent number: 8871649Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.Type: GrantFiled: March 15, 2013Date of Patent: October 28, 2014Assignees: GLOBALFOUNDRIES Inc., Renesas Electronics Corporation, International Business Machines CorporationInventors: Linus Jang, Yoshinori Matsui, Chiahsun Tseng -
Patent number: 8853757Abstract: Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: February 8, 2011Date of Patent: October 7, 2014Assignee: Intel CorporationInventor: Kevin Lee
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Patent number: 8853084Abstract: A method provides an intermediate semiconductor device structure and includes providing a wafer having first dummy gate plugs and second dummy gate plugs embedded in a first layer having a non-planar wafer surface topography due at least to a presence of the first dummy gate plugs; depositing at least one second layer over the first layer, the at least one second layer comprising a hard mask material; and removing at least a portion of the second layer to form a substantially planar wafer surface topography over the first dummy gate plugs and the second dummy gate plugs prior to gate conductor deposition.Type: GrantFiled: January 31, 2013Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventor: Effendi Leobandung
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Patent number: 8846538Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.Type: GrantFiled: July 27, 2012Date of Patent: September 30, 2014Assignee: Silicon Storage Technology, Inc.Inventors: Bomy Chen, Long Ching Wang, Sychi Fang
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Patent number: 8835247Abstract: A sensor array for detecting particles, the sensor array comprising a substrate having a plurality of holes, a plurality of electronic sensor chips each having a sensor active region being sensitive to the presence of particles to be detected, and an electric contacting structure adapted for electrically contacting the plurality of electronic sensor chips, wherein the plurality of electronic sensor chips and/or the electric contacting structure are connected to the substrate in such a manner that the plurality of holes in combination with the plurality of electronic sensor chips and/or the electric contacting structure form a plurality of wells with integrated particle sensors.Type: GrantFiled: May 11, 2009Date of Patent: September 16, 2014Assignee: NXP, B.V.Inventors: Michel De Langen, Ger Reuvers, Frans Meeuwsen
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Patent number: 8836129Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.Type: GrantFiled: March 14, 2013Date of Patent: September 16, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
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Patent number: 8815743Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.Type: GrantFiled: March 14, 2013Date of Patent: August 26, 2014Assignee: Infineon Technologies AGInventors: Albert Birner, Uwe Hoeckele, Thomas Kunstmann, Uwe Seidel
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Patent number: 8816404Abstract: A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.Type: GrantFiled: September 16, 2011Date of Patent: August 26, 2014Assignee: STATS ChipPAC, Ltd.Inventors: YoungJoon Kim, SangMi Park, YongHyuk Jeong
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Patent number: 8815694Abstract: Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region.Type: GrantFiled: December 3, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kerber
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Patent number: 8809981Abstract: A method for manufacturing a semiconductor device includes: irradiating a growth substrate with laser light to focus the laser light into a prescribed position inside a crystal for a semiconductor device or inside the growth substrate, the crystal for the semiconductor device being formed on a first major surface of the growth substrate; moving the laser light in a direction parallel to the first major surface; and peeling off a thin layer including the crystal for the semiconductor device from the growth substrate, a wavelength of the laser light being longer than an absorption end wavelength of the crystal for the semiconductor device or the growth substrate, the laser light being irradiated inside a crystal for the semiconductor device or inside the growth substrate.Type: GrantFiled: December 20, 2011Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masanobu Ando, Toru Gotoda, Toru Kita
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Patent number: 8796149Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.Type: GrantFiled: February 18, 2013Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: James W. Adkisson, David L. Harame, Qizhi Liu
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Patent number: 8790962Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.Type: GrantFiled: March 18, 2013Date of Patent: July 29, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Rui Huang, Yaojian Lin
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Patent number: 8786027Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.Type: GrantFiled: May 3, 2013Date of Patent: July 22, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
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Patent number: 8785330Abstract: A method for producing a structure including an active part with a first and a second suspended zone. The method includes machining the front face of a first substrate to define the lateral contours of at least one first suspended zone according to a first thickness less than that of the first substrate forming a stop layer of etching of the first suspended zone under the suspended zone, forming on the front face of the first substrate a sacrificial layer, machining from the rear face of the first substrate up to releasing the sacrificial layer to form at least one second suspended zone to reach the stop layer of the first suspended zone, and releasing the first and second suspended zones.Type: GrantFiled: November 21, 2012Date of Patent: July 22, 2014Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Philippe Robert, Sophie Giroud
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Patent number: 8779479Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.Type: GrantFiled: February 28, 2013Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama
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Patent number: 8779547Abstract: Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.Type: GrantFiled: December 6, 2012Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jongwon Hong, Insun Park, Hei Seung Kim, Jongmin Baek
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Patent number: 8765555Abstract: A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between.Type: GrantFiled: April 30, 2012Date of Patent: July 1, 2014Assignee: Micron Technology, Inc.Inventor: Damon E. Van Gerpen
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Patent number: 8765549Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.Type: GrantFiled: April 27, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hua Chang, Shin-Puu Jeng, Der-Chyang Yeh, Shang-Yun Hou, Wen-Chih Chiou
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Patent number: 8765608Abstract: Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.Type: GrantFiled: May 1, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ya Hui Chang
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Patent number: 8759944Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.Type: GrantFiled: May 21, 2013Date of Patent: June 24, 2014Assignee: Micron Technology, Inc.Inventors: David H. Wells, Du Li
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Patent number: 8734204Abstract: A polishing solution for metal films that comprises an oxidizing agent, a metal oxide solubilizer, a metal corrosion preventing agent, a water-soluble polymer and water, wherein the water-soluble polymer is a copolymer of acrylic acid and methacrylic acid, the copolymerization ratio of methacrylic acid in the copolymer being 1-20 mol % based on the total of acrylic acid and methacrylic acid.Type: GrantFiled: April 13, 2009Date of Patent: May 27, 2014Assignee: Hitachi Chemical Company, Ltd.Inventors: Kouji Haga, Masato Fukasawa, Hiroshi Nakagawa, Kouji Mishima
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Patent number: 8709957Abstract: A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.Type: GrantFiled: May 25, 2012Date of Patent: April 29, 2014Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Ibrahim Alhomoudi
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Patent number: 8709915Abstract: A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.Type: GrantFiled: July 23, 2012Date of Patent: April 29, 2014Inventor: Takeo Tsukamoto
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Patent number: 8697507Abstract: Provided are a transistor of a semiconductor device and a method of fabricating the same.Type: GrantFiled: January 11, 2011Date of Patent: April 15, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Jae Kyoung Mun, Hong Gu Ji, Ho Kyun Ahn, Hae Cheon Kim
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Patent number: 8698209Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.Type: GrantFiled: October 27, 2011Date of Patent: April 15, 2014Assignee: Micron Technology, Inc.Inventor: Jun Liu
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Patent number: 8679979Abstract: A method of controlling the polishing of a substrate includes polishing a substrate on a first platen using a first set of parameters, obtaining first and second sequences of measured spectra from first and second regions of the substrate with an in-situ optical monitoring system, generating first and second sequences of values from the first and second sequences of measured spectra, fitting first and second linear functions to the first and second sequences of values, determining a difference between the first linear function and the second linear function, adjusting at least one parameter of a second set of parameters based on the difference, and polishing the substrate on a second platen using the adjusted parameter.Type: GrantFiled: October 12, 2011Date of Patent: March 25, 2014Assignee: Applied Materials, Inc.Inventors: Jeffrey Drue David, Harry Q. Lee, Boguslaw A. Swedek, Dominic J. Benvegnu, Zhize Zhu, Wen-Chiang Tu
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Patent number: 8658538Abstract: A method of fabricating a memory device includes forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks.Type: GrantFiled: March 7, 2013Date of Patent: February 25, 2014Assignee: Nanya Technology CorporationInventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai