Doping Layer (epo) Patents (Class 257/E21.315)
  • Patent number: 8790969
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 29, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondo, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8633105
    Abstract: A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: January 21, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Calvin Li, Christopher Petti
  • Patent number: 8513719
    Abstract: A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 20, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Sujit Banerjee, Martin H. Manley
  • Patent number: 8481378
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: July 9, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V.
    Inventors: Alexandre Mondot, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8389399
    Abstract: A method of forming a memory cell is provided, the method including forming a first pillar-shaped element comprising a first semiconductor material, forming a first mold comprising an opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: March 5, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Calvin Li, Christopher Petti
  • Patent number: 8329532
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Herbert Schaefer, Martin Franosch, Thomas Meister, Josef Boeck
  • Publication number: 20120270393
    Abstract: In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 25, 2012
    Applicant: ASM INTERNATIONAL N.V.
    Inventors: Viljami J. Pore, Suvi P. Haukka, Tom E. Blomberg, Eva E. Tois
  • Patent number: 8164125
    Abstract: A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: April 24, 2012
    Assignee: Power Integrations, Inc.
    Inventors: Sujit Banerjee, Martin H. Manley
  • Patent number: 8102052
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: January 24, 2012
    Assignee: Infineon Technologies AG
    Inventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
  • Patent number: 8080452
    Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 20, 2011
    Assignees: NXP, B.V., STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondot, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 7947552
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: May 24, 2011
    Assignee: Infineon Technologies AG
    Inventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
  • Patent number: 7939437
    Abstract: A method for the production of a contact structure of a solar cell allows p-contacts and n-contacts to be produced simultaneously.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: May 10, 2011
    Assignee: Deutsche Cell GmbH
    Inventors: Andreas Krause, Bernd Bitnar, Holger Neuhaus
  • Patent number: 7807577
    Abstract: After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: October 5, 2010
    Assignee: ProMOS Technologies Pte. Ltd.
    Inventors: Zhong Dong, Ching-Hwa Chen
  • Patent number: 7727867
    Abstract: A MLD-SIMOX wafer is obtained by forming a first ion-implanted layer in a silicon wafer; forming a second ion-implanted layer that is in an amorphous state; and subjecting the wafer to a high-temperature heat treatment to maintain the wafer in an atmosphere containing oxygen at a temperature that is not lower than 1300° C. but lower than a silicon melting point to change the first and the second ion-implanted layers into a BOX layer, wherein the dose amount for the first ion-implanted layer is 1.25 to 1.5×1017 atoms/cm2, the dose amount for the second ion-implanted layer is 1.0×1014 to 1×1016 atoms/cm2, the wafer is preheated to a temperature of 50° C. to 200° C. before forming the second ion-implanted layer, and the second ion-implanted layer is formed in a state where it is continuously heated to a preheating temperature.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: June 1, 2010
    Assignee: Sumco Corporation
    Inventors: Yoshiro Aoki, Bong-Gyun Ko
  • Patent number: 7629247
    Abstract: A method of forming a three-dimensional, non-volatile memory array utilizing damascene fabrication techniques is disclosed. A bottom set of conductors is formed and a set of first pillar shaped elements of heavily doped semiconductor material as formed thereon. A mold is formed of insulating material having pillar shaped openings self-aligned with the first pillar shaped elements and a second semiconductor is deposited over the mold to form second pillar shaped elements aligned with the first pillar shaped elements. The pillar elements formed may be further processed by forming another mold of insulating material having trench openings aligned with the pillar shaped elements and then filling the trenches with conductive material to form conductors coupled to the pillar shaped elements.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: December 8, 2009
    Assignee: Sandisk 3D LLC
    Inventors: Kang-Jay Hsia, Calvin Li, Christopher Petti
  • Patent number: 7569449
    Abstract: Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described. Elements of lower-threshold voltage NMOS devices are formed at first locations on a substrate. Elements of higher-threshold voltage PMOS devices are formed at second locations on the substrate. Elements of higher-threshold voltage NMOS devices and elements of lower-threshold PMOS devices are formed by adding a same amount of p-type dopant at selected locations chosen from the first and second locations.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: August 4, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Adrian B. Early
  • Patent number: 7553763
    Abstract: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: June 30, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Chin-Cheng Chien, Kuo-Tai Huang
  • Patent number: 7348229
    Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type, which both are provided with extensions (2A,3A) and with a channel region (4) of a second conductivity type, opposite to the first conductivity type, between the source region (2) and the drain region (3) and with a gate region (5) separated from the surface of the semiconductor body (1) by a gate dielectric (6) above the channel region (4), and wherein a pocket region (7) of the second conductivity type and with a doping concentration higher than the doping concentration of the channel region (4) is formed below the extensions (2A,3A), and wherein the pocket region (7) is formed by implanting heavy ions in the semiconductor body (1), after which implantation a first annealing process is done at a moderate temperature and a second annealing
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: March 25, 2008
    Assignee: NXP B.V.
    Inventors: Bartlomiej Jan Pawlak, Raymond James Duffy