Doping Polycrystalline Or Amorphous Silicon Layer (epo) Patents (Class 257/E21.316)
  • Patent number: 10163739
    Abstract: A solid-state imaging device includes a substrate having a rectangular shape; a first region configured to extend on the substrate in a length direction of the substrate, and to include a plurality of electrode pads arranged above the substrate through a multilayer interconnection; and a second region configured to extend in the length direction, and to include an imaging element, an optical filter, and an insulating film. The second region extends on the substrate on which the imaging element is arranged. The optical filter is arranged above the substrate and faces the imaging element through the insulating film. The second region extends in parallel to the first region to be apart from the first region by a given distance. The plurality of electrode pads are arranged to be apart from each other by a given space, equal to or smaller than the given distance, in the length direction.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Ricoh Company, Ltd.
    Inventors: Isamu Miyanishi, Tohru Kanno
  • Patent number: 8993415
    Abstract: In a method, a gate dielectric film is formed on a semiconductor substrate. A gate electrode is formed on the gate dielectric film. Impurities of a first conduction-type are introduced into a drain-layer formation region. The impurities of the first conduction-type in the drain-layer formation region are activated by performing heat treatment. Single crystals of the semiconductor substrate in a source-layer formation region are amorphized by introducing inert impurities into the source-layer formation region. Impurities of a second conduction-type is introduced into the source-layer formation region. At least an amorphous semiconductor in the source-layer formation region is brought into a single crystal semiconductor and the impurities of the second conduction-type in the source-layer formation region is activated by irradiating the semiconductor substrate with microwaves.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Miyano, Toshitaka Miyata
  • Patent number: 8723340
    Abstract: The present invention relates to a process for the production of solar cells comprising a selective emitter using an improved etching-paste composition which has significantly improved selectivity for silicon layers.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 13, 2014
    Assignee: Merck Patent GmbH
    Inventors: Werner Stockum, Oliver Doll, Ingo Koehler
  • Patent number: 8367486
    Abstract: It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichiro Sakata
  • Patent number: 8314428
    Abstract: A thin film transistor including a lightly doped drain (LDD) region or offset region, wherein the thin film transistor is formed so that primary crystal grain boundaries of a polysilicon substrate are not positioned in the LDD or offset region.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: November 20, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Yong Park, Ki Yong Lee, Hye Hyang Park
  • Patent number: 8252668
    Abstract: Provided is a photoelectric conversion device fabrication method that realizes both high productivity and high conversion efficiency by rapidly forming an n-layer having good coverage. The fabrication method for a photoelectric conversion device includes a step of forming a silicon photoelectric conversion layer on a substrate by a plasma CVD method. In the fabrication method for the photoelectric conversion device, the step of forming the photoelectric conversion layer includes a step of forming an i-layer formed of crystalline silicon and a step of forming, on the i-layer, an n-layer under a condition with a hydrogen dilution ratio of 0 to 10, inclusive.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: August 28, 2012
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Kengo Yamaguchi, Satoshi Sakai, Yoshiaki Takeuchi
  • Patent number: 8088676
    Abstract: Crystallization-inducing metal elements are introduced onto an amorphous silicon thin film. A first, low-temperature, heat-treatment induces nucleation of metal-induced crystallization (MIC), resulting in the formation of small polycrystalline silicon “islands”. A metal-gettering layer is formed on the resulting partially crystallized thin film. A second, low-temperature, heat-treatment completes the MIC process, whilst gettering metal elements from the partially crystallized thin film. The process results in the desired polycrystalline silicon thin film.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: January 3, 2012
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Man Wong, Hoi-Sing Kwok, Zhiguo Meng, Dongli Zhang, Xuejie Shi
  • Patent number: 8062921
    Abstract: A phase change memory may be made with improved speed and stable characteristics over extended cycling. The alloy may be selected by looking at alloys that become stuck in either the set or the reset state and finding a median or intermediate composition that achieves better cycling performance. Such alloys may also experience faster programming and may have set and reset programming speeds that are substantially similar.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: November 22, 2011
    Assignee: Intel Corporation
    Inventors: Guy C. Wicker, Carl Schell, Sergey A. Kostylev, Stephen J. Hudgens
  • Patent number: 8030146
    Abstract: An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilicon layer to form a polysilicon channel layer.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: October 4, 2011
    Assignee: Au Optronics Corp.
    Inventors: Jiunn-Yi Lin, Ming-Yan Chen
  • Patent number: 7985678
    Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 26, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiraku Chakihara, Mitsuhiro Noguchi, Masahiro Tadokoro, Naonori Wada, Akio Nishida
  • Patent number: 7964479
    Abstract: The present invention provides a method for forming a layer (6) of polycrystalline semiconductor material on a substrate (1). The method comprises providing at least one catalyst particle (4) on a substrate (1), the at least one catalyst particle (4) comprising at least a catalyst material, the catalyst material having a melt temperature of between room temperature and 500° C., or being able to form a catalyst material/semiconductor material alloy with a eutectic temperature of between room temperature and 500° C., and forming a layer (6) of polycrystalline semiconductor material on the substrate (1) at temperatures lower than 500° C. by using plasma enhancement of a precursor gas, thereby using the at least one catalyst particle (4) as an initiator. The present invention furthermore provides a layer (6) of polycrystalline semiconductor material obtained by the method according to embodiments of the present invention.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: June 21, 2011
    Assignee: IMEC
    Inventors: Francesca Iacopi, Philippe M. Vereecken
  • Patent number: 7935591
    Abstract: Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: May 3, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Choon Hwan Kim, Il Cheol Rho
  • Patent number: 7927957
    Abstract: A bonded silicon wafer is produced by a method including an oxygen ion implantation step on a silicon wafer for active layer having the specified wafer face; a step of bonding the silicon wafer for active layer to a silicon wafer for support; a first heat treatment step; an inner SiO2 layer exposing step; a step of removing the inner SiO2 layer; and a planarizing step of polishing a silicon wafer composite or subjecting the silicon wafer composite to a heat treatment in a reducing atmosphere (a second heat treatment step).
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: April 19, 2011
    Assignee: SUMCO Corporation
    Inventors: Tatsumi Kusaba, Akihiko Endo, Hideki Nishihata, Nobuyuki Morimoto
  • Patent number: 7927986
    Abstract: A method of plasma doping includes providing a dopant gas comprising a dopant heavy halogenide compound gas to a plasma chamber. A plasma is formed in the plasma chamber with the dopant heavy halogenide compound gas and generates desired dopant ions and heavy fragments of precursor dopant molecule. A substrate in the plasma chamber is biased so that the desired dopant ions impact the substrate with a desired ion energy, thereby implanting the desired dopant ions and the heavy fragments of precursor dopant molecule into the substrate, wherein at least one of the ion energy and composition of the dopant heavy halogenide compound is chosen so that the implant profile in the substrate is substantially determined by the desired dopant ions.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: April 19, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, George D. Papasouliotis, Edwin Arevalo
  • Patent number: 7923357
    Abstract: A poly-silicon film formation method for forming a poly-silicon film doped with phosphorous or boron includes heating a target substrate placed in a vacuum atmosphere inside a reaction container, and supplying into the reaction container a silicon film formation gas, a doping gas for doping a film with phosphorous or boron, and a grain size adjusting gas containing a component to retard columnar crystal formation from a poly-silicon crystal and to promote miniaturization of the poly-silicon crystal, thereby depositing a silicon film doped with phosphorous or boron on the target substrate.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: April 12, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Okada, Takahiro Miyahara, Toshiharu Nishimura
  • Patent number: 7897471
    Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: March 1, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jifa Hao
  • Patent number: 7833905
    Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: November 16, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Hiraku Chakihara, Mitsuhiro Noguchi, Masahiro Tadokoro, Naonori Wada, Akio Nishida
  • Patent number: 7776669
    Abstract: A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, and including polycrystalline silicon having a constant directivity and a uniformly distributed crystal grain boundary; a gate insulating layer; a gate electrode; an interlayer insulating layer; and source and drain electrodes.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 17, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventor: Ji-Su Ahn
  • Patent number: 7723219
    Abstract: In plasma immersion ion implantation of a polysilicon gate, a hydride of the dopant is employed as a process gas to avoid etching the polysilicon gate, and sufficient argon gas is added to reduce added particle count to below 50 and to reduce plasma impedance fluctuations to 5% or less.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: May 25, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Santhanam, Manoj Vallaikal, Peter I. Porshnev, Majeed A. Foad
  • Patent number: 7682974
    Abstract: A method for manufacturing a semiconductor device includes the steps of: forming an etching layer (17) formed of silicon on a semiconductor substrate (10); forming a mask layer (20) with a pattern on the etching layer (17), which includes an intermediate layer (22) as a silicon oxide film and a top layer (24) as a polysilicon; and etching the etching layer (17) using the mask layer (20) as a mask, and eliminating the top layer (24).
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: March 23, 2010
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Junpei Yamamoto, Suguru Sassa
  • Patent number: 7659213
    Abstract: By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on the basis of silicon. Moreover, by removing a spacer structure used for forming deep drain and source regions, the degree of lateral offset of the strained silicon/carbon material with respect to the gate electrode may be determined substantially independently from other process requirements. Moreover, an additional sidewall spacer used for forming metal silicide regions may be provided with reduced permittivity, thereby additionally contributing to an overall performance enhancement.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 9, 2010
    Assignee: GlobalFoundries, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
  • Patent number: 7601571
    Abstract: A modulator has a transparent substrate with a first surface. At least one interferometric modulator element resides on the first surface. At least one thin film circuit component electrically connected to the element resides on the surface. When more than one interferometric element resides on the first surface, there is at least one thin film circuit component corresponding to each element residing on the first surface. A method of manufacturing interferometric modulators with thin film transistors is also disclosed.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: October 13, 2009
    Assignee: IDC, LLC
    Inventors: Clarence Chui, Stephen Zee
  • Patent number: 7595266
    Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: September 29, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hiraku Chakihara, Mitsuhiro Noguchi, Masahiro Tadokoro, Naonori Wada, Akio Nishida
  • Publication number: 20090191686
    Abstract: A method for preparing a doped polysilicon conductor according to this aspect of the present invention comprises the steps of (a) placing a substrate in a reaction chamber, (b) performing a deposition process to form a polysilicon layer on the substrate, (c) performing a grain growth process to form a plurality of polysilicon grains on the polysilicon layer, and (d) performing a dopant diffusion process to diffuse conductive dopants into the polysilicon layer via the polysilicon grains to form the doped polysilicon conductor.
    Type: Application
    Filed: April 23, 2008
    Publication date: July 30, 2009
    Applicant: PROMOS TECHNOLOGIES INC.
    Inventors: Chun Yao Wang, Fu Hsiung Yang
  • Patent number: 7528026
    Abstract: By consuming a surface portion of polysilicon material or silicon material after implantation and prior to activation of dopants, contaminants may be efficiently removed, thereby significantly enhancing the process uniformity during a subsequent silicidation process. Hence, the defect rate during the silicidation process, for instance “missing silicide” defects, may be significantly reduced, thereby also enhancing the reliability of static RAM cells.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: May 5, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Markus Lenski, Ralf Van Bentum, Ekkehard Pruefer
  • Publication number: 20090108323
    Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.
    Type: Application
    Filed: August 15, 2008
    Publication date: April 30, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
  • Patent number: 7501673
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer may be formed from an amorphous semiconductor material. An ohmic contact layer is formed over the diffusion barrier layer. A metal barrier layer is formed over the ohmic contact layer. A metal layer is formed over the metal barrier layer.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: March 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwa Park, Hee-Sook Park, Dae-Yong Kim, Jang-Hee Lee
  • Publication number: 20090026528
    Abstract: Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology.
    Type: Application
    Filed: October 8, 2008
    Publication date: January 29, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sung Kee PARK, Young Seon YOU, Yong Wook KIM, Yoo Nam JEON
  • Patent number: 7439116
    Abstract: Apparatus and method for forming a polycrystalline silicon thin film by converting an amorphous silicon thin film into the polycrystalline silicon thin film using a metal are provided. The method includes: a metal nucleus adsorbing step of introducing a vapor phase metal compound into a process space where the glass substrate having the amorphous silicon formed thereon is disposed, to adsorb a metal nucleus contained in the metal compound into the amorphous silicon layer; a metal nucleus distribution region-forming step of forming a community region including a plurality of silicon particles every metal nucleus in a plane boundary region occupied by the metal compound by a self-limited mechanism due to the adsorption of the metal nucleus; and an excess gas removing step of purging and removing an excess gas which is not adsorbed in the metal nucleus distribution region-forming step.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: October 21, 2008
    Inventors: Taek Yong Jang, Byoung Il Lee, Young Ho Lee
  • Patent number: 7439088
    Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line crossing each other to define a pixel region, a thin film transistor at a crossing of the gate and data lines, a metal pattern over the gate line, a passivation layer exposing the substrate in the pixel region, a part of the thin film transistor and a part of the metal pattern, and a pixel electrode in the pixel region. The pixel electrode is connected to the part of the thin film transistor and contacts the part of the metal pattern. The metal pattern has at least one curved portion in a side contacting the pixel electrode.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: October 21, 2008
    Assignee: LG Display Co., Ltd.
    Inventor: Jae-Jun Ahn
  • Patent number: 7393765
    Abstract: Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out low temperature CVD steps with a toroidal RF plasma current while applying an RF plasma bias voltage. The temperature of the workpiece is held below a threshold photoresist removal temperature. The RF bias voltage is held at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 1, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Hiroji Hanawa, Kartik Ramaswamy, Kenneth S. Collins, Amir Al-Bayati, Biagio Gallo, Andrew Nguyen
  • Patent number: 7361577
    Abstract: In a step of doping a silicon-based semiconductor film as a TFT active layer such as channel doping or the like, a protective film is formed by a CVD method as a pretreatment so as to prevent the silicon-based semiconductor film from being contaminated and etched. However, in the case of using the protective film formed by the CVD method, the problems in terms of throughput and production cost (an expensive apparatus is required) have been pointed out. The present invention is intended to solve the above-mentioned problems. Instead of the CVD method, a step of forming a chemical oxide film on a silicon-based semiconductor film is introduced as the pretreatment in the step of doping the silicon-based semiconductor film. Alternatively, a step is introduced in which unsaturated bonds present at the surface of the silicon-based semiconductor film are made to terminate with an element (for instance, oxygen) to be bonded with bonding energy higher than that of Si—H bonds.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: April 22, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Patent number: 7312137
    Abstract: A transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and forming a crystalline germanium implantation region beneath the amorphous germanium implantation region. The workpiece is annealed using a low-temperature anneal to convert the amorphous germanium region to a crystalline state while preventing a substantial amount of diffusion of germanium further into the workpiece, also removing damage to the workpiece caused by the implantation process. The resulting structure includes a crystalline germanium implantation region at the top surface of a channel, comprising a depth below the top surface of the workpiece of about 120 ? or less. The transistor has increased mobility and a reduced effective oxide thickness (EOT).
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: December 25, 2007
    Assignee: Infineon Technologies AG
    Inventor: Hong-Jyh Li
  • Patent number: 7303995
    Abstract: A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: December 4, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
  • Patent number: 7268065
    Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
  • Publication number: 20070173041
    Abstract: The invention relates to a method of manufacturing a semiconductor device (10) in which a semiconductor body (1) of silicon is provided, at a surface thereof, with a semiconductor region (4) of a first conductivity type, in which region a second semiconductor region (2A, 3A) of a second conductivity type, opposite to the first conductivity type, is formed forming a pn-junction with the first semiconductor region (4) by the introduction of dopant atoms of the second conductivity type into the semiconductor body (1), and wherein, before the introduction of said dopant atoms, an amorphous region is formed in the semiconductor body (1) by means of an amorphizing implantation of inert atoms, and wherein, after the amorphizing implantation, temporary dopant atoms are implanted in the semiconductor body (1), and wherein, after introduction of the dopant atoms of the second conductivity type, the semiconductor body is annealed by subjecting it to a heat treatment at a temperature in the range of about 500 to about 80
    Type: Application
    Filed: March 7, 2005
    Publication date: July 26, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventor: Bartlomiej Pawlak
  • Patent number: 7223676
    Abstract: A low temperature process for depositing a coating containing any of silicon, nitrogen, hydrogen or oxygen on a workpiece includes placing the workpiece in a reactor chamber facing a processing region of the chamber, introducing a process gas containing any of silicon, nitrogen, hydrogen or oxygen into the reactor chamber, generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at an HF frequency on the order of about 10 MHz to a portion of a reentrant conduit external of the chamber and forming a portion of the reentrant path, applying RF plasma bias power at an LF frequency on the order of one or a few MHz to the workpiece, and maintaining the temperature of the workpiece under about 100 degrees C.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: May 29, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Hiroji Hanawa, Kartik Ramaswamy, Kenneth S. Collins, Amir Al-Bayati, Biagio Gallo, Andrew Nguyen
  • Patent number: 7220647
    Abstract: A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that silicon nitride residues formed in a reaction between the nitrogen-containing barrier layer and the silicon-containing gate layer can be removed and the amount of pollutants and particles can be reduced. Ultimately, the yield of the process as well as the quality and reliability of the device are improved.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: May 22, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ning Wu, Charlie C J Lee, Kuan-Yang Liao
  • Patent number: 7192854
    Abstract: A method of plasma doping in which dilution of B2H6 is maximized for enhanced safety and stable plasma generation and sustention can be carried out without lowering of doping efficiency and in which the amount of dopant injected can be easily controlled. In particular, a method of plasma doping characterized in that B2H6 gas is used as a material containing doping impurity while He is used as a substance of high dissociation energy and that the concentration of B2H6 in mixed gas is less than 0.05%.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: March 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuichiro Sasaki, Bunji Mizuno, Ichiro Nakayama, Hisataka Kanada, Tomohiro Okumura
  • Patent number: 7094670
    Abstract: A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level, performing plasma immersion ion implantation on the workpiece by introducing an implant species precursor gas into the chamber and generating a plasma while minimizing deposition and minimizing etching by holding the temperature of the workpiece within a temperature range that is above a workpiece deposition threshold temperature and below a workpiece etch threshold temperature.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: August 22, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo
  • Patent number: 7084000
    Abstract: A solid-state imaging device according to the present invention includes a semiconductor substrate; a photoelectric conversion portion formed on the semiconductor substrate; a gate insulating film formed on the semiconductor substrate and covering the photoelectric conversion portion; a vertical transfer portion for transferring a charge generated at the photoelectric conversion portion in a vertical direction; and a multilayer transfer gate electrode for transferring the charge of the vertical transfer portion. At least one layer of the multilayer transfer gate electrode is made of at least two impurity doped amorphous silicon films of different impurity concentration.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: August 1, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoki Iwawaki
  • Patent number: 6855605
    Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: February 15, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Malgorzata Jurczak, Rita Rooyackers, Emmanuel Augendre, Goncal Badenes