To Modify Their Internal Properties, E.g., To Produce Internal Imperfections (epo) Patents (Class 257/E21.317)
  • Patent number: 11721674
    Abstract: A Micro-LED array device based on III-nitride semiconductors and a method for fabricating the same are provided. The Micro-LED array device includes arrayed sector mesa structures that are formed by etching to penetrate through a p-type GaN layer and a quantum-well active layer and deep into an n-type GaN layer, a p-type electrode array deposited by evaporation on the p-type GaN layer of sector arrays, and an n-type electrode array deposited by evaporation on the n-type GaN layer. The n-type electrode array forms blocking walls to isolate the sector mesas from one another. The blocking walls, and each of the blocking walls and the annular structure surrounding the sector mesa are connected to each other.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: August 8, 2023
    Assignee: NANJING UNIVERSITY
    Inventors: Tao Tao, Xuan Wang, Feifan Xu, Bin Liu, Ting Zhi, Rong Zhang
  • Patent number: 11664795
    Abstract: A switch circuit of an embodiment includes a radio-frequency switch and a level shifter circuit. The radio-frequency switch, which includes a first switch group and a second switch group each including a plurality of switches, switches transmission/reception of a radio-frequency signal. The level shifter circuit outputs a first signal for controlling ON/OFF of each switch of the first switch group and a second signal for controlling ON/OFF of each switch of the second switch group.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: May 30, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Satoshi Kurachi
  • Patent number: 10526728
    Abstract: A manufacturing method of this invention includes: a step of slicing a silicon single crystal containing boron as an acceptor and obtaining a non-heat-treated silicon wafer, a step of determining a boron concentration with respect to the non-heat-treated silicon wafer, and a step of determining an oxygen donor concentration with respect to the non-heat-treated silicon wafer, in which a determination as to whether or not to perform a heat treatment at a temperature of 300° C. or more on the non-heat-treated silicon wafer is made based on a boron concentration determined in the step of determining a boron concentration, and an oxygen donor concentration determined in the step of determining an oxygen donor concentration. By this means, a wafer in which unevenly distributed LPDs that are present on the wafer are reduced is obtained.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: January 7, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Satoshi Kudo, Kouzou Nakamura, Toshiyuki Muranaka, Shuhei Matsuda, Tegi Kim, Keiichiro Hiraki
  • Patent number: 9496342
    Abstract: A MOSFET and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100), a dummy gate structure (200), a epitaxial protection layer (101) and a sacrificial spacer (205); b. covering the dummy gate structure (200) and the substrate (100) on one side thereof by a mask layer, and forming a vacancy (102) in the substrate; c. growing a semiconductor layer (300) on the semiconductor structure to fill in the vacancy (102); d. removing the epitaxial protection layer (101) and the sacrificial spacer (205), and sequentially forming source/drain extension regions, a spacer (201), source/drain regions, and an interlayer dielectric layer (500); and e. removing the dummy gate structure (200) to form a dummy gate vacancy, and forming a gate stack in the dummy gate vacancy. In the MOSFET structure of the present disclosure, negative effects of DIBL on device performance can be effectively reduced.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: November 15, 2016
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Haizhou Yin
  • Patent number: 8895407
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Patent number: 8884375
    Abstract: A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: November 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Nakai, Masato Suga, Jusuke Ogura
  • Patent number: 8772129
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Patent number: 8658516
    Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 25, 2014
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Patent number: 8638001
    Abstract: An object of the present invention is to provide an adhesive sheet that can capture cations mixed in from outside during various processes of manufacturing a semiconductor device to prevent deterioration in electrical characteristics of a semiconductor device to be manufactured and to improve product reliability. It is an adhesive sheet for producing a semiconductor device, in which when 2.5 g of the adhesive sheet is soaked in 50 ml of an aqueous solution containing 10 ppm of copper ions, and the solution is left at 120° C. for 20 hours, the concentration of copper ions in the aqueous solution is 0 to 9.9 ppm.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: January 28, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Yuta Kimura, Yasushi Inoue, Takeshi Matsumura
  • Patent number: 8629044
    Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 14, 2014
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Patent number: 8587025
    Abstract: A method for forming a laterally varying n-type doping concentration is provided. The method includes providing a semiconductor wafer with a first surface, a second surface arranged opposite to the first surface and a first n-type semiconductor layer having a first maximum doping concentration, implanting protons of a first maximum energy into the first n-type semiconductor layer, and locally treating the second surface with a masked hydrogen plasma. Further, a semiconductor device is provided.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina
  • Patent number: 8575652
    Abstract: An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiki Kamata
  • Publication number: 20130252424
    Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hung Lin, Li-Ting Wang, Tze-Liang Lee
  • Publication number: 20130203229
    Abstract: The present invention provides a method of reducing a surface doping concentration of a doped diffusion region. First, a semiconductor substrate is provided. The semiconductor substrate has the doped diffusion region disposed therein, and the doped diffusion region is in contact with a surface of the semiconductor substrate. A doping concentration of the doped diffusion region close to the surface is larger than a doping concentration of the doped diffusion region away from the surface. Then, a thermal oxidation process is performed to form an oxide layer on the surface of the semiconductor substrate. A part of the doped diffusion region in contact with the surface reacts with oxygen to form a part of the oxide layer. Then, the oxide layer is removed.
    Type: Application
    Filed: June 29, 2012
    Publication date: August 8, 2013
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8492248
    Abstract: A surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region, an insulating layer is formed over the surface of the single crystal semiconductor substrate, and a surface of a substrate having an insulating surface is made to be in contact with a surface of the insulating layer to bond the substrate having an insulating surface to the single crystal semiconductor substrate. Then, the single crystal semiconductor substrate is separated at the damaged region by performing heat treatment to form a single crystal semiconductor layer over the substrate having an insulating surface, and the single crystal semiconductor layer is patterned to form a plurality of island-shaped semiconductor layers. One of the island-shaped semiconductor layers is irradiated with a laser beam which is shaped to entirely cover the island-shaped semiconductor layer.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Tanaka
  • Publication number: 20130149843
    Abstract: An in-situ gettering method for removing impurities from the surface and interior of a upgraded metallurgical grade silicon wafer is continuously conducted in a reaction chamber. Chloride gas is mixed with carrier gas. The gaseous mixture is used to clean the surface of the silicon wafer. Then, the gaseous mixture is used to form a porous structure on the surface of the silicon wafer before hot annealing is executed. Finally, the gaseous mixture is used to execute hot etching on the surface of the silicon wafer and remove the porous structure from the surface of the silicon wafer. As the chloride gas is used to clean the surface of the silicon wafer and form the porous structure on the surface of the silicon wafer, external gettering is improved. Moreover, interstitial-type metal impurities are effectively removed from the interior of the silicon wafer.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Jin-Jang Jheng, Tsun-Neng Yang, Chin-Chen Chiang
  • Patent number: 8440551
    Abstract: A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: May 14, 2013
    Assignee: ULVAC, Inc.
    Inventors: Kazuhiko Tonari, Tsutomu Nishihashi
  • Publication number: 20130109134
    Abstract: A method of manufacturing a semiconductor device, includes introducing a substrate into a growth furnace, forming impurity absorption layers on the substrate and on inner walls of the growth furnace, the impurity absorption layers absorbing impurities on a surface of the substrate and impurities in the growth furnace, etching and removing the impurity absorption layers and a portion of the substrate to produce a thinned substrate, forming a buffer layer on the thinned substrate, and forming semiconductor layers on the buffer layer.
    Type: Application
    Filed: June 28, 2012
    Publication date: May 2, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Susumu HATAKENAKA, Zempei KAWAZU, Hiroyuki KAWAHARA, Takashi NAGIRA
  • Publication number: 20130092949
    Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.
    Type: Application
    Filed: September 12, 2012
    Publication date: April 18, 2013
    Inventors: Nobuyuki Ikarashi, Masayasu Tanaka
  • Publication number: 20130049173
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph Benedetto
  • Patent number: 8383496
    Abstract: A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: February 26, 2013
    Inventors: Kazuhiko Tonari, Tsutomu Nishihashi
  • Patent number: 8377799
    Abstract: An object of the present invention is to provide an SOI substrate including a semiconductor layer which is efficiently planarized. A method for manufacturing an SOI substrate includes a step of irradiating a bond substrate with an accelerated ion to form an embrittlement region; a step of bonding the bond substrate and the base substrate with an insulating layer positioned therebetween; a step of splitting the bond substrate at the embrittlement region to leave a semiconductor layer bonded to the base substrate; a step of disposing the semiconductor layer in front of a semiconductor target containing the same semiconductor material as the semiconductor layer; and a step of alternately irradiating the surface of the semiconductor layer and the semiconductor target with a rare gas ion, so that the surface of the semiconductor layer is planarized.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: February 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Mizuho Sato, Noriaki Uto
  • Publication number: 20130040438
    Abstract: A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Hong He, Alexander Reznicek, Devendra K. Sadana, Paul D. Brabant, Keith Chung, Manabu Shinriki
  • Publication number: 20130020585
    Abstract: A silicon carbide substrate capable of reducing on-resistance and improving yield of semiconductor devices is made of single-crystal silicon carbide, and sulfur atoms are present in one main surface at a ratio of not less than 60×1010 atoms/cm2 and not more than 2000×1010 atoms/cm2, and oxygen atoms are present in the one main surface at a ratio of not less than 3 at % and not more than 30 at %.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 24, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Keiji ISHIBASHI
  • Publication number: 20130017672
    Abstract: A plasma treatment method includes: creating a plasma from a mixed gas containing carbon and nitrogen to generate CN active species, and treating a surface of a semiconductor substrate with the CN active species.
    Type: Application
    Filed: July 7, 2012
    Publication date: January 17, 2013
    Applicant: SONY CORPORATION
    Inventors: Nobuyuki Kuboi, Masanaga Fukusawa
  • Publication number: 20130009725
    Abstract: The invention relates to a Radio Frequency System and method. A Radio Frequency (RF) system comprising a RF switch comprising a plurality of transistor switching elements implemented on Silicon on Insulator (SOI) for switching at least one or more RF signals and said SOI comprises a bulk substrate region and a buried oxide region. At least one filter is adapted to isolate the RF signal from the substrate and/or other high frequency signals or control signals present in the RF system. There is also provided a coupling capacitor adapted to cooperate with the filter to improve linearity of the transistor switch elements.
    Type: Application
    Filed: October 18, 2010
    Publication date: January 10, 2013
    Applicant: FERFICS LIMITED
    Inventors: Eugene Heaney, John O'Sullivan, Stephen Kenney
  • Publication number: 20130005094
    Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.
    Type: Application
    Filed: September 10, 2012
    Publication date: January 3, 2013
    Inventors: Masaya KADONO, Shunpei YAMAZAKI, Yukio YAMAUCHI, Hidehito KITAKADO
  • Patent number: 8338269
    Abstract: Methods and apparatus provide for forming a semiconductor-on-insulator (SOI) structure, including subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that at least one parameter of the weakened slice varies spatially across the weakened slice in at least one of X- and Y- axial directions.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: December 25, 2012
    Assignee: Corning Incorporated
    Inventors: Sarko Cherekdjian, Jeffrey Scott Cites, James Gregory Couillard, Richard Orr Maschmeyer, Michael John Moore, Alex Usenko
  • Patent number: 8324084
    Abstract: An object is to provide a manufacturing method of a semiconductor substrate provided with a single crystal semiconductor layer with a surface having a high degree of flatness. Another object is to manufacture a semiconductor device with high reliability by using the semiconductor substrate provided with a single crystal semiconductor layer with a high degree of flatness. In a manufacturing process of a semiconductor substrate, a thin embrittled region containing a large crystal defect is formed in a single crystal semiconductor substrate at a predetermined depth by subjecting the single crystal semiconductor substrate to a rare gas ion irradiation step, a laser irradiation step, and a hydrogen ion irradiation step. Then, by performing a separation heating step, a single crystal semiconductor layer that is flatter on a surface side than the embrittled region is transferred to a base substrate.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichi Koezuka
  • Publication number: 20120302042
    Abstract: An object of the present invention is to provide an adhesive composition that can form an adhesive sheet for producing a semiconductor device capable of suppressing deterioration in ion scavengeability after the adhesive sheet goes through thermal history. It is an adhesive composition for producing a semiconductor device containing at least an organic complex-forming compound that forms a complex with cations, and the 5% weight loss temperature of the organic complex-forming compound measured by thermogravimetry is 180° C. or more.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 29, 2012
    Inventors: Yuta KIMURA, Yasushi INOUE, Takeshi MATSUMURA
  • Publication number: 20120252197
    Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of boron amide precursor or an organoboron precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 8273624
    Abstract: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting ions into a substrate includes providing a substrate into a processing chamber, generating a plasma from a gas mixture including a reacting gas and a etching gas in the chamber, adjusting the ratio between the reacting gas and the etching gas in the supplied gas mixture and implanting ions from the plasma into the substrate. In another embodiment, the method includes providing a substrate into a processing chamber, supplying a gas mixture including reacting gas and a halogen containing reducing gas into the chamber, forming a plasma from the gas mixture, gradually increasing the ratio of the etching gas in the gas mixture, and implanting ions from the gas mixture into the substrate.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: September 25, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Peter Porshnev, Majeed A. Foad
  • Publication number: 20120205821
    Abstract: Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 16, 2012
    Inventors: Michael Tan, Cheng P. Pour
  • Patent number: 8242033
    Abstract: Methods for making and/or treating articles of semiconducting material are disclosed. In various methods, a first article of semiconducting material is provided, the first article of semiconducting material is heated sufficiently to melt the semiconducting material, and the melted semiconducting material is solidified in a direction substantially parallel to a shortest dimension of the melted article of semiconducting material. Articles of semiconducting materials made by methods described herein are also disclosed.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: August 14, 2012
    Assignee: Corning Incorporated
    Inventors: Glen Bennett Cook, Prantik Mazumder, Balram Suman, Natesan Venkataraman
  • Patent number: 8236709
    Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Domenicucci, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang
  • Publication number: 20120164818
    Abstract: Disclosed is a process for cleaning a wafer having an uneven pattern at its surface. The process includes at least: a step of cleaning the wafer; a step of substituting a cleaning liquid retained in recessed portions of the wafer with a water-repellent liquid chemical after cleaning; and a step of drying the wafer. The process is characterized in that the cleaning liquid has a boiling point of 55 to 200° C., and characterized in that the water-repellent liquid chemical used for the substitution has a temperature of not lower than 40° C. and lower than a boiling point of the water-repellent liquid chemical thereby imparting water repellency at least to surfaces of the recessed portions. With this process, it is possible to provide a cleaning process for improving the cleaning step that tends to induce a pattern collapse.
    Type: Application
    Filed: February 22, 2011
    Publication date: June 28, 2012
    Applicant: Central Glass Company, Limited
    Inventors: Soichi KUMON, Takashi SAIO, Shinobu ARATA, Masanori SAITO, Hidehisa NANAI, Yoshinori AKAMATSU
  • Publication number: 20120146024
    Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered Bettering structure that can be used to control wafer warpage.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Inventors: David Lysacek, Jana Vojtechovska, Lubomir Dornak, Petr Kostelnik, Lukas Valek, Petr Panek
  • Patent number: 8196546
    Abstract: Methods and apparatus provide for: a first source of plasma, wherein the plasma includes a first species of ions; a second source of plasma, wherein the plasma includes a second species of ions; selection of the plasma from the first and second sources; and acceleration the first species of ions or the second species of ions toward a semiconductor wafer.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: June 12, 2012
    Assignee: Corning Incorporated
    Inventor: Sarko Cherekdjian
  • Publication number: 20120122300
    Abstract: An apparatus comprising a microelectromechanical system. The microelectromechanical system includes a crystalline structural element having dislocations therein. For at least about 60 percent of adjacent pairs of the dislocations, direction vectors of the dislocations form acute angles of less than about 45 degrees.
    Type: Application
    Filed: January 26, 2012
    Publication date: May 17, 2012
    Applicant: Lucent Technologies Inc.
    Inventor: George Patrick Watson
  • Publication number: 20120108042
    Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.
    Type: Application
    Filed: November 3, 2010
    Publication date: May 3, 2012
    Inventors: Jennifer Lequn Liu, Shu Qin, Allen McTeer, Yongjun Jeff Hu
  • Publication number: 20120083099
    Abstract: The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 5, 2012
    Applicant: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. NUZZO, John A. ROGERS, Etienne MENARD, Keon Jae LEE, Dahl-Young KHANG, Yugang SUN, Matthew MEITL, Zhengtao ZHU, Heung Cho KO, Shawn MACK
  • Patent number: 8143142
    Abstract: A method of fabricating an epi-wafer includes providing a wafer including boron by cutting a single crystal silicon ingot, growing an insulating layer on one surface of the wafer, performing thermal treatment of the wafer, removing the insulating layer formed on one surface of the wafer, mirror-surface-grinding one surface of the wafer, and growing an epitaxial layer on one surface of the wafer and forming a high-density boron layer within the wafer that corresponds to the interface between the wafer and the epitaxial layer.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 27, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Young-Soo Park, Gi-Jung Kim, Won-Je Park, Jae-Sik Bae
  • Patent number: 8129261
    Abstract: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting ions into a substrate includes providing a substrate into a processing chamber, the substrate comprising substrate surface having one or more features formed therein and each feature having one or more horizontal surfaces and one or more vertical surfaces, generating a plasma from a gas mixture including a reacting gas adapted to produce ions, depositing a material layer on the substrate surface and on at least one horizontal surface of the substrate feature, implanting ions from the plasma into the substrate by an isotropic process into at least one horizontal surface and into at least one vertical surface, and etching the material layer on the substrate surface and the at least one horizontal surface by an anisotropic process.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: March 6, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Peter I. Porshnev, Matthew D. Scotney-Castle, Majeed A. Foad
  • Publication number: 20120034761
    Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include exposing a substrate having an oxide layer thereon to an oxidizing source. The oxidizing source oxidizes an upper portion of the substrate beneath the oxide layer to form an oxide layer having an increased thickness. The oxide layer with the increased thickness is then removed to expose a clean surface of the substrate. The removal of the oxide layer generally includes removal of contaminants present in and on the oxide layer, especially those contaminants present at the interface of the oxide layer and the substrate. An epitaxial layer may then be formed on the clean surface of the substrate.
    Type: Application
    Filed: July 6, 2011
    Publication date: February 9, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Satheesh Kuppurao, Manish Hemkar, Vinh Tran, Yihwan Kim
  • Patent number: 8076727
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20110285004
    Abstract: Methods for protecting circuit device materials, optoelectronic devices, and caps using a reflowable getter are described. The methods, devices and caps provide advantages because they enable modification of the shape and activity of the getter after sealing of the device. Some embodiments of the invention provide a solid composition comprising a reactive material and a phase changing material. The combination of the reactive material and phase changing material is placed in the cavity of an electronic device. After sealing the device by conventional means (epoxy seal for example), the device is subjected to thermal or electromagnetic energy so that the phase changing material becomes liquid, and consequently: exposes the reactive material to the atmosphere of the cavity, distributes the getter more equally within the cavity, and provides enhanced protection of sensitive parts of the device by flowing onto and covering these parts, with a thin layer of material.
    Type: Application
    Filed: July 28, 2011
    Publication date: November 24, 2011
    Inventor: Pierre-Marc Allemand
  • Patent number: 8058148
    Abstract: Methods and apparatus provide for forming a semiconductor-on-insulator (SOI) structure, including subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that at least one parameter of the weakened slice varies spatially across the weakened slice in at least one of X- and Y-axial directions.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: November 15, 2011
    Assignee: Corning Incorporated
    Inventors: Sarko Cherekdjian, Jeffrey Scott Cites, James Gregory Couillard, Richard Orr Maschmeyer, Michael John Moore, Alex Usenko
  • Publication number: 20110244660
    Abstract: An object is to provide a manufacturing method of a semiconductor substrate provided with a single crystal semiconductor layer with a surface having a high degree of flatness. Another object is to manufacture a semiconductor device with high reliability by using the semiconductor substrate provided with a single crystal semiconductor layer with a high degree of flatness. In a manufacturing process of a semiconductor substrate, a thin embrittled region containing a large crystal defect is formed in a single crystal semiconductor substrate at a predetermined depth by subjecting the single crystal semiconductor substrate to a rare gas ion irradiation step, a laser irradiation step, and a hydrogen ion irradiation step. Then, by performing a separation heating step, a single crystal semiconductor layer that is on a surface side than the embrittled region is transferred to a base substrate.
    Type: Application
    Filed: March 25, 2011
    Publication date: October 6, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Junichi KOEZUKA
  • Patent number: 8021962
    Abstract: A method of manufacturing a functional film by which a functional film formed on a film formation substrate can be easily peeled from the film formation substrate. The method includes the steps of: (a) forming a separation layer on a substrate by using an inorganic material which is decomposed to generate a gas by being applied with an electromagnetic wave; (b) forming a layer to be peeled containing a functional film, which is formed by using a functional material, on the separation layer; and (c) applying the electromagnetic wave toward the separation layer so as to peel the layer to be peeled from the substrate or reduce bonding strength between the layer to be peeled and the substrate.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: September 20, 2011
    Assignee: Fujifilm Corporation
    Inventor: Yukio Sakashita
  • Patent number: 8003493
    Abstract: A process for splitting a semiconductor substrate having an identification notch on its periphery, by creating a weakened zone in the substrate by implanting atomic species into the substrate while the substrate is held in place on a portion of its periphery during the implanting; and splitting the substrate along the weakened zone by placing the held portion of the substrate in a splitting-wave initiation sector while positioning the notch for initiating a splitting wave followed by the propagation of the wave into the substrate. During splitting the notch is positioned so that it is in a quarter of the periphery of the substrate diametrically opposite the sector for initiating the splitting wave or in the quarter of the periphery of the substrate that is centered on the sector.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: August 23, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Nadia Ben Mohamed, Sébastien Kerdiles