Of Silicon Body, E.g., For Gettering (epo) Patents (Class 257/E21.318)
  • Patent number: 11005002
    Abstract: The present disclosure relates to a method of manufacturing a semiconductor device, including the successive steps of: a) forming doped germanium on a germanium layer covering a first support; b) covering said doped germanium with a second support; and c) removing the first support.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: May 11, 2021
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Willy Ludurczak, Abdelkader Aliane, Luc Andre, Jean-Louis Ouvrier-Buffet, Julie Widiez
  • Patent number: 10546758
    Abstract: A gettering layer forming method includes a coating step of applying a solution of metal salt to a back side of a wafer, and a diffusing step of heating the wafer after performing the coating step, thereby diffusing the metal salt on the back side of the wafer to form a gettering layer containing the metal salt on the back side of the wafer, in which the metal salt is diffused in the gettering layer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 28, 2020
    Assignee: DISCO CORPORATION
    Inventors: Daigo Shitabo, Seiji Harada, Hiroki Takeuchi
  • Patent number: 10541149
    Abstract: A gettering layer forming method includes a coating step of applying a solution of metal salt to a back side of a wafer, and a drying step of drying the wafer after performing the coating step, thereby forming a gettering layer containing the metal salt on the back side of the wafer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 21, 2020
    Assignee: DISCO CORPORATION
    Inventor: Seiji Harada
  • Patent number: 10329142
    Abstract: A wafer level package includes a wafer member having inner cavities in which circuit elements are disposed, element wall members disposed on an internal surface of the wafer member and enclosing element sections in which the circuit elements are disposed, and clearance wall members disposed on external surfaces of the element wall members and dividing a space between the element sections into clearance sections.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 25, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Moon Chul Lee, Duck Hwan Kim, Yeong Gyu Lee, Jae Chang Lee, Tae Yoon Kim, Kyong Bok Min
  • Patent number: 10276741
    Abstract: A method for eliminating metal composites from a polycrystalline silicon cell piece, comprising the steps of: injecting current into the polycrystalline silicon cell piece under a certain temperature by means of an electric injection method, thereby eliminating the metal composites from the interior of the polycrystalline silicon cell piece; the present invention discloses a simple process, a short processing-time, a low manufacturing cost, and can easily be scaled for manufacture.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 30, 2019
    Assignee: Changzhou Shichuang Energy Technology Co., Ltd.
    Inventors: Changrui Ren, Liming Fu
  • Patent number: 10217638
    Abstract: A method for removing crystal originated particles from a crystalline silicon body having opposite first and second surfaces includes: increasing a surface area of at least one of the first and second surfaces by an etch process; and oxidizing the increased surface area at a temperature of at least 1000° C. and for a duration of at least 20 minutes.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Peter Irsigler
  • Patent number: 10175176
    Abstract: A method of evaluating characteristics of a work piece includes forming a photosensitive layer on the work piece. Then an ion implantation is performed on the work piece. The work piece is radiated, and an optical intensity of the photosensitive material on the work piece is calculated. The ion implantation pattern is evaluated according to the optical intensity. A chemical structure of the photosensitive material is changed upon the ion implantation. The work piece is recovered by reversing the chemical structure of the photosensitive material or removing the ion interrupted photosensitive material by chemicals.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Kuo-Sheng Chuang, You-Hua Chou
  • Patent number: 9892910
    Abstract: A dense array of semiconductor single crystalline semiconductor nanocrystals is provided in the present application by forming an amorphous semiconductor material layer surrounding a plurality of patterned nanostructures comprised of a single crystalline semiconductor material portion. A thermal anneal, i.e., (solid phase epitaxy), is then performed to crystallize a portion of the amorphous semiconductor material layer that is in contact with each single crystalline semiconductor material portion and to provide a plurality of spaced apart single crystalline nanocrystals on a surface of an insulator. A remaining portion of the amorphous semiconductor material layer that was not crystallized is thereafter removed.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hong He, Juntao Li
  • Patent number: 9679820
    Abstract: An evaluation method of a device wafer on which plural devices are formed on a front surface and inside which a gettering layer is formed is provided. In the evaluation method, electromagnetic waves are radiated toward a back surface of the device wafer and excitation light is radiated to generate excess carriers. Furthermore, the gettering capability of the gettering layer formed in the device wafer is determined based on the damping time of reflected electromagnetic waves.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 13, 2017
    Assignee: Disco Corporation
    Inventors: Naoya Sukegawa, Seiji Harada
  • Patent number: 9018735
    Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: April 28, 2015
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Jung-Goo Park
  • Patent number: 8981332
    Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (?fG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Dipankar Pramanik, Milind Weling
  • Patent number: 8846500
    Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered gettering structure that can be used to control wafer warpage.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: David Lysacek, Jana Vojtechovska, Lubomir Dornak, Petr Kostelnik, Lukas Valek, Petr Panek
  • Patent number: 8841158
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 23, 2014
    Assignee: Sony Corporation
    Inventor: Shin Iwabuchi
  • Patent number: 8829532
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: September 9, 2014
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Maik Häberlen, Jörg Lindner, Bernd Stritzker
  • Patent number: 8753961
    Abstract: A method of nucleating and growing oxygen precipitates during a pad oxidation process. The nucleating is performed during in the oxidation furnace prior to the pad oxide growth. At least a portion of the growth of the oxygen precipitates occurs during the pad oxide growth. The oxygen precipitates are of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Bradley David Sucher
  • Patent number: 8728921
    Abstract: A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness to form a thinned substrate; applying a dopant to the back side of the thinned substrate; and laser processing the back side of the thinned substrate to form a plurality of patterns of lasered features containing the dopant. The dopant can be selected to modify properties of the semiconductor substrate such as carrier properties, gettering properties, mechanical properties or visual properties.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim Corbett
  • Patent number: 8664746
    Abstract: A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: March 4, 2014
    Assignee: STMicroelectronics Pte. Ltd.
    Inventors: Janusz Karol Korycinski, Wanliang Wen
  • Patent number: 8658516
    Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 25, 2014
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Patent number: 8642449
    Abstract: A silicon wafer which has DZ layers formed on both sides thereof by heat treatment in an atmosphere of reducing gas (such as hydrogen) or rare gas (such as argon) with a specific temperature profile for heating, holding, and cooling, and which also has a gettering site of BMD in the bulk inside the DZ layer. A silicon wafer which has a silicon epitaxial layer formed on one side thereof. The DZ layer and the silicon epitaxial layer contain dissolved oxygen introduced into their surface parts, with the concentration and distribution of dissolved oxygen properly controlled. Introduction of oxygen into the surface part is accomplished by heat treatment and ensuing rapid cooling in an atmosphere of oxygen-containing gas.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: February 4, 2014
    Assignee: Globalwafers Japan Co., Ltd.
    Inventors: Takashi Watanabe, Ryuji Takeda
  • Patent number: 8638001
    Abstract: An object of the present invention is to provide an adhesive sheet that can capture cations mixed in from outside during various processes of manufacturing a semiconductor device to prevent deterioration in electrical characteristics of a semiconductor device to be manufactured and to improve product reliability. It is an adhesive sheet for producing a semiconductor device, in which when 2.5 g of the adhesive sheet is soaked in 50 ml of an aqueous solution containing 10 ppm of copper ions, and the solution is left at 120° C. for 20 hours, the concentration of copper ions in the aqueous solution is 0 to 9.9 ppm.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: January 28, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Yuta Kimura, Yasushi Inoue, Takeshi Matsumura
  • Patent number: 8629044
    Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 14, 2014
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Publication number: 20130309845
    Abstract: A method of processing a substrate is provided. The method includes providing a substrate, performing a device forming process on the substrate, and cleaning the substrate. The step of cleaning the substrate includes cleaning the substrate with an atomic spray and rinsing the substrate with deionized water.
    Type: Application
    Filed: May 17, 2012
    Publication date: November 21, 2013
    Applicant: UNITED MICRO ELECTRONICS CORP.
    Inventor: Tsung-Hsun Tsai
  • Patent number: 8575661
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventor: Shin Iwabuchi
  • Patent number: 8569175
    Abstract: The invention relates to a method for dry chemical treatment of substrates selected from the group comprising silicon, ceramic, glass, and quartz glass, in which the substrate is treated in a heated reaction chamber with a gas which contains hydrogen chloride as etching agent, and also to a substrate which can be produced in this way. The invention likewise relates to uses of the previously mentioned method.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: October 29, 2013
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.
    Inventors: Stefan Reber, Gerhard Willeke
  • Patent number: 8569149
    Abstract: A method of treating a semiconductor device wherein there is provided a semiconductor device, the semiconductor device being at least in part chemically bonded to an undesired chemical species. The semiconductor device is subjected to light of a wavelength sufficient to cleave at least some of the chemical bonds between the semiconductor device and the undesired chemical species, and the semiconductor device is exposed to a source of a desired chemical species, such that the semiconductor device becomes at least in part chemically bonded to the desired chemical species.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Roy Meade
  • Patent number: 8524002
    Abstract: Silicon wafers doped with nitrogen, hydrogen and carbon, have a plurality of voids, wherein 50% or more of the total number of voids are bubble-like shaped aggregates of voids; a V1 region having a void density of over 2×104/cm3 and below 1×105/cm3 which occupies 20% or less of the total area of the silicon wafer; a V2 region having a void density of 5×102 to 2×104/cm3 which occupies 80% or more of the total area of said silicon wafer; and a bulk micro defect density which is 5×108/cm3 or more, have excellent GOI characteristics and a high C-mode pass rate. The wafers are cut from a single crystal pulled by a method in which carbon, nitrogen, and hydrogen dopants are controlled, and the crystal is subjected to rapid cooling.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 3, 2013
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Masamichi Ohkubo
  • Patent number: 8497208
    Abstract: A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Yoshiyuki Nakao, Noriyoshi Shimizu
  • Publication number: 20130168697
    Abstract: A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 ?m from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives.
    Type: Application
    Filed: September 11, 2012
    Publication date: July 4, 2013
    Applicant: TOKAI CARBON KOREA CO., LTD.
    Inventors: Joung Il Kim, Jae Seok Lim, Mi-Ra Yoon
  • Patent number: 8476149
    Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 2, 2013
    Assignee: Global Wafers Japan Co., Ltd.
    Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
  • Publication number: 20130105806
    Abstract: Silicon nanoparticle inks provide a basis for the formation of desirable materials. Specifically, composites have been formed in thin layers comprising silicon nanoparticles embedded in an amorphous silicon matrix, which can be formed at relatively low temperatures. The composite material can be heated to form a nanocrystalline material having crystals that are non-rod shaped. The nanocrystalline material can have desirable electrical conductive properties, and the materials can be formed with a high dopant level. Also, nanocrystalline silicon pellets can be formed from silicon nanoparticles deposited form an ink in which the pellets can be relatively dense although less dense than bulk silicon. The pellets can be formed from the application of pressure and heat to a silicon nanoparticle layer.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Inventors: Guojun Liu, Shivkumar Chiruvolu, Weidong Li, Uma Srinivasan
  • Publication number: 20130087933
    Abstract: A structure for encapsulating at least one electronic device, including at least one first cavity bounded by a support and at least one cap provided on the support and wherein the electronic device is encapsulated, at least one aperture passing through the cap and communicating the inside of the first cavity with at least one portion of getter material provided in at least one second cavity which is arranged on the support and adjacent to the first cavity, at least one part of said portion of getter material being provided on the support or against at least one outer side wall of the first cavity, the first cavity and the second cavity forming together a hermetically sealed volume.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 11, 2013
    Applicant: Commissariat A L'Energie Atomique ET Aux Energies Alternatives
    Inventor: Commissariat A L'Energie Atomique ET Aux Energies Alternatives
  • Publication number: 20130069203
    Abstract: A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Applicant: STMICROELECTRONICS PTE. LTD.
    Inventors: Janusz Karol Korycinski, Wanliang Wen
  • Publication number: 20130045586
    Abstract: An internal gettering process for a Czochralski silicon wafers comprises: (1) heating a Cz silicon wafer to 1200-1250° C. at a heating rate of 50-100° C./s under a nitrogen atmosphere, maintaining for 30-150 seconds, cooling the Cz silicon wafer to 800-1000° C. first at a cooling rate of 5-50° C./s, and then cooling the Cz silicon wafer naturally; (2) annealing the Cz silicon wafer obtained in the step (1) at 800-900° C. under an argon atmosphere for a period of 8-16 hours. The present invention only involves two heat treatment steps which require lower temperature and shorter time comparing to the conventional processes. The density of the bulk microdefects and the width of the denuded zone can be easily controlled by the temperature, duration and cooling rate of rapid thermal processing in the first step.
    Type: Application
    Filed: March 16, 2012
    Publication date: February 21, 2013
    Applicant: ZHEJIANG UNIVERSITY
    Inventors: Xiangyang Ma, Ze Xu, Biao Wang, Deren Yang
  • Patent number: 8377202
    Abstract: A method for manufacturing a silicon wafer having a defect-free region in a surface layer, in which at least only a surface layer region to a predetermined depth from a front surface of a silicon wafer to be processed is subjected to heat treatment at a temperature of not less than 1100 degrees C. for not less than 0.01 msec to not more than 1 sec, to thereby make the surface layer defect-free. As a result of this, there is provided a method for manufacturing a silicon wafer, in which a DZ layer without generation of crystal defects from the front surface to a constant depth can be uniformly formed, and oxide precipitates having a steep profile inside the wafer can be secured and controlled with a high degree of accuracy.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: February 19, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Koji Ebara
  • Publication number: 20130029497
    Abstract: A method is developed to crystallize amorphous silicon (a-Si) thin films, in cold environment, by combining microwave-absorbing materials (MAM) and microwave irradiation. The MAM is set on top or around of the a-Si thin film. MAM composes of dielectric, magnetic, semiconductor, ferroelectric and carbonaceous material oxides, carbides, nitrides and borides, which will absorb and concentrate electric or magnetic field of the microwave. The microwave frequency is selected from 1 to 50 GHz, at a power density not less than 5 W/cm2. Temperature rise of the MAM is monitored and controlled by an optical pyrometer to be less than 600° C., and better be within 400-500° C. The application of MAM at patterned local areas leads to localized heating and crystallization of a-Si film right at the patterns to facilitate manufacture of semiconductor devices.
    Type: Application
    Filed: February 17, 2012
    Publication date: January 31, 2013
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tsung-Shune Chin, Tsun-Hsu Chang, Shih-Chieh Fong, Hsien-Wen Chao
  • Patent number: 8362530
    Abstract: An active region made of Si or SiGe is formed in a surface part of a substrate. A gate electrode is disposed over the active region. A gate insulating film is disposed between the gate electrode and the substrate. A source and a drain are formed in the surface part of the substrate on sides of the gate electrode. A surface of the active region under the gate electrode includes a slope surface being upward from a border of the active region toward an inner side of the active region. The slope surface has a crystal plane equivalent to (331).
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: January 29, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hidenobu Fukutome
  • Publication number: 20130023097
    Abstract: Semiconductor devices and methods for making such devices are described. The UMOS (U-shaped MOSFET) semiconductor devices can be formed by providing a semiconductor substrate, forming a trench in the substrate using a wet or dry etching process, and then radiating the trench structure using microwaves (MW) at low temperatures. The MW radiation process improves the profile of the trench and repairs the damage to the trench structure caused by the dry etching process. The microwave radiation can help re-align the Si or SiGe atoms in the semiconductor substrate and anneal out the defects present after the dry etching process. As well, the microwave radiation can getter atoms or ions used in the dry etching process that are left in the lattice of the trench structure. Other embodiments are described.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 24, 2013
    Inventor: Robert J. Purtell
  • Patent number: 8357592
    Abstract: A method for manufacturing a semiconductor substrate dedicated to a semiconductor device, in which multi-photon absorption is generated in a micro-region inside the semiconductor substrate by condensing laser beams in any micro-region inside the semiconductor substrate, and a gettering sink is formed by changing the crystal structure of only the micro-region.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: January 22, 2013
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Publication number: 20130015568
    Abstract: Getter structure comprising at least one getter portion arranged on a support and including at least two adjacent getter material parts arranged on the support one beside the other, with different thicknesses and of which the surface grain densities are different from one another.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 17, 2013
    Applicant: Commissariat a I'energie atomique et aux ene alt
    Inventors: Christine FERRANDON, Xavier BAILLIN
  • Patent number: 8349646
    Abstract: A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: January 8, 2013
    Assignee: Infineon Technologies Austria AG
    Inventor: Hans-Joachim Schulze
  • Patent number: 8343853
    Abstract: A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about ?70° C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100° C. or more.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hyoung Koo, Sam-jong Choi, Yeonsook Kim, Taesung Kim, Heesung Kim, KyooChul Cho, Joonyoung Choi
  • Patent number: 8329563
    Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: December 11, 2012
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadaharu Minato, Hidekazu Yamamoto
  • Publication number: 20120306054
    Abstract: A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 6, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Yi-Chiau Huang, Errol Antonio C. Sanchez, Xianzhi Tao
  • Patent number: 8324084
    Abstract: An object is to provide a manufacturing method of a semiconductor substrate provided with a single crystal semiconductor layer with a surface having a high degree of flatness. Another object is to manufacture a semiconductor device with high reliability by using the semiconductor substrate provided with a single crystal semiconductor layer with a high degree of flatness. In a manufacturing process of a semiconductor substrate, a thin embrittled region containing a large crystal defect is formed in a single crystal semiconductor substrate at a predetermined depth by subjecting the single crystal semiconductor substrate to a rare gas ion irradiation step, a laser irradiation step, and a hydrogen ion irradiation step. Then, by performing a separation heating step, a single crystal semiconductor layer that is flatter on a surface side than the embrittled region is transferred to a base substrate.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichi Koezuka
  • Patent number: 8316745
    Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: November 27, 2012
    Assignee: Calisolar Inc.
    Inventors: Fritz G. Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniaina, Dieter Linke
  • Publication number: 20120295416
    Abstract: An object of the present invention is to provide an adhesive sheet that can capture cations mixed in from outside during various processes of manufacturing a semiconductor device to prevent deterioration in electrical characteristics of a semiconductor device to be manufactured and to improve product reliability. It is an adhesive sheet for producing a semiconductor device, in which when 2.5 g of the adhesive sheet is soaked in 50 ml of an aqueous solution containing 10 ppm of copper ions, and the solution is left at 120° C. for 20 hours, the concentration of copper ions in the aqueous solution is 0 to 9.9 ppm.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 22, 2012
    Inventors: Yuta KIMURA, Yasushi INOUE, Takeshi MATSUMURA
  • Patent number: 8309436
    Abstract: A method of producing an epitaxial substrate for a solid-state imaging device, comprising: forming a gettering sink by injecting laser beam to a semiconductor substrate through one surface thereof, condensing the laser beam to an arbitrarily selected portion of the semiconductor substrate, thereby causing multi-photon absorption process to occur in the portion, and forming a gettering sink having a modified crystal structure; and epitaxially growing at least two epitaxial layers on the semiconductor substrate in which the gettering sink is formed.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 13, 2012
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Patent number: 8293613
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Soo Park, Young-Nam Kim, Young-Sam Lim, Gi-Jung Kim, Pil-Kyu Kang
  • Patent number: 8273644
    Abstract: A soldering method of soldering first and second members includes shooting a laser light to at least one part of an outer peripheral portion surrounding a soldering-target region of the first member thereby to form an oxide film, and bonding the second member with the soldering-target region through a solder. According to the method, the solder resist is never exfoliated even after cleaning with chemicals for removing flux residues contained in solder.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: September 25, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazunaga Onishi, Yoshitaka Nishimura, Tatsuo Nishizawa, Eiji Mochizuki
  • Patent number: 8268705
    Abstract: The present invention is a method for producing an SOI wafer comprising at least a step of forming an ion-implanted damaged layer by ion-implanting a neutral element electrically inactive in silicon from one surface of the base wafer or the bond wafer, in which ion-implanting in the step of forming the ion-implanted damaged layer is performed at a dosage of 1×1012 atoms/cm2 or more and less than 1×1015 atoms/cm2. As a result, there may be provided a method for producing an SOI wafer having sufficient gettering ability while the suppression of leak failure, degradation of oxide dielectric breakdown voltage or the like is provided.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: September 18, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno