Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first insulating film on a semiconductor substrate; forming a mask with an opening of a predetermined pattern in the first insulating film; performing anisotropic etching on the semiconductor substrate with the mask used as an etching mask to form a trench; forming a second insulating film on a surface of an inner wall of the trench with the mask used as a selective oxidation mask; removing the mask; forming a conductive film on the semiconductor substrate to fill the trench with the conductive film; and etching back the conductive film until at least a surface of the semiconductor substrate is exposed.

Abstract: A semiconductor device has a drift region (20) (third semiconductor region) of an n-type (first conductivity type); a body region (50) (second semiconductor region) of a p-type (second conductivity type) provided on the drift region (20); an emitter region (60) (first semiconductor region) of the n-type formed in the top surface of the body region (50) and separated from the drift region (20) by the body region (50); a trench (14) extending from the top surface of the emitter region (60) through the body region (50) into the drift region (20); a trench gate electrode (13) filled in the trench (14); and a semiconductor region (70) (fourth semiconductor region) of the p-type formed in contact with side faces of the trench protruding into the drift region (20). Therefore, the semiconductor device can suppress a surge voltage at turn-off, and can be produced easily.

Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

Abstract: A method for fabricating a semiconductor device is provided which has first and second regions, transistors of different conductivity types being formed on parts of a substrate corresponding to the first and second regions. The method includeujs the steps of: (a) forming a first insulating film to cover the parts of the substrate corresponding to the first and second regions; (b) forming a first thin film on the first insulating film, the first thin film having a relatively higher etching rate than the first insulating film in plasma etching using a halogen gas; and (c) removing a part of the first thin film corresponding to the first region by the plasma etching using a mask covering the second region and modifying a part of the first insulating film corresponding to the first region.

Abstract: On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird's beak length by the silicon oxide film.

Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

Abstract: A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material layer on a semiconductor substrate; forming a photoresist layer on the semiconductor substrate so as to expose extension region formation portions of the trench-type cell transistor region and a high breakdown voltage transistor region; forming extension regions in each region by performing ion implantation in the semiconductor substrate surface of the trench-type cell transistor region and the high breakdown voltage transistor region and then patterning gates, and forming extension regions of an ordinary breakdown voltage transistor by covering the trench-type cell transistor region and the high breakdown voltage transistor region with a photoresist layer and implanting ions in the ordinary breakdown voltage transistor region.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.

Abstract: A method for forming a memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

Abstract: A method for fabricating a fin transistor includes patterning a first pad layer provided over a substrate using an isolation mask, etching the substrate using the isolation mask and the first pad layer to form trenches, filling the trenches with an insulating material to form isolation structures, etching the isolation structures within the trenches using a gas having a high selectivity ratio of the insulating material to the first pad layer to form fin structures, forming a gate insulating layer over the fin structures, and forming a conductive layer over the gate insulating layer.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: A method of fabricating a semiconductor device includes: forming an insulating film on a semiconductor body to cover a termination area surrounding a cell area; forming a mask material film to cover the cell area and the insulating film; forming a resist film to cover the mask material film; patterning the resist film to have an opening serving as a gate-use resist pattern above the cell area and another opening serving as a dummy resist pattern above the insulating film; selectively etching the mask material film by use of the patterned resist film as a mask so that the insulating film is remained under the dummy resist pattern; selectively etching the semiconductor body by use of the patterned mask material film as another mask to form a trench in the cell area as corresponding to the gate-use resist pattern; and burying gate material in the trench to form the trench gate.

Abstract: A method for fabricating a semiconductor device having a flask type recess gate includes forming a hard mask pattern on a substrate, etching the substrate to a predetermined depth using the hard mask pattern to form a first recess pattern, forming a passivation layer on sidewalls of the first recess pattern and the hard mask pattern, etching a bottom surface of the first recess pattern exposed by the passivation layer to form a second recess pattern, oxidizing sidewalls of the second recess pattern to form a silicon oxide layer, removing the passivation layer and the silicon oxide layer in sequential order, and forming a gate pattern over an intended recess pattern including the first recess pattern and the second recess pattern.

Abstract: This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.

Abstract: A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof is larger than the width of the trench. An emitter electrode is formed on the first main surface and insulated from the gate electrode electrically and connected to a whole upper surface of the expanding part of the potential fixing electrode. Thus, a semiconductor device capable of enhancing reliability in order to prevent an aluminum spike from generating and a manufacturing method thereof can be provided.

Abstract: A p-type collector layer is formed on a reverse side of an n-type high-resistivity first base layer, a p-type second base layer is formed on an obverse side of the first base layer, an emitter layer is formed on the second base layer, gate electrodes are formed inside trenches extending in a direction and intruding through the emitter layer and the second base layer into intermediate depths of the first base layer, with gate insulating films in between, a collector electrode is connected to the collector layer, an emitter electrode is connected to the emitter layer, the first base layer and the second base layer, the emitter layer is composed of first emitter layers extending along the trenches in the direction, and second emitter layers extending in a perpendicular direction for a ladder form interconnection between first emitter layers, and the base contact layer has a higher impurity density than the second base layer, and envelopes the second emitter layers.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Abstract: A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.

Abstract: A method for forming a semiconductor structure includes the following steps. A starting semiconductor substrate having a top-side surface and a back-side surface is provided. A recess is formed in the starting semiconductor substrate through the top-side of the starting semiconductor substrate. A semiconductor material is formed in the recess. A vertically conducting device is formed in and over the semiconductor material, where the starting semiconductor substrate serves as a terminal of the vertically conducting device. A non-recessed portion of the starting semiconductor substrate allows a top-side contact to be made to portions of the starting semiconductor substrate extending beneath the semiconductor material.

Abstract: A semiconductor device includes: a semiconductor substrate; a separation region in the substrate; an embedded layer; a channel forming region; a source region; a drain region; a first electrode for the source region; a second electrode for the channel forming region; a third electrode for the drain region; a trench penetrating the channel forming region between the source region and the drain region; a trench gate electrode in the trench; an offset layer on a portion to be a current path provided by the trench gate electrode; and an electric field relaxation layer under the channel forming region and the offset layer connected to the channel forming region and covering a bottom of the trench.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

Abstract: The present invention provides a vertical tapered dielectric high-voltage device (10) in which the device drift region is depicted by action of MOS field plates (30) formed in vertical trenches. The high-voltage device comprises: a substrate (32); a silicon mesa (20) formed on the substrate and having a stripe geometry, wherein the silicon mesa provides a drift region having a constant doping profile; a recessed gate (22) and source (SN) formed on the silicon mesa; a trench (26) adjacent each side of the silicon mesa; and a metal-dielectric field plate structure (12) formed in each trench; wherein each metal-dielectric field plate structure comprises a dielectric (28) and a metal field plate (30) formed over the dielectric, and wherein a thickness of the dielectric increases linearly through a depth of the trench to provide a constant longitudinal electric field.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: Even when the spaces between the gate wiring become wide, a power semiconductor device can be obtained to meet requirements for increased current capacity and higher reliability. The power semiconductor device has an n+ buffer layer 56 provided on the p+ collector layer 55; an n? layer 57 provided on the n+ buffer layer 56; a p base region 58 provided selectively in the top side of the n? layer 57; an n+ emitter region 59 provided selectively in the top side of the p base region 58; a gate insulation film 60 provided on the n? layer 57 and portions of the p base region 58 and the n+ emitter region 59; a gate electrode 1 including a polysilicon film 1a provided on the gate insulation film 60, and a doped polysilicon film that is provided on the polysilicon film 1a and doped with impurities; an emitter electrode that is provided on the p base region 58 and is electrically connected with the n+ emitter region 59; a collector electrode provided on the bottom side of the p+ collector layer.

Abstract: A buried-contact solar cell, in-process buried-contact solar cell components and methods for making buried contact solar cells wherein a self-doping contact material is placed in a plurality of buried-contact surface grooves. By combining groove doping and metallization steps, the resulting solar cell is simpler and more economical to manufacture.

Abstract: A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by patterning the polycrystalline silicon film in an active cell area, a gate electrode is formed within the groove portion, and the inside of the groove portion is embedded in a gate wiring area. Extending to the outside of the groove portion continuously out of the groove portion, there is a gate drawing electrode electrically connected to the gate electrode. Slits extending from the end portion of the gate drawing electrode are formed in the gate drawing electrode outside of the groove portion. Then, a silicon oxide film and a BPSG film are deposited on the substrate.

Abstract: A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate.

Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

Abstract: A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.

Abstract: A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.

Abstract: The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.

Abstract: A method of manufacturing a semiconductor device is disclosed that includes the treating the surface of a SiC semiconductor substrate prior to forming a gate oxide film on the SiC semiconductor substrate in order to etch the SiC semiconductor substrate by several nm to 0.1 ?m with hydrogen in a reaction furnace. The treating is conducted a reduced pressure in the furnace, at a temperature of 1500° C. or higher. The manufacturing method facilitates the removal of particles and oxide residues remaining on the trench inner wall after trench etching in the manufacturing process for manufacturing a SiC semiconductor device having a fine trench-type MOS gate structure.

Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.

Abstract: In fabricating a transistor having the round corner recess channel structure, a buffer layer and a hard mask layer are formed in the active area of a semiconductor substrate. The buffer layer and the hard mask layer are etched so as to expose a predetermined channel region of the active area in the substrate. The predetermined channel region is wet etched to undercut the buffer layer below the hard mask layer. The exposed area of the substrate is etched by using the hard mask layer as an etching barrier so as to form a recess. The hard mask layer is removed. Light etch treatment is performed to round out the top corner of the recess. The buffer layer is then removed.