Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.

Abstract: Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.

Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.

Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

Abstract: A semiconductor device 100 includes: a semiconductor substrate 10 of silicon carbide of a first conductivity type; a silicon carbide epitaxial layer 20 of the first conductivity type, which has been grown on the principal surface 10a of the substrate 10; well regions 22 of a second conductivity type, which form parts of the silicon carbide epitaxial layer 20; and source regions 24 of the first conductivity type, which form respective parts of the well regions 22. A channel epitaxial layer 30 of silicon carbide has been grown over the well regions 22 and source regions 24 of the silicon carbide epitaxial layer 20. A portion of the channel epitaxial layer 30 that is located over the well regions 22 functions as a channel region 40. And a dopant of the first conductivity type has been implanted into the other portions 33 and 35 of the channel epitaxial layer 30 except the channel region 40.

Abstract: A field effect transistor includes: a channel layer 103 containing GaN or InGaN; a first electron-supplying layer 104 disposed over the channel layer 103 and containing InxAlyGa1-x-yN (0?x<1, 0<y<1, 0<x+y<1); a first etch stop layer 105 disposed over the first electron-supplying layer 104 and containing indium aluminum nitride (InAlN); and a second electron-supplying layer 106 provided over the first etch stop layer 105 and containing InaAlbGa1-a-bN (0?a<1, 0<b<1, 0<a+b<1). A first recess 111, which extends through the second electron-supplying layer 106 and the first etch stop layer 105 and having a bottom surface constituted of a section of the first electron-supplying layer 104, is provided in the second electron-supplying layer 106 and the first etch stop layer 105. A gate electrode 109 covers the bottom surface of the first recess 111 and is disposed in the first recess 111.

Abstract: A semiconductor device (10) comprises a substrate (11), a semiconductor layer (12), an insulation film (13), a protective film (15), a source electrode (21), a drain electrode (22), a gate electrode (23). The semiconductor device (10) comprises a protective film (15) formed so as to cover at least an upper surface of the insulation film (13). This enables preventing aluminum contained in the source electrode (21) and the drain electrode (22) from reacting with material contained in the insulation film (13). Accordingly, the increase of the resistance of the electrode and the increase of current collapse are prevented. Accordingly, the semiconductor device (10) has a satisfactory electric performance characteristics.

Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.

Abstract: A compound semiconductor device includes a compound semiconductor laminated structure; a source electrode, a drain electrode, and a gate electrode formed over the compound semiconductor laminated structure; a first protective film formed over the compound semiconductor laminated structure between the source electrode and the gate electrode and including silicon; and a second protective film formed over the compound semiconductor laminated structure between the drain electrode and the gate electrode and including more silicon than the first protective film.

Abstract: In a high voltage junction field effect transistor, a first well (11) of a first conductivity type is formed in a substrate (10) of a second conductivity type. A source (14) and a drain (15) which are each of the first conductivity type are formed in the first well. A gate (16) of the second conductivity type is arranged in a second well (12) of the second conductivity type, wherein the second well is of the retrograde type. The source, gate and drain are spaced apart from one another by field oxide regions (13a to 13d). Field plates (17a, 17b) extend over the field oxide (13a, 13b) from the gate (16) in the direction of source and drain.

Abstract: By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with extremely shallow PN junctions may be formed on the basis of pre-amorphization implantation processes while substantially avoiding any undue side effects typically obtained in conventional techniques due to stacking faults.

Abstract: Silicon-on-insulator JFET (SOI JFET) having a fully depleted body and fabrication methods therefor. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time). The devices and techniques include a fully-depleted body SOI-JFET, with improved switching characteristic over partially-depleted SOI JFET or bulk silicon devices. In one example, by tuning the thickness of the silicon containing layer of the SOI substrate, the body region of the JFET can be fully depleted during the OFF-state thus offering the performance benefits of suppressed leakage current. Additionally, improved AC performance (e.g., faster switching time) is achieved.

Abstract: Junction field-effect transistors (JFETs) having insulator-isolated source/drain regions and fabrication methods therefor are disclosed here. In SOI JFETs and bulk silicon JFETs having junction isolated source and drain regions from the body region, the junction leakage current is one of the leakage components of the off-state leakage current and consequently limits the on-off switching performance. In particular, for short-channel devices (for example, sub-100 nm and/or sub-65 nm devices), the leakage currents are especially pronounced. The techniques herein introduced include JFET with an insulating spacer such that the source and drain regions are insulator isolated from the body region. In one embodiment, the source and drain regions of the transistor are insulator isolated by silicon dioxide thus reducing the source-drain to body junction leakage current and improved on-off performance.

Abstract: A method for fabricating a junction field effect transistor includes the steps of the type I semiconductor at the base thereof being doped with the type II semiconductor to form a type II well with a hole; then, a drive-in process of the type II semiconductor is performed to allow the implant dosage of the type II well getting less gradually from the surroundings of the hole toward the center of the hole; and finally, the gate, the source and the drain of the junction field effect transistor being formed successively on the type II well. The implant dosage at the hole, which is acted as a channel, is determined in accordance with the preset size of the hole during the type II well being formed such that it is capable being compatible with the output voltages of different junction field effect transistors to achieve the purpose of the adjustment of the pinch-off voltage of the junction field effect transistor without the need of the mask and the manufacturing process.

Abstract: A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one buried region of a second conductivity type is formed in the semiconductor body and at least a surface region of the second conductivity type is formed at the first surface of the semiconductor body, wherein the buried region and the surface region are formed such that they are spaced apart from each other. The buried region is formed by deep implantation of a first dopant of the second conductivity type.

Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Abstract: A memory cell (FIG. 6A) compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory cell includes a first junction field effect transistor (600) having a first conductivity type. A second junction field effect transistor (602) having a second conductivity type is coupled to the first junction field effect transistor. An access transistor (610) is coupled to the first and second junction field effect transistors.

Abstract: A circuit 32 is provided comprising a first diffusion region 34 and a parallel second diffusion region 36. A sequence of N gate layers 40, 42, 46 is provided with a first and an Nth of these gate layers covering different respective ones of the diffusion regions 34, 36 whilst the middle (N-2) gate layers 42 cover both diffusion regions 34, 36. A bridging conductor 64 connects the first gate layer 40 and the Nth gate layer 46. In some embodiments, the second diffusion region is provided as two second diffusion sub-regions 68, 70 having a diffusion region gap 74 therebetween and electrically connected via a jumper connector 42. A first gate layer 76 which forms a gate electrode with a first diffusion region 66 can extend through this diffusion region gap 74 not forming a gate electrode therewith and facilitating use of a collinear bridging conductor 82 to connect to the Nth gate layer 80.

Abstract: According to one embodiment of the present invention, a method of forming a semiconductor device is provided, the method including: forming a substrate; forming a first gate on the substrate; forming a mask layer on the substrate, the mask layer including a first window covering an area within which the first gate is formed so that the first gate divides the substrate exposed by the first window into a first region and a second region; and doping the exposed substrate using rays inclined with respect to the substrate top surface, where the position of the first gate with respect to a border of the first window is chosen such that the inclined doping rays impinge more on the first region than on the second region.

Abstract: A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.

Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of silicide. The second connection region is in ohmic contact with the drain region and formed of silicide. The third connection region in ohmic contact with the gate region.

Abstract: A process for manufacturing a Junction Field-Effect Transistor, comprises doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region. The process continues by implanting impurities of a second conductivity type into said well region to form a channel region, and by implanting impurities of the first conductivity type in said well region to form a back gate region. The process continues by forming a trench to expose at least one sidewall of said channel region, wherein the trench extends far enough along the sidewall to expose at least a portion of said back gate region. The process continues by depositing polysilicon to fill said trench along the at least one sidewall of said channel region and at least a portion of said back gate region, wherein at least a portion of the polysilicon will form a gate contact. The polysilicon is then doped with impurities of a first conductivity type.

Abstract: A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise a semiconductor material formed over and in contact with the first diffusion region and the second diffusion region. A portion of the first conductive line in contact with the first diffusion region is doped to an opposite conductivity type as the first diffusion region. At least a second conductive line comprising a semiconductor material is formed in parallel with the first conductive line and over and in contact with the first diffusion region and the second diffusion region. A portion of the second conductive line can be in contact with the first diffusion region and doped to a same conductivity type as the first diffusion region.

Abstract: A method for fabricating a semiconductor device comprises depositing a first layer of oxide on at least a portion of a channel of a transistor. The method further comprises depositing a layer of nitride on the first layer of oxide and etching at least a portion of the layer of nitride to the first layer of oxide. The method further comprises depositing a second layer of oxide and planarizing the oxide to expose at least a portion of the layer of nitride. The method further comprises stripping at least a portion of the layer of nitride to create one or more notches and removing at least a portion of the first layer of oxide. The method further comprises depositing a layer of polysilicon, wherein at least a portion of the layer of polysilicon is deposited into at least one of the one or more notches.

Abstract: A double-gate semiconductor device provides a high breakdown voltage allowing for a large excursion of the output voltage that is useful for power applications. The double-gate semiconductor device may be considered a double-gate device including a MOS gate and a junction gate, in which the bias of the junction gate may be a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. Because an individual junction gate has an intrinsically high breakdown voltage, the breakdown voltage of the double-gate semiconductor device is greater than the breakdown voltage of an individual MOS gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices.

Abstract: In a semiconductor device having a first MIS transistor on a semiconductor substrate, the first MIS transistor includes a p-type semiconductor layer, a first gate insulating film, a first gate electrode, a first sidewall insulating film including at least a first sidewall, an n-type extension diffusion layer, and an n-type impurity diffusion layer. The first sidewall is not formed at the side faces of the first gate electrode on the p-type semiconductor layer. An insulating film having tensile stress is formed on the semiconductor substrate so as to cover the first MIS transistor.

Abstract: This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages.

Abstract: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

Abstract: A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region.

Abstract: A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region.

Abstract: A junction field effect transistor comprises a semiconductor wafer having a (110) and/or (100) surface orientation. A source region and a drain region are formed on the semiconductor wafer. A channel region of a p-conductivity type is formed between the source region and the drain region. The channel region is oriented along a <110> and/or <100> direction of the semiconductor wafer.

Abstract: A process for manufacturing a Junction Field-Effect Transistor, comprises doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region. The process continues by implanting impurities of a second conductivity type into said well region to form a channel region, and by implanting impurities of the first conductivity type in said well region to form a back gate region. The process continues by forming a trench to expose at least one sidewall of said channel region, wherein the trench extends far enough along the sidewall to expose at least a portion of said back gate region. The process continues by depositing polysilicon to fill said trench along the at least one sidewall of said channel region and at least a portion of said back gate region, wherein at least a portion of the polysilicon will form a gate contact. The polysilicon is then doped with impurities of a first conductivity type.

Abstract: An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.

Abstract: A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one buried region of a second conductivity type is formed in the semiconductor body and at least a surface region of the second conductivity type is formed at the first surface of the semiconductor body, wherein the buried region and the surface region are formed such that they are spaced apart from each other. The buried region is formed by deep implantation of a first dopant of the second conductivity type.

Abstract: A ED-HEMT structure includes a buffer layer (4) including a doped layer (18), a channel layer (6), a barrier layer (8), and a second doped layer (20). An enhancement mode HEMT gate (12) is formed in a via extending through the second doped layer (20) and a depletion mode HEMT structure is formed over the second doped layer (20). The layer sequence allows the formation of both enhancement and depletion mode HEMTs in the same structure with good properties.

Abstract: A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), including the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon substrate; etching the insulation oxide layer until the P-type silicon substrate is exposed so as to form a bit line contact hole on the drain; implanting arsenic ions into the P-type silicon substrate via the bit line contact hole to form an arsenic bit line contact window; and implanting phosphorus ions into the P-type silicon substrate via the bit line contact hole to form a phosphorus bit line contact window below the arsenic bit line contact window. In this way, a concentration gradient of N-type ions can be reduced at the bit line contact window, and further a PN junction leakage current can be reduced, thus lowing the power consumption of the DRAM when the DRAM is used for a low power consumption product.

Abstract: A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate.

Abstract: An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.

Abstract: A junction field effect transistor includes a substrate and a well region on the substrate. A channel region lies in the well region. A source region lies in the channel region. A drain region lies in the channel region and apart from the source region. A gate region is isolated from the source, drain, and channel regions. The gate region is in contact with a portion of the well region.

Abstract: A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region.

Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.

Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

Abstract: An isolation region is provided around a sense part. The isolation region is provided to have a depth that suppresses spread of a region with an uneven current distribution, which occurs at a peripheral edge of the sense part. Thus, in the sense part, an influence of the region with the uneven current distribution can be suppressed. Since the current distribution can be set more even throughout the sense part, the on-resistance in the sense part can be set closer to its designed value. Thus, a current ratio corresponding to a cell ratio can be obtained as designed. Consequently, current detection accuracy is improved.

Abstract: A multi-finger transistor and method of manufacturing the same are provided. The multi-finger transistor includes two active regions, a multi-finger gate, a plurality of source regions and a plurality of drain regions. The two active regions are defined in a unit cell of a substrate. The multi-finger gate includes a plurality of gate fingers formed in the two active regions and a gate connector between the two active regions. The gate connector connects the gate fingers to each other. The source regions are formed in first portions of the two active regions adjacent to the gate fingers. The drain regions are formed in second portions of the two active regions adjacent to the gate fingers.

Abstract: A transistor for a phase change memory device includes a semiconductor substrate in which active regions are delimited by an isolation structure. A groove is defined on a surface of a gate forming area of each active region. Portions of the isolation structure, which are adjacent to the gate forming area of the active region, are recessed to expose side faces of the gate forming area of the active region. A gate is formed on the gate forming area of the active region over the gate forming area grooves and exposed side faces thereof as well as the recessed portions of the isolation structure. Junction areas are then formed in the active region on both sides of the gate to complete the transistor of a phase change memory device.

Abstract: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.

Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).