Abstract: A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10?5 [Pa] or less.

Abstract: Accordingly, the present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A substrate which has a conductive layer disposed thereon is provided and the conductive layer has an oxide layer with an exposed surface. The exposed surface of the oxide layer contacts a solution of an organic surface active compound in an organic solvent to form a protective layer of the organic surface active compound over the oxide layer. The protective layer has a thickness of from about 0.5 nm to about 5 nm and ranges therebetween depending on a chemical structure of the surface active compound.

Abstract: A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.

Abstract: The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed.

Abstract: A semiconductor printed circuit board assembly (PCBA) and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of dielectric substrate placed on the core layer. A second layer of dielectric substrate is placed on the lower surface of the core layer of CIC. The layers are laminated together. Blind vias are laser drilled into the layers of dielectric substrate. The partially completed PCBA is subjected to a reactive ion etch (RIE) plasma as a first step to clean blind vias in the PCBA. After the plasma etch, an acidic etchant liquid solution is used on the blind vias. Pre-plating cleaning of blind vias removes a majority of oxides from the blind vias. Seed copper layers are then applied to the PCBA, followed by a layer of copper plating that can be etched to meet the requirements of the PCBA.

Abstract: An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.

Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.

Abstract: Transparent electrodes are manufactured. In accordance with various example embodiments, a transparent electrode is manufactured by generating a solution including a composite material having nanotubes and a conjugated polymer, in which the nanotubes constitute a majority of the composite material by weight. The conjugated polymer is used to disperse the nanotubes in the solution, and the solution is coated onto a substrate to form an electrode including a network of the carbon nanotubes.

Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.

Abstract: A structure and method of forming pillar bumps with controllable shape and size are provided, which use polishing planarization technology to eliminate shape difference among pillar bumps on a wafer and die, thus yield the pillar bumps with design shape and size.

Abstract: The RTD device of the present invention is comprised of a semiconductor substrate and a substantially thin conductive metal layer disposed upon the semiconductor substrate, wherein the conductive metal has a substantially linear temperature-resistance relationship. The conductive layer is etched into a convoluted RTD pattern, which consequently increases the overall resistance and minimizes the overall mass of the RTD assembly. A contact glass cover and a conductive metal-glass frit are placed over the RTD assembly to hermetically seal the RTD. The resultant structure can be “upside-down” mounted onto a header or a flat shim so that the bottom surface of the semiconductor substrate is exposed to the external environment, thus shielding the RTD from external forces. The resultant structure is a low mass, highly conductive, leadless, and hermetically sealed RTD that accurately measures the temperature of liquids and gases and maintains fast response time in high temperatures and harsh environments.

Abstract: A semiconductor device is disclosed wherein a tin diffusion inhibiting layer is provided above the land of a wiring line, and a solder ball is provided above the tin diffusion inhibiting layer. Thus, even when this semiconductor device is, for example, a power supply IC which deals with a high current, the presence of the tin diffusion inhibiting layer makes it possible to more inhibit the diffusion of tin in the solder ball into the wiring line.

Abstract: A surface-mounted electronic component including balls bonded to its front surface and, on the front surface, a protective resin layer having a thickness smaller than the ball height, wherein grooves extend in the resin layer between balls of the chip.

Abstract: There is provided an anode for an organic electronic device.

Abstract: Apparatuses and methods for diverting a flow of a liquid precursor during flow stabilization and plasma stabilization stages during PECVD processes are effective at eliminating particle defects in PECVD films deposited using a liquid precursor.

Abstract: In the present invention, to keep the conductive paste from flowing, an organic layer is formed on the substrate, following which the conductive paste is printed and fired. An electrode could be formed with a method comprising steps of: applying an organic paste onto one side of a substrate so as to form an organic layer; applying a conductive paste onto the organic layer; and firing the conductive paste so as to form an electrode and burn off the organic layer.

Abstract: A method for manufacturing a semiconductor device includes forming a first opening in a substrate to expose an interconnect structure, forming a seed film on the substrate, forming a first projecting electrode buried inside the first opening protruding outward from the substrate, forming a first metal film on the first projecting electrode, attaching a first supporting substrate to the substrate with a first adhesion layer, forming a second opening in the substrate to expose the interconnect structure, forming a second projecting electrode buried inside the second opening and protruding outward from the substrate, forming a second metal film on the second projecting electrode, attaching a second supporting substrate to the substrate with a second adhesion layer, removing the first supporting substrate, the first adhesion layer, and an exposed part of the seed film, removing the second supporting substrate and the second adhesion layer, and cutting the substrate into the plurality of chips.

Abstract: Methods are provided herein for forming metal oxide thin films by atomic layer deposition. The metal oxide thin films can be deposited at high temperatures such that the thin film is crystalline as deposited. The metal oxide thin films can be used, for example, as dielectric oxides in transistors, flash devices, capacitors, integrated circuits, and other semiconductor applications.

Abstract: A method for manufacturing a semiconductor device includes forming an electrode pad in a surface layer of an insulating layer; disposing a conductive particle, of which at least a portion of the surface is coated with a thermoplastic resin, over the electrode pad; and fixing the conductive particle over the electrode pad using the resin, by heating the resin to soften the resin, and then cooling and solidifying the resin after the conductive particle and the electrode pad are electrically connected to each other, to form the conductive particle as an external connection terminal.

Abstract: A method of fabricating a semiconductor device includes: forming a semiconductor chip portion having an electrode on a main surface of a wafer; forming a first resist pattern having a first opening on the electrode; filling the first opening with a first electrically conductive material, thereby forming an electrically conductive post; removing the first resist pattern after said forming of the electrically conductive post; forming an interlayer dielectric film having a second opening positioned on the electrically conductive post; and forming an electrically conductive redistribution layer extending from an upper surface of the electrically conductive post over an upper surface of the interlayer dielectric film.

Abstract: There is provided a package substrate capable of controlling the degree of warpage thereof by improving the composition and formation of a post terminal and a method of fabricating the same. The package substrate includes a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a separation barrier layer provided on the conductive pad inside the opening and formed to be higher than the upper surface of the insulating layer along the side walls thereof; a post terminal provided on the separation barrier layer; and a solder bump provided on the post terminal.

Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.

Abstract: A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.

Abstract: A wiring substrate includes an insulating layer, a wiring layer buried in the insulating layer, and a connection pad connected to the wiring layer via a via conductor provided in the insulating layer and in which at least a part is buried in an outer surface side of the insulating layer, wherein the connection pad includes a first metal layer (a first copper layer) arranged on the outer surface side, an intermediate metal layer (a nickel layer) arranged on a surface of an inner layer side of the first metal layer, and a second metal layer (a second copper layer) arranged on a surface of an inner layer side of the intermediate metal layer, and a hardness of the intermediate metal layer is higher than a hardness of the first metal layer and the second metal layer.

Abstract: Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.

Abstract: A thin-film solar module contacted on one side includes a support layer, a photoactive absorber layer and at least one dopant layer deposited over a surface area of at least one side of the absorber layer so as to form a thin-film packet that is divided into thin-film solar cell areas by insulating separating trenches. The thin-film solar module includes first and second contact systems. The first contact system includes contacts connected by an outer contact layer. The second contact system consists of an inner contact layer covering a side of the solar cell areas that face away from the support layer so as to separately discharge excess charge carriers generated by incident light in the absorber layer. The second contact system includes structures that surround and electrically insulate the contacts, which extend through the inner contact layer from the outer contact layer.

Abstract: Provided is a method for manufacturing a semiconductor device including: an electrode formation step of forming an electrode on one surface of a semiconductor substrate; a through hole formation step of forming a through hole starting from a position on the other surface corresponding to the position of the electrode; a first insulating layer formation step of forming a first insulating layer on at least an inner circumferential surface, a periphery of an opening, and a bottom surface of the through hole; a modifying step of reforming a first portion of the first insulating layer formed on the bottom surface of the through hole; a modified region removal step of removing the modified region; and a conductive layer formation step of forming a conductive layer on the electrode exposed inside the through hole and on the first insulating layer such that the conductive layer is electrically connected with the electrode.

Abstract: Provided are a spacer capable of avoiding a poor connection due to the suction of solder when the clearance width between a soldered semiconductor device and a printed circuit board is made constant, and a manufacturing method for the spacer. The spacer includes an electrically insulating base member, and at least one solder guiding terminal. The base member has a bottom face, a top face and at least one side face, of which the bottom face and the top face are out of contact with each other whereas the side face contacts one or both the bottom face and the top face. The solder guiding terminal covers the bottom face partially, the top face partially, and the side face partially or wholly. A solder guiding face as the surface of a portion of the solder guiding terminal covering the side face is not normal to the bottom face.

Abstract: Methods and compositions for depositing metal films are disclosed herein. In general, the disclosed methods utilize precursor compounds comprising gold, silver, or copper. More specifically, the disclosed precursor compounds utilize pentadienyl ligands coupled to a metal to increase thermal stability. Furthermore, methods of depositing copper, gold, or silver are disclosed in conjunction with use of other precursors to deposit metal films. The methods and compositions may be used in a variety of deposition processes.

Abstract: Methods and compositions for preparing highly conductive electronic features are disclosed. When organoamine-stabilized silver nanoparticles are exposed to an alkaline composition, the resulting electronic feature is highly conductive. Such methods are particularly advantageous when applied to aged silver nanoparticle compositions.

Abstract: A method of processing a substrate that displays out-gassing when placed in a vacuum comprises placing the substrate in a vacuum and performing an out-gassing treatment by heating the substrate to a temperature T1 and removing gaseous contamination emitted from the substrate until the out-gassing rate is determined by the diffusion of the substrate's contamination and thus essentially a steady state has been established. Afterwards, the temperature is lowered to a temperature T2 at which the diffusion rate of the substrate's contamination is lower than at T1. The substrate is further processed at said temperature T2 until the substrate has been covered with a film comprising a metal.

Abstract: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: With reference to a direction perpendicular to a direction of forming electrodes to which a voltage can be applied, fine structures are each arranged within ±5 degrees at a substantially even interval, and a semiconductor element is formed by using the fine structures. On an insulating substrate, at least two electrodes are arranged at a predetermined interval, and there are formed one or more fine structure arranging regions, each of which is formed by a unit of the two electrodes. A semiconductor element electrode is made in contact with the plurality of the fine structures, each having two ends in contact with the two electrodes and a length in a longitudinal direction of a nano order to a micron order, and arranged within ±5 degrees with reference to the direction perpendicular to the direction of forming the electrodes.

Abstract: A layer to be etched is first formed in a substrate. Then, a mask pattern is formed over the layer to be etched. Then, the layer to be etched is wet-etched using the mask pattern as a mask. In the procedure of performing wet etching, the substrate is dipped into an etching bath with the mask pattern downward.

Abstract: This invention provides a silver thick film paste composition comprising a silver powder comprising silver particles, each said silver particle comprising silver components 100-2000 nm long, 20-100 nm wide and 20-100 nm thick assembled to form a spherically-shaped, open-structured particle, wherein the d50 particle size is from about 2.5 ?m to about 6 ?m. There is also provided a method of making a semiconductor device, and in particular a solar cell, using the silver thick film paste composition to form a front side electrode.

Abstract: Provided are a schottky diode having an appropriate low breakdown voltage to be used in a radio frequency identification (RFID) tag and a method for fabricating the same. The schottky diode includes a silicon substrate having a structure in which an N-type well is formed on a P-type substrate, an insulating layer surrounding a circumference of the N-type well so as to electrically separate the N-type well from the P-type substrate, an N+ doping layer partly formed in a portion of a region of an upper surface of the N-type well, an N? doping layer partly formed in the other portion of a region of the upper surface of the N-type well, a cathode formed on the N+ doping layer, and an anode formed on the N? doping layer.

Abstract: A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess.

Abstract: A method for fabricating a hollow nanotube structure is disclosed. The method includes the steps of providing a substrate, developing a plurality of nanowires on the substrate with a predetermined size on the seed layer at relatively low temperature by a hydro-thermal growth method, forming an outer covering layer on the surfaces of the nanowires, selectively etching an upper end of the outer coating layer to expose an upper end of the nanowires and removing the nanowires to remain the hollow outer coating layer to form a plurality of hollow nanotubes. The method can simplify the nanotube manufacturing process, increase the dimension precision of the nanotubes and enhance the photoelectric properties of micro-electro-mechanical elements.

Abstract: A system, method and apparatus is capable of producing layers of various materials stacked on one another on a substrate without exposing the substrate to the pressure and contaminants of ambient air until the stack is complete. In one aspect, the stack of layers can include both an insulative layer of one or more insulative films, and a conductive metal layer of one or more conductive metal layer films. In another aspect, a bias signal of positive and negative voltage pulses may be applied to a target of a deposition chamber to facilitate deposition of the target material in a suitable fashion. In yet another aspect, one or more of the deposition chambers may have associated therewith a pump which combines a turbomolecular pump and a cryogenic pump to generate an ultra high vacuum in that chamber. Other features are described and claimed.

Abstract: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.

Abstract: The invention relates to a method for connecting a precious metal surface to a polymer, wherein a layer made of 20% to 40% gold and 80% to 60% silver is deposited on a substrate and the silver is subsequently selectively removed in order to produce a nanoporous gold layer. A fluid polymer is applied to the gold layer and cured.

Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Abstract: An adhesion layer and a supporting substrate are provided on the entire surface of the first surface side of a substrate with a metal seed film provided on the first surface side of the substrate. After the removal of the adhesion layer and the supporting substrate provided on the first surface of the substrate, an exposed part of the metal seed film is removed. After this, a plurality of semiconductor chips is stacked and first reflow is performed to the semiconductor chips.

Abstract: In sophisticated semiconductor devices, the electromigration performance of copper metal lines at the top interface thereof may be enhanced by forming a copper alloy that is locally restricted to the interface. To this end, an appropriate alloy-forming species, such as aluminum, may be provided on the basis of a non-masked deposition process and may be subsequently removed by a non-masked etch process, wherein the characteristic of the resulting alloy may be adjusted during an intermediate heat treatment.

Abstract: It was found out that when radicals generated by plasma are fed to a treatment chamber via a plurality of holes (111) formed on a partition plate which separates a plasma-forming chamber (108) from the treatment chamber, and the radicals are mixed with a treatment gas which is separately fed to the treatment chamber, the excitation energy of the radicals is suppressed and thereby the substrate surface treatment at high Si-selectivity becomes possible, which makes it possible to conduct the surface treatment of removing native oxide film and organic matter without deteriorating the flatness of the substrate surface. The radicals in the plasma are fed to the treatment chamber via radical-passing holes (111) of a plasma-confinement electrode plate (110) for plasma separation, the treatment gas is fed to the treatment chamber (121) to be mixed with the radicals in the treatment chamber, and then the substrate surface is cleaned by the mixed atmosphere of the radicals and the treatment gas.

Abstract: Provided is a technology capable of improving the reliability of a semiconductor device using a SiOC film as an interlayer film. In the invention, by forming an interlayer film from a SiOC film having a Si—CH3 bond/Si—O bond ratio less than 2.50% or having a strength ratio determined by the FT-IR of a Si—OH bond to a SiO—O bond exceeding 0.0007, a strength ratio of a SiH bond to a SiO—O bond at a wavelength of 2230 cm?1 exceeding 0.0050 and a strength ratio of a Si—H bond to a SiO—O bond at a wavelength of 2170 cm?1 exceeding 0.0067, the interlayer film has a relative dielectric constant of to 3 or less, and owing to suppression of lowering in hardness or elastic modulus, has improved mechanical strength.

Abstract: The present invention discloses a MEMS device with guard ring, and a method for making the MEMS device. The MEMS device comprises a bond pad and a sidewall surrounding and connecting with the bond pad, characterized in that the sidewall forms a guard ring by an etch-resistive material.

Abstract: A method of forming an inorganic silazane-based dielectric film includes: introducing a gas constituted by Si and H and a gas constituted by N and optionally H into a reaction chamber where an object is placed; controlling a temperature of the object at ?50° C. to 50° C.; and depositing by plasma reaction a film constituted by Si, N, and H containing inorganic silazane bonds.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: A TiN film is formed to have a predetermined thickness on a semiconductor wafer by heating the semiconductor wafer at a film formation temperature within a process container and performing a cycle including a first step and a second step at least once. The first step is arranged to supply a TiCl4 gas and a NH3 gas to form a film of TiN by CVD. The second step is arranged to stop the TiCl4 gas and supply the NH3 gas. In film formation, the semiconductor wafer is set at a temperature of less than 450° C. and the process container is set to have therein a total pressure of more than 100 Pa. The NH3 gas is set to have a partial pressure of 30 Pa or less within the process container in the first step.