Abstract: A module (100) is described having a semiconductor chip (1) which has at least one contact pad (2). A first dielectric layer (3), which contains a fluorocarbon compound, as well as a first wiring layer (4) are applied to the semiconductor chip (1).

Abstract: A substrate with an embedded passive element and methods for manufacturing the same are provided, wherein the substrate includes an interlayer circuit board having a first conductive circuit, a dielectric layer, a first electrode, a second electrode, and a second conductive circuit. The dielectric layer formed on the interlayer circuit board has a first recess and a second recess for respectively accommodating the first electrode and the second electrode. The embedded passive element is formed by the first electrode, the second electrode, and the dielectric layer between the first electrode and the second electrode. The second conductive circuit electrically connects the first electrode and the second electrode.

Abstract: A power MOSFET wafer level chip-scale packaging method is disclosed. The method includes the steps of electroless plating a wafer backside and a plurality of contact pads on a wafer front side and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies. In an alternative embodiment, the method includes the steps of providing a permanent protective layer on a wafer backside, electroless plating a plurality of contact pads on a wafer front side, and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies.

Abstract: A method of forming a contact plug in a semiconductor device includes the steps of forming a plurality of select lines and a plurality of word lines on a semiconductor substrate; forming a first etching stop layer on the select lines and the word lines; forming a second etching stop layer on the first etching stop layer; forming an insulating layer on the second etching stop layer; removing the insulating layer placed between the select lines, the second etching stop layer and the first etching stop layer to form a contact hole through which a portion of the semiconductor substrate is exposed; and filling the contact hole with conductive material to form a contact plug, and so the nitride layer is thinly formed and the high dielectric layer is then formed to form the etching stop layer. Due to the above, a layer stress caused by the nitride layer can be minimized, and it is possible to resolve a problem of exposing the semiconductor substrate caused by a damage of the etching stop layer.

Abstract: Disclosed is a method of manufacturing an alignment key of a semiconductor device. According to an embodiment, the method includes forming an insulating layer on a semiconductor substrate on which a cell region and a scribe line are defined, forming a photoresist pattern on the insulating layer and etching the insulating layer using the photoresist pattern as an etch mask so as to form a contact hole on the cell region and a mark hole on the scribe line, depositing a metal layer in the contact hole and the mark hole, and planarizing the metal layer so as to form a contact and an alignment mark. The mark hole can be the same size as the contact hole. In addition, the mark hole can be formed in plurality on the scribe line.

Abstract: A semiconductor device and a fabricating method thereof are provided. A first device having a photodiode cell can be disposed adjacent to a second device having a transistor, and a connection electrode can electrically connect the first device and the second device.

Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.

Abstract: An integrated circuit die includes one or more tubular-shaped conductive bumps disposed on one side thereof. The tubular-shaped bumps may comprise copper, and may be used for input/output (I/O) signaling. The die may also include solid bumps for I/O and/or power delivery. The tubular-shaped bumps are relatively more compliant than the solid bumps, and may alleviate the effects of thermally induced stresses. Other embodiments are described and may be claimed.

Abstract: A semiconductor fabrication method or process is provided for fabricating an integrated circuit (IC) originally having an Al backend design using a Cu BEOL fabrication process. The method converts the Al backend design to a Cu backend design without redesigning the IC for Cu BEOL fabrication process, and uses the resultant Cu design to fabricate the IC using Cu BEOL fabrication process. The Al-Cu conversion first determines layer construction of the Al design, and then matches metal resistances of the Al design with metal resistances of a Cu design, matches intra-metal capacitances of the Al design with intra-metal capacitances of the Cu design, and matches inter-metal capacitance of the Al design with inter-metal capacitances of the Cu design.

Abstract: A semiconductor device fabrication method by which the thermal stability of nickel silicide can be improved. Nickel (or a nickel alloy) is formed over a semiconductor substrate on which a gate region, a source region, and a drain region are formed. Dinickel silicide is formed by performing a first annealing step, followed by a selective etching step. By performing a plasma treatment step, plasma which contains hydrogen ions is generated and the hydrogen ions are implanted in the dinickel silicide or the gate region, the source region, and the drain region under the dinickel silicide. The dinickel silicide is phase-transformed into nickel silicide by performing a second annealing step.

Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.

Abstract: Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.

Abstract: Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n+ silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300° C. or less.

Abstract: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Abstract: An apparatus for chemical vapor deposition includes a reaction chamber providing a predetermined sealed space, a reaction gas supply unit for supplying a first reaction gas into the reaction chamber and a reaction gas supply line formed by operatively connecting the reaction gas supply unit and the reaction chamber. The reaction gas supply line allows the first reaction gas to flow through. The apparatus further includes a raw material supply unit for supplying at least one liquid raw material for generating a second reaction gas to be mixed with the first reaction gas supplied through the reaction gas supply line, a liquid raw material supply line allowing the at least one liquid raw material, which is supplied from the raw material supply unit, to flow into the reaction gas supply line, an injector for injecting the at least one liquid raw material to be vaporized at a portion where the liquid raw material supply line is connected to the reaction gas supply line.

Abstract: A method of depositing a ruthenium(Ru) thin film on a substrate in a reaction chamber, includes: (i) supplying a gas of a ruthenium precursor into the reaction chamber so that the gas of the ruthenium precursor is adsorbed onto the substrate, wherein the ruthenium precursor a ruthenium complex contains a non-cyclic dienyl; (ii) supplying an excited reducing gas into the reaction chamber to activate the ruthenium precursor adsorbed onto the substrate; and (iii) repeating steps (i) and (ii), thereby forming a ruthenium thin film on the substrate.

Abstract: Example embodiments may provide a wafer type probe card, a method of fabricating a wafer type probe card, and/or a semiconductor test apparatus having the wafer type probe card. The wafer type probe card may include a semiconductor and a plurality of probing chips. The semiconductor substrate may include a plurality of probing area each including a first surface and/or a second surface opposite to the first surface. Each of the plurality of probing chips may include a plurality of conductive first pads arranged in the first surface of each of the plurality of probing areas and/or a plurality of conductive second pads arranged in the second surface of each the plurality of probing chips to be respectively connected to the first pads.

Abstract: A manufacturing method of a display panel for an LCD includes forming a gate line on a flexible insulation substrate, depositing a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer and forming a data line and a drain electrode on the semiconductor layer and the gate insulating layer. The forming the semiconductor layer may be performed by PECVD at about 100° C. to about 180° C., the gate insulating layer may have a thickness of about 2000 ? to about 5500. The method may further include performing hydrogen plasma treatment on the gate insulating layer after the depositing the gate insulating layer and annealing the substrate having the plurality of thin films after the forming the data line and the drain electrode. The insulation substrate may include PES.

Abstract: A light-absorbing layer is selectively formed over an insulating surface, an insulating layer is formed over the insulating surface and the light-absorbing layer, the insulating surface, the light-absorbing layer, and the insulating layer are irradiated with laser light to selectively remove only the insulating layer above the light-absorbing layer in an irradiated region of the insulating layer so that an opening reaching the light-absorbing layer is formed in the insulating layer, and a conductive film is formed in the opening so as to be in contact with the light-absorbing layer. By forming the conductive film in the opening so as to be in contact with the exposed light-absorbing layer, the conductive film can be electrically connected to the light-absorbing layer with the insulating layer interposed therebetween.

Abstract: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.

Abstract: A method of forming copper metal lines capable of improving surface coatability without forming overhangs of a diffusion barrier film for preventing diffusion of copper in an upper portion of a hole and preventing formation of a copper void is disclosed. The method includes coating a lower layer on a substrate, coating an interlayer insulating film to cover the lower layer, partially and selectively etching the interlayer insulating film to form a trench and a hole such that the lower layer is partially exposed by the hole, and forming diffusion barrier films for preventing diffusion of copper on the interlayer insulating film having the trench and the hole and on the lower layer partially exposed by the hole, wherein the step of forming diffusion barrier films includes forming a first diffusion barrier film for preventing diffusion of copper which is made of a tungsten nitride film and forming a second diffusion barrier film for preventing diffusion of copper which is made of tungsten.

Abstract: Provided is a method for manufacturing a semiconductor device. In the method, photoresist patterns having a first width are formed on a semiconductor substrate, and the semiconductor substrate is etched using the photoresist patterns as a mask to form a semiconductor protrusion portion. An oxide layer is formed on an entire surface of the semiconductor substrate including the semiconductor protrusion portion. Subsequently, the semiconductor protrusion portion is removed to form a trench surrounded by the oxide layer. After that, blanket-etching is performed on the trench to leave only a portion of the oxide layer formed around the trench. Metal is deposited on an entire surface of the semiconductor substrate including the oxide layer, and the oxide layer is removed to form a metal line.

Abstract: Provided are methods of manufacturing a semiconductor device. Some embodiments of such methods may include forming a preliminary gate pattern on a substrate. The preliminary gate pattern may include silicon. Methods may include forming an insulation layer pattern on the substrate after forming the preliminary gate pattern. The insulation layer pattern exposes an upper face of the preliminary gate pattern. Methods may include forming a metal layer on the upper face of the preliminary gate pattern via an electroless plating process. Methods may include forming a gate pattern including a metal silicide from a reaction between the preliminary gate pattern and the metal layer by performing a heat treatment process.

Abstract: A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-distribution wiring layer including a wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape and connected to the other end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface with a contour crossing an upper contour of the post electrode mounting portion at more than two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.

Abstract: Disclosed are a metal interconnection structure of a semiconductor device and a method for manufacturing the same. The structure includes an upper interlayer dielectric layer pattern including fluorine (F), an upper metal interconnection in the upper interlayer dielectric layer pattern and connecting with a lower metal interconnection formed in a lower interlayer dielectric layer pattern. The lower interlayer dielectric layer pattern can include a barrier pattern provided below the upper interlayer dielectric layer pattern to inhibit diffusion of F, an adhesion layer pattern below the barrier layer pattern, and a silicon-oxy-carbide (SiOC) layer pattern below the adhesion layer pattern. In order to inhibit F from penetrating into a neighboring interlayer dielectric layer, the barrier layer can include boron (B), which can combine with F, thereby inhibiting diffusion of the F. Accordingly, the increase of the dielectric constant of an SiOC layer due to diffusion of F is inhibited.

Abstract: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.

Abstract: A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.

Abstract: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).

Abstract: Provided are a schottky diode having an appropriate low breakdown voltage to be used in a radio frequency identification (RFID) tag and a method for fabricating the same. The schottky diode includes a silicon substrate having a structure in which an N-type well is formed on a P-type substrate, an insulating layer surrounding a circumference of the N-type well so as to electrically separate the N-type well from the P-type substrate, an N+ doping layer partly formed in a portion of a region of an upper surface of the N-type well, an N? doping layer partly formed in the other portion of a region of the upper surface of the N-type well, a cathode formed on the N+ doping layer, and an anode formed on the N? doping layer.

Abstract: A nickel-based germanide contact includes a processing material that inhibits agglomeration of nickel-based germanide during processing to form the contact as well as during post-germanidation processes. The processing material is either in the form of a capping layer over the nickel layer or integrated into the nickel layer used to form the nickel-based contact. Reducing agglomeration improves electrical characteristics of the contact.

Abstract: An integrated sputtering method and reactor for copper or aluminum seed layers in which a plasma sputter reactor initially deposits a thin conformal layer onto a substrate including a high-aspect ratio hole subject to the formation of overhangs. After the seed deposition, the same sputter reactor is used to sputter etch the substrate with energetic light ions, especially helium, having an energy sufficiently low that it selectively etches the metallization to the heavier underlying barrier layer, for example, copper over tantalum or aluminum over titanium. An RF inductive coil generates the plasma during the sputtering etching while the target power is turned off. A final copper flash step deposits copper over the bare barrier field region before copper is electrochemically plated to fill the hole. The invention also includes a simultaneous sputter deposition and sputter etch, and an energetic ion processing of the copper seed sidewall.

Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.

Abstract: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.

Abstract: A portion to be melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Abstract: A polysilicon electrode layer (103) (a first electrode layer) is formed by forming a polysilicon film on a gate oxide film (102) on a silicon wafer (101). A tungsten layer (105) (a second electrode layer) is formed on this polysilicon electrode layer (103). In addition, a barrier layer (104) is formed on the polysilicon electrode layer (103) before the formation of the tungsten layer (105). Etching is then conducted using a silicon nitride layer (106) as the etching mask. Next, an oxide insulating film (107) is formed on an exposed surface of the polysilicon layer (103) by plasma oxidation wherein a process gas containing oxygen gas and hydrogen gas is used at a process temperature not less than 300° C. With this method, a selective oxidation of the polysilicon electrode layer (103) can be carried out without oxidizing the tungsten layer (105).

Abstract: A pattern film forming method includes a step of producing a transfer sheet in which a thin film is formed on a surface of a sheet-shaped material and a step of pressing the thin film against a pattern film formation surface of the substrate with a pressing member having convex portions corresponding to the pattern film from a reverse surface of the transfer sheet opposite to the thin film or a reverse surface of the substrate opposite to the pattern film formation surface to transfer the thin film to the substrate. A pattern film forming apparatus includes a sheet supply device, a pressing device and a substrate transport device. A high-definition pattern film having a desired pattern and a sharp edge can be formed with high productivity.

Abstract: A system of making a semiconductor device by forming bumps on pads of a test piece which is a semiconductor wafer or chip is disclosed. The system includes a mask substrate having holding holes; a supply portion for supplying a bump material including liquid, which contains a plurality of individual bump materials, to a target face of the mask substrate, so as to make the bump materials be fastened to the holding holes; a compressing plate, provided at the side of the other face of the mask substrate, which can optionally be made to contact with the other face; and a cleaning station for supplying a cleaning liquid or gas to the target face of the mask substrate. After the bump materials are fastened to the holding holes and the target face is cleaned, the bump materials are pressed, together with the mask substrate, onto the pads of the test piece.

Abstract: A method for producing a field effect transistor having source/drain electrodes of metal single-layer film firmly adhering to the gate insulating film is provided. The method includes forming a gate electrode on a support, forming a gate insulating film on the support and the gate electrode, performing treatment with a silane coupling agent on the surface of the gate insulating film, forming source/drain electrodes of metal single-layer film on the gate insulating film which has been treated with a silane coupling agent, and forming a channel-forming region of semiconductor layer on the gate insulating film held between the source/drain electrodes.

Abstract: A method for fabricating a capacitor is disclosed. First, a dielectric layer is disposed on a semiconductor substrate. Next, at least one dual damascene opening and at least one capacitor opening are formed in the dielectric layer. Next, a first conductive layer is disposed on the surface of the dielectric layer, the bottom and sidewall of the capacitor opening, and the dual damascene opening. Next, an insulating layer is formed on the first conductive layer and a second conductive layer is disposed on the insulating layer. Following that, a planarization process is performed to remove the second conductive layer, the insulating layer, and the first conductive layer on the dielectric surface for forming a capacitor and a dual damascene conductor.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.