Abstract: A method of manufacturing a filling of a gap region. The method includes the steps of: applying a carrier fluid and filler particles in a gap region between a first surface and a second surface; exposing the filler particles to a force field for driving the filler particles towards a preferred direction; and withholding the filler particles in a gap region by using a barrier element for forming a path of attached filler particles between the first surface and the second surface.

Abstract: A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.

Abstract: A method for manufacturing a semiconductor package includes the steps of forming first circuit patterns on an upper surface of a carrier substrate. Bumps are formed in recesses defined on the upper surface of the carrier substrate. An insulation layer is formed on the upper surface of the carrier substrate to cover the first circuit patterns. Second circuit patterns are formed on an upper surface of the insulation layer so as to be electrically connected with the first circuit patterns. The carrier substrate is then separated from the insulation layer.

Abstract: Apparatus for assembling a semiconductor device has a plate with body and a surface heatable to a controlled a temperature profile from location to location across the plate. Mesas at same temperature of plate protrude from the surface are configured to support a portion of the substrate. Movable capillaries have openings for blowing cooled gas onto selected locations of the assembly. At least one movable syringe movable has an opening for dispensing a polymer precursor.

Abstract: A semiconductor package is provided with a functionally necessary minimum number of components with which stress concentrated on specific solder bumps is reduced and ruptures of the bumps are prevented even when stress caused by physical bending or a difference in thermal expansion coefficient is applied to the package. The semiconductor package includes a tabular die and bonding pads arranged on a mounting surface of the die. A passivation layer and a protective film are provided on the mounting surface such that central areas of the bonding pads are open. Under-bump metals (UBMs) connected to the bonding pads are provided in the openings, and solder bumps are provided on the surfaces of the UBMs. The diameter of the UBMs provided at corners of the die is less than that of the UBM provided at the approximate center of the die so that the elastic modulus of the UBMs provided at the corners is small.

Abstract: A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Abstract: In one embodiment, a method of forming a semiconductor device package includes: (1) providing a carrier and a semiconductor device including an active surface; (2) forming a first redistribution structure including a first electrical interconnect extending laterally within the first structure and a plurality of second electrical interconnects extending vertically from a first surface of the first interconnect, each second interconnect including a lower surface adjacent to the first surface and an upper surface opposite the lower surface; (3) disposing the device on the carrier such that the active surface is adjacent to the carrier; (4) disposing the first structure on the carrier such that the upper surface of each second interconnect is adjacent to the carrier, and the second interconnects are positioned around the device; and (5) forming a second redistribution structure adjacent to the active surface, and including a third electrical interconnect extending laterally within the second structure.

Abstract: The present disclosure relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor element includes a base material and at least one through via structure. The base material has a first surface, a second surface, at least one groove and at least one foundation. The groove opens at the first surface, and the foundation is disposed on the first surface. The through via structure is disposed in the groove of the base material, and protrudes from the first surface of the base material. The foundation surrounds the through via structure. Whereby, the foundation increases the strength of the through via structure, and prevents the through via structure from cracking.

Abstract: A heat radiation package of the present invention includes a substrate in an upper surface side of which recess portion is provided, embedded wiring portion which is filled in the recess portion of the substrate and on which semiconductor element which generates a heat is mounted, and a heat sink connected to a lower surface side of the substrate. The substrate is made of silicon, ceramics, or insulating resin.

Abstract: The semiconductor device includes a wiring substrate having connection pads and a semiconductor chip having electrode pads. The semiconductor chip is mounted on the wiring substrate, and the electrode pads are connected to the connection pads via solder bumps. An underfill resin formed of a cured thermosetting resin is filled in a gap between the wiring substrate and the semiconductor chip. The underfill resin has a glass transition temperature which increases accompanying growth of crystal grains of the solder bumps.

Abstract: A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.

Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed.

Abstract: A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a result of moisture.

Abstract: A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin.

Abstract: An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall and under the overhang. The overhang prevents underfill material from extending over an upper surface of the IC chip. In another embodiment, a ball grid array (BGA) is first mounted to landing pads on a lower of two joined IC chip packages. Since the BGA is formed on the lower IC chip package first, the BGA acts as a dam for the underfill material thereon. The underfill material extends about the respective IC chip and surrounds a bottom portion of a plurality of solder elements of the BGA and at least a portion of respective landing pads thereof.

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract: A process for forming semiconductor packages includes partially etching a leadframe matrix, encapsulating it with mold compound, placing a semiconductor die in a leadframe unit and singulating the leadframe matrix. A system for forming semiconductor packages includes means for partially etching a leadframe matrix, means for encapsulating it with mold compound, means for placing a semiconductor die in a leadframe unit and means for singulating the leadframe matrix.

Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting a die over the substrate; mounting an interposer having a slot over the die; covering a first encapsulant over the die and the interposer, a central region of the interposer exposed from the first encapsulant; and forming a hole through the first encapsulant to expose a peripheral portion of the interposer.

Abstract: A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.

Abstract: A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly.

Abstract: A semiconductor element built-in device includes: a first substrate having a first pad thereon; a semiconductor element on the first substrate; a second substrate having a second pad thereon and mounted on the first substrate via a solder terminal having a solder coated thereon; a resin layer provided between the first substrate and the second substrate such that the solder terminal and the semiconductor element are embedded in the resin layer; and a dam provided at least partially around at least one of the first and second pads, the dam being configured to restrain the solder flowing from the solder terminal.

Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.

Abstract: An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.

Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.

Abstract: Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered.

Abstract: A method of through substrate via (TSV) die assembly includes positioning a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated to form a plurality of singulated stacked die assemblies.

Abstract: A fabrication method for a resin encapsulated semiconductor device includes the steps of: (1) die-bonding a semiconductor device to a first electrical connection metallic terminal of a wiring substrate; (2) electrically connecting an electrode of the semiconductor device and a second electrical connection metallic terminal of the wiring substrate via an electrical connector; (3) surface treating such an assembly by applying a solution to a surface of the assembly and baking the applied solution; and (4) transfer-molding an insulating encapsulating resin onto the surface-treated assembly.

Abstract: The electronic device, which allows inhibiting the breaking-away of the element from the frame member, even if the temperature change of the electronic device is repeated, and the process for manufacturing the electronic device, are achieved. An electronic device includes a photo-sensitive element formed in a wafer, a frame member installed on the wafer to surround a functional unit, and an encapsulating resin layer filling a circumference of the frame member.

Abstract: A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the second surface, and substrate pads on the second surface, adjacent to the opening. Bond pads of the semiconductor die are aligned with the opening through the substrate. Intermediate conductive elements, such as bond wires, extend from bond pads of the semiconductor die, through the opening, to substrate pads on the opposite, second surface of the substrate. An encapsulant, which fills the opening and covers the intermediate conductive elements, protrudes beyond a plane in which the second surface of the substrate is located.

Abstract: The method for producing a circuit substrate of the present invention is characterized in that the circuit substrate is produced using as sheet a circuit substrate sheet including an uncured layer a part of which, the part being other than a part at which a circuit chip is disposed, is selectively curable before or after disposal of said circuit chip, wherein the uncured layer has a softness that enables embedding of the circuit chip in the circuit substrate sheet upon pressing the circuit chip that has been disposed on a surface of the uncured layer. According to the method for producing the circuit substrate of the present invention, the circuit chip can be embedded inwards with high accuracy, and the circuit substrate can be produced easily with high accuracy.

Abstract: In a method for transferring at least one of power and ground signal between a die and a package base of a semiconductor device, a connector is formed there between. The connector, which is disposed above the die attached to the package base, includes a center pad electrically coupled to the die by a plurality of conductive bumps and a finger extending outward from the center pad towards the package base. The finger is electrically coupled to the package base by a conductive pad. A plurality of bond wires are formed to electrically couple the package base and the die. A resistance of a conductive path via the connector is much less than a resistance of a conductive path via any one of the plurality of bond wires to facilitate an efficient transfer of the at least one of power and ground signal.

Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire.

Abstract: An integrated circuit package system is provided including forming a wafer having a back side and an active side, forming a recess in the wafer from the back side, forming a cover in the recess, and singulating the wafer at the recess filled with the cover.

Abstract: A disclosed semiconductor device includes a wiring board, a semiconductor element mounted on a principal surface of the wiring board with flip chip mounting, a first conductive pattern formed on the principal surface along at least an edge portion of the semiconductor element, a second conductive pattern formed on the principal surface along the first conductive pattern and away from the first conductive pattern, a passive element bridging between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board, and a resin layer filling a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board.

Abstract: An optical detector includes a detector surface operable to receive light, a depleted field region coupled to the underside of the detector surface, a charge collection node underlying the depleted field region, an active pixel area that includes the portion of the depleted field region above the charge collection node and below the detector surface, and two or more guard regions coupled to the underside of the detector surface and outside of the active pixel area. The depleted field region includes an intrinsic or a near-intrinsic material. The charge collection node has a first width, and the guard regions are separated by a second width that is greater than the first width of the charge collection node. The guard regions are operable to prevent crosstalk to an adjacent optical detector.

Abstract: The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Abstract: A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.

Abstract: A method for detecting soft errors in an integrated circuit (IC) due to transient-particle emission, the IC comprising at least one chip and a substrate includes mixing an epoxy with a radioactive source to form a hot underfill (HUF); underfilling the chip with the HUF; sealing the underfilled chip; measuring a radioactivity of the HUF at an edge of the chip; measuring the radioactivity of the HUF on a test coupon; testing the IC for soft errors by determining a current radioactivity of the HUF at the time of testing based on the measured radioactivity; and after the expiration of a radioactive decay period of the radioactive source, using the IC in a computing device by a user.

Abstract: The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing each other; ejecting a gas (9a) from a gas generation source (1) included in the first electronic component (2) by heating the first electronic component (2) and the solder resin composition; and inducing the flow of the solder powder (5a) in the solder resin composition (6) by inducing convection of the gas (9a) in the solder resin composition (6), and electrically connecting the connecting terminals (3) and the electrode terminals (7) by self-assembly on the connecting terminals (3) and the electrode terminals (7).

Abstract: Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.

Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the remelt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; placing an integrated circuit device, having an external connector, adjacent to and electrically isolated from the lead; mounting an integrated circuit over the lead and the integrated circuit device with the integrated circuit electrically isolated from the integrated circuit device; and forming a package encapsulation, having an encapsulation base, over the lead, the integrated circuit, and the integrated circuit device with the lead and the external connector exposed from the encapsulation base.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: A high frequency flip chip package substrate of a polymer is a one-layer structure packaged by a high frequency flip chip package process to overcome the shortcomings of a conventional two-layer structure packaged by the high frequency flip chip package process. The conventional structure not only incurs additional insertion loss and return loss in its high frequency characteristic, but also brings out a reliability issue. Thus, the manufacturing process of a ceramic substrate in the conventional structure still has the disadvantages of a poor yield rate and a high cost.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect over the base circuit assembly, the inner interconnect on the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and the outer interconnect.

Abstract: Semiconductor-on-diamond devices and methods for making such devices are provided. One such method may include depositing a semiconductor layer on a semiconductor substrate, depositing an adynamic diamond layer on the semiconductor layer opposite the semiconductor substrate, and coupling a support substrate to the adynamic diamond layer opposite the semiconductor layer to support the adynamic layer.

Abstract: An electronic component having an encapsulation which has at least two double layers is described. In addition, a method for producing an electronic component in which a layer sequence is encapsulated is described.

Abstract: Lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between the input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper.

Abstract: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.