Abstract: A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a paddle, an inner post adjacent to the paddle, a jumper pad, and an outer post, with the jumper pad between the inner post and the outer post; mounting an integrated circuit over a paddle first side, the paddle first side co-planar with the outer post; connecting a first jumper interconnect between the integrated circuit and the jumper pad; connecting a second jumper interconnect between the jumper pad and the outer post; and forming an encapsulation over paddle, the integrated circuit, the first jumper interconnect, the jumper pad, and the second jumper interconnect.

Abstract: A method includes providing a carrier; applying a dielectric layer to the carrier; applying a metal layer to the dielectric layer; placing a first semiconductor chip on the metal layer with contact pads of the first semiconductor chip facing the metal layer; covering the first semiconductor chip with an encapsulation material; and removing the carrier.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base panel having a first side with a cavity and a second side opposite the first side; connecting an integrated circuit device and the first side; applying a resist mask having an opening on the second side, the opening offset from the cavity; forming a bump contact in the opening; applying an encapsulation in the cavity over the integrated circuit device and the first side; and forming a package lead by removing a portion of the base panel under the cavity, a flared tip of the package lead intersecting a base side of the encapsulation.

Abstract: A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material, and further including a method of producing the semiconductor device. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu6Sn5 content greater than a eutectic content.

Abstract: A QFN package includes a chip-mounting base; electrically connecting pads disposed around the periphery of the chip-mounting base, the bottom surfaces of the chip-mounting base and the electrically connecting pads being covered by a copper layer; a chip mounted on the top surface of the chip-mounting base; bonding wires electrically connecting to the chip and the electrically connecting pads; an encapsulant encapsulating the chip-mounting base, the electrically connecting pads, the chip and the bonding wires while exposing the copper layer; and a dielectric layer formed on the bottom surfaces of the encapsulant and the copper layer and having a plurality of openings exposing a portion of the copper layer. The copper layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the interface between the chip-mounting base, the electrically connecting pads and the dielectric layer, thereby avoiding solder extrusion and enhancing product yield.

Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.

Abstract: A metal post chip connecting device without soldering materials is revealed, primarily comprising a chip and a substrate. A plurality of metal pillars are disposed on and extruded from a surface of the chip where each metal pillar has an end surface and two corresponding parallel sidewalls. The substrate has an upper surface and a plurality of bonding pads disposed on the upper surface where each bonding pad has a concaved bottom surface and two corresponding concaved sidewalls. The chip is bonded onto the upper surface of the substrate through heat, pressure, and ultrasonic power so that the end surfaces of the metal pillars self-solder to the concaved bottom surfaces and two parallel sidewalls of the metal pillars partially self-solder to two concaved sidewalls to form U-shape cross-sections of metal bonding between the metal pillars and the bonding pads.

Abstract: A microwave circuit package having a ball grid array, BGA, soldered on to a planar major surface of a metal housing of the package for the electrical connection of the ports of the microwave circuit through RF signal paths to an adjacent electrical device. Each of the RF signal paths comprises a pin electrically connected to a respective port of the microwave circuit package, projecting normally through an opening in the said major surface from which it is electrically insulated, and soldered to a ball of the BGA; the pin and the surrounding balls of the BGA, which are soldered to the metal housing, constituting a coaxial RF signal path.

Abstract: A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate-such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder.

Abstract: A package device and a fabrication method thereof comprises providing a plurality of package units each having a plurality of penetrated holes; stacking the plurality of package units in a manner such that the penetrated holes of the plurality of package units are aligned; filling a conductive material into the plurality of penetrated holes substantially, so as to electrically connect the plurality of package units through the conductive material; and disposing a plurality of solder balls on the bottom of the conductive material filling the plurality of penetrated holes, and connecting the plurality of solder balls with the conductive material electrically.

Abstract: Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.

Abstract: A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterised in that it comprises the step of patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface. Also the method has the step of applying a compound to one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material. These correspond to the one or more channels on the surface and allow the passage of waste material away from the joint area to the outer edge of the surface.

Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: A surface preparation method for improved adhesion in an electronic package system. The method of improving adhesion in the electronic package system includes depositing a passivation layer on a bonding surface and roughening at least a portion of the passivation layer. A coating material is deposited on the passivation layer. The bonding surface can be part of a semiconductor or package substrate. The roughening process can be performed by a chemical or mechanical process. In another embodiment, an electronic package system includes a bonding surface of a semiconductor or package substrate. A passivation layer is deposited on the bonding surface and a portion of the passivation layer is roughened for improved adhesion. A coating material is deposited on the roughened portion of the passivation layer.

Abstract: Apparatus and methods for providing a robust solder connection in a flip chip arrangement using lead free solder are disclosed. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of a material comprising one of nickel, nickel alloys, palladium, platinum, cobalt, silver, gold, and alloys of these is formed on the exterior surface of the copper column. A lead free solder connector is disposed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. A thermal reflow is performed. The metal finish may be of nickel, nickel alloy and nickel based materials. Following a thermal reflow, the solder connection formed between the copper terminal column and the metal finish solder pad is less than 0.5 wt. %.

Abstract: Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first dielectric layer over a first conductor structure of a semiconductor chip and forming a first opening in the first dielectric layer to expose at least a portion of the conductor structure. The first opening defines an interior wall that includes plural protrusions. A solder structure is coupled to the first conductor structure such that a portion of the solder structure is positioned in the first opening.

Abstract: A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

Abstract: A mounting structure for a semiconductor device includes a stepwise stress buffer layer under a likewise stepwise UBM structure.

Abstract: Disclosed in this specification is a lead-free soldering alloy made of gold, tin and indium. The tin is present in a concentration of 17.5% to 20.5%, the indium is present in a concentration of 2.0% to 6.0% and the balance is gold and the alloy has a melting point between 290° C. and 340° C. and preferably between 300° C. and 340° C. The soldering alloy is particularly useful for hermetically sealing semiconductor devices since the melting temperature is sufficiently high to permit post-seal heating and sufficiently low to allow sealing of the semiconductor without causing damage.

Abstract: A metallic interconnect structure (200) for connecting a gold bump (205) and a contact pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 ?m), which covers the copper pad. The nickel layer insures that the gold/tin intermetallics and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.

Abstract: A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.

Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.

Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.

Abstract: A semiconductor packaging system includes a semiconductor die and a solder pillar on a side of the semiconductor die extending outwardly from a side of the semiconductor die. The solder pillar electrically couples to an electrical contact of a packaging substrate, even when access to the electrical contact is limited by a mask.

Abstract: A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump.

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract: This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.

Abstract: Quad Flat No-Lead packaged devices are manufactured using two singulation operations with two different saw blades of varying widths with the first singulation operation using a wider saw blade than the second singulation operation. Between singulation operations, the exposed portions of the leads are plated with a solderable metal. By performing the second singulation operation within the first cut made by the first singulation, at least half of the exposed metal of the leads remains plated. Thus, better solder joints may be formed, which allows for simpler visual inspection.

Abstract: A treatment for a microelectronic device comprises a dicing tape (110) and a polymer composite film (120) having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50° Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.

Abstract: A fan-out wafer level package includes a semiconductor die with contact pads positioned on a top surface. A fan-in redistribution layer positioned over the die includes contact pads in electrical communication with the first contact pads of the die. A buffer layer positioned over the fan-in layer includes a plurality of vias, in electrical contact with the contact pads of the fan-in layer. A fan-in redistribution layer is positioned over the buffer layer and includes contact pads on a surface opposite the buffer layer, in electrical communication with the vias. The semiconductor die, fan-in layer, and buffer layer are encapsulated in a molding com-pound layer. Solder contacts, for electrically connecting the semiconductor device to a electronic circuit board, are positioned on contact pads of the fan-out layer. The buffer layer has a substantial thickness, to reduce and distribute shear stresses resulting from thermal mismatch of coefficients of thermal expansion of the semiconductor die and a circuit board.

Abstract: This document discusses, among other things, a semiconductor die package having a first and a second discrete components embedded into a dielectric substrate. An integrated circuit (IC) die is surface mounted on a first side of the dielectric substrate. The semiconductor die package includes a plurality of conductive regions on the second side of the dielectric substrate for mounting the semiconductor die package. A plurality of through hole vias couple the IC die to the first and second discrete components and the plurality of conductive regions.

Abstract: An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip.

Abstract: Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.

Abstract: A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material, and further including a method of producing the semiconductor device. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu6Sn5 content greater than a eutectic content.

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pads that horizontally overlap; and forming an interconnection between the device and the bond wire pad row.

Abstract: A method of forming at least one bonding structure may be provided. A ball may be formed on the front end of a wire outside a capillary. The capillary may be moved downwardly to form a preliminary compressed ball on a first pad using the ball. The capillary may be moved upwardly to form a neck portion on the preliminary compressed ball using the preliminary compressed ball and the wire. The capillary may be moved obliquely and downwardly to form a compressed ball. The capillary may extend the wire from the compressed ball to a second pad.

Abstract: A first semiconductor element is mounted on a wiring board. A second semiconductor element having a portion projecting to an outer side of an outer periphery of the first semiconductor element is disposed on the first semiconductor element via an adhesive. The adhesive has a viscosity (?0.5 rpm) at a low-rotation speed in a range from 10 Pa·s to 150 Pa·s and a thixotropic ratio of 2 or higher expressed by a ratio (?0.5 rpm/?5 rpm) of the viscosity (?0.5 rpm) at the low-rotation speed to a viscosity (?5 rpm) at a high-rotation speed. The second semiconductor element is bonded onto the first semiconductor element while the adhesive is filled in a hollow portion between the projecting portion of the second semiconductor element and the wiring board.

Abstract: An apparatus for supplying electrical power to a movable member. The apparatus includes a fixed member, the movable member moving relative to the fixed member, a flexible wiring member having an end connected to the movable member and another end connected to the fixed member, configured to transmit the electrical power from the fixed member to the movable member, and a cooling member configured to cool the fixed member.

Abstract: A semiconductor chip according to the present invention includes a semiconductor substrate, a bump of a metal projecting from a surface of the semiconductor substrate, and an alloy film covering the entire surface of the bump, the alloy film being composed of an alloy of the metal of the bump and a second metal.

Abstract: Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection reliability. And to achieve the above objects, the semiconductor device has the solder bump which electrically connects a semiconductor chip and a package substrate, the under-filling resin with which it filled up between the semiconductor chip and the package substrate, and a solder ball which electrically connects a package substrate with the outside, and the solder bump's elastic modulus is made lower than the elastic modulus of a solder ball.

Abstract: A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.

Abstract: A column is coupled to a last metallization of a die and the column is mated to a mounting substrate with that aid of a solder. The column may have the solder attached thereto before mating to the mounting substrate and the mounting substrate may be a bare-board (no solder mask) during the mating process. The column has an aspect ratio between 0.75 and 10.

Abstract: A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members.

Abstract: Disclosed is a die mounting substrate, which includes a mounting substrate having a pad, a die having a terminal and surface-mounted on the mounting substrate, and a conductive paste bump formed on the pad or the terminal so as to connect the pad and the terminal to each other. When the die is connected and mounted on the mounting substrate using the conductive paste bump, shear stress is relieved thus preventing reliability from decreasing due to a difference in the coefficient of thermal expansion between the die and the mounting substrate, and also preventing the force of adhesion of the bump from decreasing due to the reduction in size of the pad of the mounting substrate.

Abstract: A method is described in which a contact hole to an interconnect in an insulating layer is fabricated. A barrier layer is subsequently applied. Afterward, a photoresist layer is applied, irradiated and developed. With the aid of a galvanic method, a copper contact is then produced in the contact hole. Either the barrier layer or an additional boundary electrode layer serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production.

Abstract: A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.