Abstract: A number of deep trench openings are formed in a semiconductor wafer to have substantially equal depths and no oxide undercut by forming a number of shallow trench openings, forming a mask structure in the shallow trench openings where the mask structure has a substantially planar top surface, forming a number of mask openings in the mask structure, and etching the semiconductor wafer through the mask openings to form the deep trench openings.

Abstract: A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.

Abstract: Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about 120 ? over the layer of porous aluminum oxide.

Abstract: A method of filling a trench comprises heating a semiconductor substrate having a trench formed therein and an oxide film formed at least on the sidewall of the trench and supplying an aminosilane gas to the surface of the substrate so as to form a seed layer on the semiconductor substrate, heating the semiconductor substrate having the seed layer formed thereon and supplying a monosilane gas to the surface of the seed layer so as to form a silicon film on the seed layer, filling the trench of the semiconductor substrate, which has the silicon film formed thereon, with a filling material that shrinks by burning, and burning the semiconductor substrate coated by the filling material filling the trench in an atmosphere containing water and/or a hydroxy group while changing the filling material into a silicon oxide and changing the silicon film and the seed layer into a silicon oxide.

Abstract: An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.

Abstract: A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, an liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.

Abstract: A method of forming semiconductor devices includes stacking an insulating layer and a polysilicon layer over a semiconductor substrate, forming a region where nitrogen (N) is scattered in a place adjacent to a surface of the polysilicon layer within the polysilicon layer using a plasma method, and depositing a doped polysilicon layer on the polysilicon layer including the region where nitrogen (N) is scattered.

Abstract: Disclosed are an element isolation structure of a semiconductor device and a method for forming the same, the method including preparing a semiconductor substrate having an inactive region and an active region defined thereon, forming a first hard mask on the semiconductor substrate, exposing the inactive region of the semiconductor substrate by patterning the first hard mask, forming a second hard mask on the entire surface of the semiconductor substrate including the first hard mask, forming a deep trench in the semiconductor substrate by patterning the second hard mask and the semiconductor substrate, removing the patterned second hard mask, forming a shallow trench overlapped with the deep trench by patterning the semiconductor substrate using the first hard mask as a mask, forming an insulation film on the entire surface of the substrate including the shallow trench and the deep trench, filling the shallow trench and the deep trench by forming an element isolation film on the insulation film, and forming

Abstract: By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements.

Abstract: Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.

Abstract: A method of forming an isolation layer in a semiconductor device is disclosed, by which breakdown voltage and PN junction leakage characteristics of the isolation layer are enhanced. Embodiments include depositing a pad nitride layer over a semiconductor substrate, reducing the thickness of the pad nitride layer by etching a portion of the pad nitride layer, forming a tetraethyl orthosilicate (TEOS) oxide layer over the remaining pad nitride layer, forming a trench by selectively removing the tetraethyl orthosilicate oxide layer and the pad nitride layer over an isolation area of the semiconductor substrate, depositing an high density plasma oxide layer over the substrate to fill the trench, and forming an isolation layer by planarizing the high density plasma oxide layer and the tetraethyl orthosilicate oxide layer.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

Abstract: A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device.

Abstract: A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.

Abstract: A semiconductor device includes an insulating layer and an undoped polysilicon layer that are stacked over a semiconductor substrate. The semiconductor substrate is exposed by removing the portions of the undoped polysilicon layer and the insulating layer. The trenches are formed by etching the exposed semiconductor substrate. Isolation layers are formed in the trenches, and a doped polysilicon layer is formed by implanting impurities into the undoped polysilicon layer.

Abstract: A method for fabricating an etching barrier includes forming wall bodies with a trench in between the wall bodies in a semiconductor substrate. An etching barrier is formed by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein one of two bottom edge portions of the trench is not covered by the deposition due to a shadow effect by upper portions of the wall bodies.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may include first and second active patterns. The second active patterns may protrude from the first active patterns. The semiconductor devices may also include a device isolation pattern between each of the first active patterns. The semiconductor devices may further include a sidewall mask on the first active patterns and the second active patterns. The semiconductor devices may additionally include a buried conductive pattern on the device isolation pattern.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.

Abstract: A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide.

Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Abstract: A nonvolatile semiconductor memory device includes a first insulating layer, charge storage layers, element isolation insulating films, and a second insulating layer formed on the charge storage layers and the element isolation insulating films and including a stacked structure of a first silicon nitride film, first silicon oxide film, intermediate insulating film and second silicon oxide film. The first silicon nitride film has a nitrogen concentration of not less than 21×1015 atoms/cm2. Each element isolation insulating film includes a high-temperature oxide film formed along lower side surfaces of the charge storage layers between the charge storage layers and a coating type insulating film. The first silicon nitride film is formed on an upper surface of the high-temperature oxide film in upper surfaces of the element isolation insulating films and not on the upper surface of the coating type insulating film.

Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

Abstract: A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.

Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.

Abstract: A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.

Abstract: The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like.

Abstract: A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects.

Abstract: The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper layer is reduced by making separate layers respectively serve as a mask during forming the hole in a semiconductor substrate, and a stopper during removing the insulating film filled in the hole.

Abstract: This invention relates to materials and processes for thin film deposition on solid substrates. Silica/alumina nanolaminates were deposited on heated substrates by the reaction of an aluminum-containing compound with a silanol. The nanolaminates have very uniform thickness and excellent step coverage in holes with aspect ratios over 40:1. The films are transparent and good electrical insulators. This invention also relates to materials and processes for producing improved porous dielectric materials used in the insulation of electrical conductors in microelectronic devices, particularly through materials and processes for producing semi-porous dielectric materials wherein surface porosity is significantly reduced or removed while internal porosity is preserved to maintain a desired low-k value for the overall dielectric material.

Abstract: The present invention provides a manufacturing method of a semiconductor device including: a step of forming a shallow trench on a semiconductor substrate; a step of forming an insulating layer in the shallow trench; and a step of forming a deep trench in the shallow trench, the deep trench penetrating through the insulating layer and being deeper than the shallow trench; wherein the step of forming the deep trench includes to form a first deep trench including an inner side face having a first taper angle with respect to the semiconductor substrate; and form a second deep trench including an inner side face having a second taper angle with respect to the semiconductor substrate, wherein the second taper angle is different from the first taper angle.

Abstract: A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic sources and drains.

Abstract: Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.

Abstract: An excessive metallic film on a device isolation region is prevented from contributing to silicidation in an end of a source-drain diffusion layer region to thereby form a silicide film with uniform film thickness. There are sequentially conducted a step of forming a device isolation region 3 in a substrate 1 including a silicon layer at least in a surface thereof and filling a first insulator in the device isolation region 3, a step of making height of an upper surface of the first insulator less than height of an upper surface of the substrate 1 and forming a sidewall film 10 on a sidewall of the device isolation region 3, and a step of depositing a metallic film 11 on the substrate 1 and then conducting silicidation through a thermal process.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: The invention relates to a method for manufacturing components on a mixed substrate. It comprises the following steps: —providing a substrate of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer between a supporting substrate and a thin layer, —forming in this substrate a plurality of trenches opening out at the free surface of the thin layer and extending over a depth such that it passes through the thin layer and the buried oxide layer, these primary trenches delimiting at least one island of the SeOI substrate, —forming a mask inside the primary trenches and as a layer covering the areas of the free surface of the thin layer located outside the islands, —proceeding with heat treatment for dissolving the buried oxide layer present at the island, so as to reduce the thickness thereof.

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

Abstract: An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate.

Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line contact hole obtained by etching the semiconductor substrate; a bit line contact plug having a smaller width than that of the bit line contact hole; and a bit line connected to the upper portion of the bit line contact plug, thereby preventing a short of the bit line contact plug and the storage node contact plug to improve characteristics of the semiconductor device.

Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. In an embodiment, an apparatus includes a substrate having a first surface and a second surface, the second surface being opposite the first surface; a first device and a second device overlying the substrate; and an isolation structure that extends through the substrate from the first surface to the second surface and between the first device and the second device.

Abstract: Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over fins and isolation materials and performing a multi-stage etching process to remove upper portions of the multi-layer structure and upper portions of isolation materials. Upper portions of the fins are exposed by removing the upper portions of the isolation materials via the multi-stage etching process. A stage of the multi-stage etching process removes an upper layer of the multi-layer structure and an upper portion of the isolation materials, and the stage can be terminated about at the same time when the upper surface of the underlying layer of the multi-layer structure is exposed.

Abstract: A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer and the substrate using the first photoresist pattern as a mask. Removing the first photoresist pattern. Filling the trench with a trench oxide layer. Planarizing the trench oxide layer. Forming an etch stop layer on and/or over the trench oxide layer. Forming a second photoresist pattern on and/or over the etch stop layer. Etching the etch stop layer and the trench oxide layer using the second photoresist pattern as an etch mask. Removing the second photoresist pattern and the etch stop layer.

Abstract: To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating fil

Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess.

Abstract: A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.

Abstract: A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the bottom of the trenches and to remove the material enclosed by the trench to form the large microchannels. A method of simultaneously forming large and small microchannels. A method of forming structures on the backside of the substrate around a microchannel to mate with another device.

Abstract: A semiconductor device with mini silicon-oxide-nitride-oxide-silicon (mini-SONOS) cell is disclosed. The semiconductor device includes: a semiconductor substrate; a shallow trench isolation (STI) embedded in the semiconductor substrate; a logic device partially overlapping the STI; and a SONOS cell formed in the overlapped region of the logic device and the STI.

Abstract: Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.

Abstract: An HDP-CVD process is described, including a deposition step conducted in an HDP-CVD chamber and a pre-heating step that is performed outside of the HDP-CVD chamber before the deposition step and pre-heats a wafer to a temperature higher than room temperature and required in the HDP-CVD process deposition step.