With Separation/delamination Along Ion Implanted Layer, E.g., "smart-cut", "unibond" (epo) Patents (Class 257/E21.568)
  • Patent number: 7915684
    Abstract: To provide a structure and a manufacturing method for efficiently forming a transistor to which tensile strain is preferably applied and a transistor to which compressive strain is preferably applied over the same substrate when stress is applied to a semiconductor layer in order to improve mobility of the transistors in a semiconductor device. Plural kinds of transistors which are separated from a single-crystal semiconductor substrate and include single-crystal semiconductor layers bonded to a substrate having an insulating surface with a bonding layer interposed therebetween are provided over the same substrate. One of the transistors uses a single-crystal semiconductor layer as an active layer, to which tensile strain is applied. The other transistors use single-crystal semiconductor layers as active layers, to which compressive strain using part of heat shrink generated by heat treatment of the base substrate after bonding is applied.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: March 29, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshifumi Tanada
  • Patent number: 7910455
    Abstract: The present invention relates to a method for producing an SOI wafer, having at least a step of a bonding heat treatment for increasing bonding strength by heat-treating a bonded wafer obtained by bonding a base wafer and a bond wafer, in which argon is ion-implanted from a surface of either the base wafer or the bond wafer at a dosage of 1×1015 atoms/cm2 or more at least before the bonding step, the surface ion-implanted with argon is used as a bonding surface in the bonding step, and an increase rate of temperature to a treatment temperature of the bonding heat treatment is 5° C./minute or higher. Thus the present invention provides a method for producing an SOI wafer facilitating the efficient production of an SOI wafer having in the neighborhood of a buried insulator layer thereof a polycrystalline silicon layer uniform in thickness introduced and having high gettering ability toward metal contaminations in the SOI layer by a simple and low-cost method.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: March 22, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno
  • Patent number: 7910456
    Abstract: An embodiment of a composite substrate member in accordance with the present invention has a handle substrate member derived from a plurality of nanoparticles in a fluid mixture, and a thickness of material transferred to the handle substrate member. The handle substrate member may be formed from a plurality of liquid layers, for example a thinner surface layer conveying specific properties to the donor/substrate interface, and a thicker support layer dispensed over the surface layer.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: March 22, 2011
    Assignee: Silicon Genesis Corporation
    Inventor: Harry Robert Kirk
  • Publication number: 20110065263
    Abstract: It is an object of the invention is to provide a method suitable for reprocessing a semiconductor substrate having favorable planarity. Another object of the invention is to manufacture a reprocessed semiconductor substrate by using the method suitable for reprocessing a semiconductor substrate having favorable planarity, and to manufacture an SOI substrate by using the reprocessed semiconductor substrate. A projecting portion of a semiconductor substrate is removed using a method capable of selectively removing a semiconductor region which is damaged by ion irradiation or the like. Further, an oxide film is formed on a surface of the semiconductor substrate when the semiconductor substrate is planarized by a polishing treatment typified by a CMP method, whereby the semiconductor substrate is evenly polished at a uniform rate. Moreover, a reprocessed semiconductor substrate is manufactured using the aforementioned method, and an SOI substrate is manufactured using the reprocessed semiconductor substrate.
    Type: Application
    Filed: August 19, 2010
    Publication date: March 17, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Ryota IMAHAYASHI, Hideto OHNUMA
  • Patent number: 7906408
    Abstract: Provided is a method of manufacturing a strained silicon-on-insulator (SSOI) substrate that can manufacture an SSOI substrate by separating a bonded substrate using a low temperature heat treatment. The manufacturing method includes: providing a substrate; growing silicon germanium (SiGe) on the substrate to thereby form a SiGe layer; growing silicon (Si) with a lattice constant less than a lattice constant of SiGe on the SiGe layer to thereby form a transformed Si layer; and implanting ions on the surface of the transformed Si layer, wherein, while growing of the SiGe layer, the SiGe layer is doped with impurity at a depth the ions are to be implanted. Accordingly, it is possible to manufacture a substrate with an excellent surface micro-roughness. Since a bonded substrate can be separated using low temperature heat treatment by interaction between implanted ions and impurity, it is possible to reduce manufacturing costs and facilitate an apparatus.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 15, 2011
    Assignee: Siltron Inc.
    Inventors: In Kyum Kim, Suk June Kang, Hyung Sang Yuk
  • Patent number: 7902038
    Abstract: The invention relates to a method for production of a detachable substrate, comprising a method step for the production of an interface by means of fixing, using molecular adhesion, one face of a layer on one face of a substrate, in which, before fixing, a treatment stage for at least one of said faces is provided, rendering the mechanical hold at the interface at such a controlled level to be compatible with a subsequent detachment.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: March 8, 2011
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Bernard Aspar, Hubert Moriceau, Olivier Rayssac, Bruno Ghyselen
  • Publication number: 20110053345
    Abstract: An object is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate. A semiconductor substrate is reprocessed in the following manner: etching treatment is performed on a semiconductor substrate in which a projection including a damaged semiconductor region and an insulating layer exists in a peripheral portion, whereby the insulating layer is removed; and etching treatment is performed on the semiconductor substrate with the use of a mixed solution including a substance that oxidizes a semiconductor material included in the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls oxidation speed of the semiconductor material and dissolution speed of the oxidized semiconductor material, whereby the damaged semiconductor region is selectively removed with a non-damaged semiconductor region left.
    Type: Application
    Filed: August 19, 2010
    Publication date: March 3, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Keitaro IMAI
  • Patent number: 7897443
    Abstract: The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed on an insulating substrate, the production method comprising the steps of: implanting a substance for separation into a single crystal semiconductor substrate, thereby forming a separation layer; transferring a part of the single crystal semiconductor substrate, separated at the separation layer, onto the insulating substrate, thereby forming the single crystal semiconductor layer; forming a hydrogen-containing layer on at least one side of the single crystal semiconductor layer; and diffusing hydrogen from the hydrogen-containing layer to the single crystal semiconductor layer.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: March 1, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masao Moriguchi, Yutaka Takafuji, Steven Roy Droes
  • Patent number: 7897476
    Abstract: To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOI substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eiji Higa, Yoji Nagano, Tatsuya Mizoi, Akihisa Shimomura
  • Publication number: 20110045654
    Abstract: In order to polish a layer of germanium (121), a first step of chemical-mechanical polishing of the surface (121a) of the germanium layer (121) is carried out with a first polishing solution having an acidic pH. The first polishing step is followed by a second step of chemical-mechanical polishing of the surface of the germanium layer (121) carried out with a second polishing solution having an alkaline pH.
    Type: Application
    Filed: June 9, 2009
    Publication date: February 24, 2011
    Inventors: Muriel Martinez, Pierre Bey
  • Publication number: 20110042693
    Abstract: A semiconductor device (10) includes a support substrate (14), an adhered device part (11) adhered to the support substrate (14), a multilayer device part (13) stacked on the adhered device part (11), and an adjacent device part (12) formed in a region adjacent to the adhered device part on the support substrate (14). The adhered device part (11), the multilayer device part (13), and the adjacent device part (12) are electrically connected to one another.
    Type: Application
    Filed: April 9, 2009
    Publication date: February 24, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei, Kazuo Nakagawa, Shin Matsumoto
  • Patent number: 7892861
    Abstract: The present invention provides improved methods for fabricating compound-material wafers, in particular a silicon on insulator type wafer. The improved methods lead to reduced numbers of deflects arising on or near the periphery of the wafers. In a first method, wafers are selected in dependence on edge roll off values determined at about 0.5-2.5 mm away from the edge of the wafer, where edge roll off values are determined in dependence on the second derivative of the wafer height profiles. In a second method, wafers selected according to the first method are further processed by bonding, forming a splitting layer, and detaching the two wafers at the splitting layer.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: February 22, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Ludovic Ecarnot, Willy Michel, Patrick Reynaud, Walter Schwarzenbach
  • Patent number: 7892948
    Abstract: The present invention provides a method for manufacturing an SOI wafer in which a thickness of an SOI layer is increased by growing an epitaxial layer on the SOI layer of the SOI wafer having an oxide film and the SOI layer formed on a base wafer, wherein the epitaxial growth is performed in such a manner that a reflectivity of a surface of the SOI wafer on which the epitaxial layer is grown in a wavelength region of a heating light at the start of the epitaxial growth falls within the range of 30% to 80%. As a result, in the method for manufacturing the SOI wafer in which a thickness of the SOI layer is increased by growing the epitaxial layer on the SOI layer of the SOI wafer having the oxide film and the SOI layer formed on the base wafer, a method for manufacturing a high-quality SOI wafer with less slip dislocation and others is provided.
    Type: Grant
    Filed: January 15, 2007
    Date of Patent: February 22, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Shinichiro Yagi
  • Publication number: 20110039395
    Abstract: To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.
    Type: Application
    Filed: October 22, 2010
    Publication date: February 17, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hideto OHNUMA, Kenichiro MAKINO, Yoichi IIKUBO, Masaharu NAGAI, Aiko SHIGA
  • Publication number: 20110027969
    Abstract: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having no oxide film wherein hydrogen ions are implanted into a wafer for active layer having no oxide film on its surface to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer.
    Type: Application
    Filed: October 12, 2010
    Publication date: February 3, 2011
    Applicant: SUMCO CORPORATION
    Inventors: Satoshi MURAKAMI, Nobuyuki Morimoto, Hideki Nishihata, Akihiko Endo
  • Patent number: 7879690
    Abstract: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: February 1, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Emmanuel Augendre, Thomas Ernst, Marek Kostrzewa, Hubert Moriceau
  • Patent number: 7879689
    Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel TFT and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: February 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoaki Moriwaka
  • Publication number: 20110014776
    Abstract: A method for easily manufacturing a transparent SOI substrate having: a main surface with a silicon film formed thereon; and a rough main surface located on a side opposite to a side where the silicon film is formed. A method for manufacturing transparent SOI substrate, having a silicon film formed on a first main surface of the transparent insulating substrate, while a second main surface of the transparent insulating substrate, an opposite to the first main surface, is roughened. The method includes at least the steps of: roughening the first main surface with an RMS surface roughness lower than 0.7 nm and the second main surface with an RMS surface roughness higher than the surface roughness of the first main surface to prepare the transparent insulating substrate; and forming the silicon film on the first main surface of the transparent insulating substrate.
    Type: Application
    Filed: April 1, 2009
    Publication date: January 20, 2011
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shoji Akiyama, Makoto Kawai, Atsuo Ito, Yoshihiro Kubota, Kouichi Tanaka, Yuji Tobisaka, Hiroshi Tamura
  • Publication number: 20110003461
    Abstract: An SOI substrate having a single crystal semiconductor layer with high surface planarity is manufactured. A semiconductor substrate is doped with hydrogen, whereby a damaged region which contains large quantity of hydrogen is formed. After a single crystal semiconductor substrate and a supporting substrate are bonded together, the semiconductor substrate is heated, whereby the single crystal semiconductor substrate is separated in the damaged region. While a heated high-purity nitrogen gas is sprayed on a separation plane of the single crystal semiconductor layer separated from the single crystal semiconductor substrate, laser beam irradiation is performed. By irradiation with a laser beam, the single crystal semiconductor layer is melted, whereby planarity of the surface of the single crystal semiconductor layer is improved and re-single-crystallization is performed.
    Type: Application
    Filed: September 15, 2010
    Publication date: January 6, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Patent number: 7863155
    Abstract: It is an object of the present invention to obtain a large-sized SOI substrate by providing a single-crystal silicon layer over a large-sized glass substrate in a large area. After a plurality of rectangular single-crystal semiconductor substrates each provided with a separation layer are aligned over a dummy substrate and both of the substrates are fixed with a low-temperature coagulant, the plurality of single-crystal semiconductor substrates are bonded to a support substrate; the temperature is raised up to a temperature, at which the low-temperature coagulant does not to have a bonding effect, so as to isolate the dummy substrate and the single-crystal semiconductor substrates; heat treatment is performed to separate part of the single-crystal semiconductor substrates, along a boundary of the respective separation layers; and single-crystal semiconductor layers are provided over the support substrate.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: January 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Publication number: 20100330778
    Abstract: The embrittlement layer and the semiconductor layer remaining on the periphery of the semiconductor substrate after separation are selectively removed using a mixed solution containing a substance functioning as an oxidizer for oxidizing a semiconductor, a substance dissolving an oxide of a semiconductor, and a substance functioning as a decelerator of oxidization of a semiconductor and dissolution of an oxide of a semiconductor. Note that the semiconductor film is separated from the semiconductor substrate along an embrittlement layer that is formed in the semiconductor substrate by implantation of an H+ ion generated from a hydrogen gas with use of an ion implantation apparatus.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 30, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kazuya Hanaoka
  • Publication number: 20100330779
    Abstract: A bond substrate is irradiated with accelerated ions to form an embrittled region in the bond substrate; an insulating layer is formed over a surface of the bond substrate or a base substrate; the bond substrate and the base substrate are bonded to each other with the insulating layer interposed therebetween; a region in which the bond substrate and the base substrate are not bonded to each other and which is closed by the bond substrate and the base substrate is formed in parts of the bond substrate and the base substrate; the bond substrate is separated at the embrittled region by heat treatment; and a semiconductor layer is formed over the base substrate.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Naoki OKUNO, Akihisa SHIMOMURA, Hajime TOKUNAGA
  • Publication number: 20100330777
    Abstract: Disclosed is a method for reprocessing a semiconductor substrate which is by-produced in manufacturing a silicon-on-insulator substrate. The method includes: forming an embrittlement layer in a single crystal semiconductor substrate; bonding the single crystal semiconductor substrate with a base substrate having an insulating surface; and separating the single crystal semiconductor substrate along the embrittlement layer to give a silicon-on-insulator substrate and a semiconductor substrate to be reprocessed. The above steps provide, in the peripheral portion on the semiconductor substrate, a projection comprising the embrittlement layer and a single crystal semiconductor layer over the embrittlement layer. The method is characterized by an etching step to selectively remove the projection without etching a portion where the projection is absent, which allows the semiconductor substrate to be reused for the production of another silicon-on-insulator substrate.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 30, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kazuya HANAOKA
  • Patent number: 7858430
    Abstract: In aspects of the present invention, a method is disclosed to form a lamina having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: December 28, 2010
    Assignee: Twin Creeks Technologies, Inc.
    Inventors: Mohamed M. Hilali, Christopher J. Petti, S. Brad Herner
  • Patent number: 7858494
    Abstract: Adhesion of particles due to static buildup during a laminated substrate manufacturing process is constrained, so as to reduce generation of a void or a blister in a lamination step and improve yield. A laminate 13 is formed by superimposing a first semiconductor substrate 11, which is to be an active layer, on a second semiconductor substrate 12, which is to be a supporting substrate, via an oxide film 11a. Electric resistance of either or both of the first and second semiconductor substrates 11 and 12 before superimposition is 0.005-0.2 ?cm.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: December 28, 2010
    Assignee: Sumco Corporation
    Inventors: Akihiko Endo, Hideki Nishihata, Nobuyuki Morimoto
  • Patent number: 7858431
    Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: December 28, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumito Isaka, Sho Kato, Koji Dairiki
  • Publication number: 20100323496
    Abstract: The invention relates to a process for manufacturing a composite substrate comprising bonding a first substrate (10) onto a second semi-conducting substrate (30), characterized in that it includes, before bonding, the formation of a bonding layer (20) between the first and the second substrate, the bonding layer (20) comprising a plurality of islands (21) distributed over the surface of the first substrate (10) in a determined pattern and separated from one another by regions (22) of a different type, which are distributed in a complementary pattern, wherein the islands (21) are formed via a plasma treatment of the material of the first substrate (10).
    Type: Application
    Filed: March 26, 2008
    Publication date: December 23, 2010
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Frederic Allibert, Sebastien Kerdiles
  • Publication number: 20100323497
    Abstract: A method of transferring a thin layer from a source substrate having a surface layer of a first material along a free surface thereof to a target substrate having at least one surface layer of a second material along a free surface thereof, where the first material differs from the second material, includes forming within the surface layer of the source substrate a weakened zone delimiting a thin layer with respect to the free surface, and assembling the free surface of the source substrate to the free surface of the target substrate in a stack of alternating layers comprising the first and second materials, so that there are, on either side of an interface formed by bringing the free surfaces into intimate contact. The cumulative thicknesses of the layers of the first material are substantially equal to the cumulative thickness of the layers of the second material, the layers having thicknesses at least equal to 50 microns and at least 1000 times the depth at which the weakened zone is formed.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 23, 2010
    Inventor: Franck Fournel
  • Patent number: 7855149
    Abstract: Provided may be a treatment method to remove defects created on the surface of a substrate, a method of fabricating an image sensor by using the treatment method, and an image sensor fabricated by the same. The treatment method may include providing a semiconductor substrate including a surface defect, providing a chemical solution to a surface of the semiconductor substrate, and removing the surface defect by consuming the surface of the semiconductor substrate and forming a chemical oxide layer on the semiconductor substrate.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: December 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi-Bum Kim, Hyun-Pil Noh
  • Patent number: 7855128
    Abstract: A method for fabricating a back-illuminated semiconductor imaging device on an ultra-thin semiconductor-on-insulator substrate (UTSOI) is disclosed. The UTSOI substrate is formed by providing a handle wafer comprising a mechanical substrate and an insulator layer substantially overlying the mechanical substrate. A donor wafer is provided. Hydrogen is implanted in the donor wafer to form a bubble layer. The donor wafer is doped with at least one dopant to form a doped layer proximal to the bubble layer. The handle wafer and the donor wafer are bonded between the insulator layer of the handle wafer and a surface of the donor wafer proximal to the doped layer to form a combined wafer having a portion substantially underlying the bubble layer. The portion of the combined wafer substantially underlying the bubble layer is removed so as to expose a seed layer. An epitaxial layer is grown substantially overlying the seed layer, wherein at least one dopant diffuse into the epitaxial layer.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: December 21, 2010
    Assignee: Sarnoff Corporation
    Inventors: Rui Zhu, Peter Alan Levine, Pradyumna Kumar Swain, Mahalingam Bhaskaran
  • Publication number: 20100314722
    Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.
    Type: Application
    Filed: February 19, 2009
    Publication date: December 16, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
  • Publication number: 20100317161
    Abstract: To provide a method for manufacturing an SOI substrate having a single crystal semiconductor layer having a small and uniform thickness over an insulating film. Further, time of adding hydrogen ions is reduced and time of manufacture per SOI substrate is reduced. A bond layer is formed over a surface of a first semiconductor wafer and a separation layer is formed below the bond layer by irradiating the first semiconductor wafer with H3+ ions by an ion doping apparatus. H3+ ions accelerated by high voltage are separated to be three H+ ions at a semiconductor wafer surface, and the H+ ions cannot enter deeply. Therefore, H+ ions are added into a shallower region in the semiconductor wafer at a higher concentration than the case of using a conventional ion implantation method.
    Type: Application
    Filed: August 24, 2010
    Publication date: December 16, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Akiharu MIYANAGA, Ko INADA, Yuji IWAKI
  • Patent number: 7851332
    Abstract: A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a substrate having an insulating surface, and a plurality of stacks over the substrate having an insulating surface. Each of the plurality of stacks includes a bonding layer over the substrate having an insulating surface, an insulating layer over the bonding layer, and a single crystal semiconductor layer over the insulating layer. The substrate having an insulating surface has a depression, and the depression is provided between one of the plurality of stacks and another adjacent one of the plurality of stacks.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: December 14, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Tetsuya Kakehata
  • Patent number: 7851330
    Abstract: Methods are disclosed for preparing a reconditioned donor substrate by providing a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and depositing an additional layer onto the opposite surface of the remainder substrate to increase its thickness and to form a reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: December 14, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Frederic Dupont
  • Publication number: 20100311221
    Abstract: Hydrogen ions are implanted to a surface (main surface) of the single crystal Si substrate 10 at a dosage of 1.5×1017 atoms/cm2 or higher to form the hydrogen ion implanted layer (ion-implanted damage layer) 11. As a result of the hydrogen ion implantation, the hydrogen ion implanted boundary 12 is formed. The single crystal Si substrate 10 and the low melting glass substrate 20 are bonded together. The bonded substrate is heated at relatively low temperature, 120° C. or higher and 250° C. or lower (below a melting point of the support substrate). Further, an external shock is applied to delaminate the Si crystal film along the hydrogen ion implanted boundary 12 of the single crystal Si substrate 10 out of the heat-treated bonded substrate. Then, the surface of the resultant silicon thin film 13 is polished to remove a damaged portion, so that a semiconductor substrate can be fabricated.
    Type: Application
    Filed: August 6, 2010
    Publication date: December 9, 2010
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Patent number: 7846817
    Abstract: It is an object of the present invention to manufacture a semiconductor element and an integrated circuit that have high performance over a large-sized substrate with high throughput and high productivity. When single crystal semiconductor layers are transferred from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers divided such that they have the size of semiconductor elements to be manufactured are transferred to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: December 7, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ikuko Kawamata, Yasuyuki Arai
  • Patent number: 7846818
    Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: December 7, 2010
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Publication number: 20100304507
    Abstract: The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm.
    Type: Application
    Filed: September 11, 2008
    Publication date: December 2, 2010
    Applicant: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Brigitte Soulier Bouchet, Sébastien Kerdiles, Walter Schwarzenbach
  • Publication number: 20100301455
    Abstract: A method for producing a bonded substrate having a Si1-xGex (0<x?1) film in which a larger than ever biaxial strain has been introduced. Specifically, the method involves at least the steps of: providing a donor wafer and a handle wafer having a thermal expansion coefficient lower than the donor wafer, implanting ions of any one or both of hydrogen and a noble gas into the donor wafer to form an ion-implanted layer, performing a plasma activation treatment on at least one of bonding surfaces of the donor wafer and the handle wafer, bonding the donor wafer to the handle wafer, splitting the donor wafer through application of a mechanical impact to the ion-implanted layer, performing a surface treatment on a split surface of the donor wafer, and epitaxially growing a Si1-xGex (0<x?1) film on the split surface to thus form a strained Si1-xGex (0<x?1) film on the bonded wafers.
    Type: Application
    Filed: November 27, 2008
    Publication date: December 2, 2010
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Shoji Akiyama
  • Publication number: 20100295105
    Abstract: A method for manufacturing a semiconductor device includes: an element portion formation step of forming an element portion on a base layer; a delaminating layer formation step of forming a delaminating layer in the base layer; a bonding step of bonding the base layer having the element portion to a substrate; and a separation step of separating and removing a portion of the base layer in the depth direction along the delaminating layer by heating the base layer bonded to the substrate. The method further includes, after the separation step, an ion implantation step of ion-implanting a p-type impurity element in the base layer for adjusting the impurity concentration of a p-type region of the element.
    Type: Application
    Filed: September 25, 2008
    Publication date: November 25, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumori Fukushima, Kazuhide Tomiyasu, Yutaka Takafuji, Kenshi Tada, Michiko Takei
  • Publication number: 20100297828
    Abstract: A method for fabricating a substrate of the semiconductor on insulator type by forming an epitaxial layer of semiconducting material on a donor substrate having oxygen precipitates with a density of less than 1010/cm3 or a mean size of less than 500 nm, forming an oxide layer on either a donor or receiver substrate, implanting atomic species in the donor substrate to form a weakened zone in the epitaxial layer, bonding the donor and receiver substrates together, with the oxide layer present at the bonding interface, fracturing the donor substrate in the weakened zone to transfer a layer of the donor substrate to the receiver substrate with the transferred layer including the epitaxial layer, and recycling the remainder of the donor substrate to form a receiver substrate for fabrication of a second semiconductor on insulator type substrate.
    Type: Application
    Filed: January 29, 2009
    Publication date: November 25, 2010
    Inventor: Christophe Maleville
  • Patent number: 7839001
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 23, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Giséle Rayssac, legal representative
  • Publication number: 20100291753
    Abstract: A single crystal semiconductor layer is formed over a substrate having an insulating surface by the following steps: forming an ion doped layer at a given depth from a surface of a single crystal semiconductor substrate; performing plasma treatment to the surface of the single crystal semiconductor substrate; forming an insulating layer on the single crystal semiconductor substrate to which the plasma treatment is performed; bonding the single crystal semiconductor substrate to the substrate having the insulating surface with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate using the ion doped layer as a separation surface. As a result, a semiconductor substrate in which a defect in an interface between the single crystal semiconductor layer and the insulating layer is reduced can be provided.
    Type: Application
    Filed: July 21, 2010
    Publication date: November 18, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tetsuya KAKEHATA, Kazutaka KURIKI
  • Publication number: 20100291755
    Abstract: An SOI substrate is manufactured by a method in which a first insulating film is formed over a first substrate over which a plurality of first single crystal semiconductor films is formed; the first insulating film is planarized; heat treatment is performed on a single crystal semiconductor substrate attached to the first insulating film; a second single crystal semiconductor film is formed; a third single crystal semiconductor film is formed using the first single crystal semiconductor films and the second single crystal semiconductor films as seed layers; a fragile layer is formed by introducing ions into the third single crystal semiconductor film; a second insulating film is formed over the third single crystal semiconductor film; heat treatment is performed on a second substrate superposed on the second insulating film; and a part of the third single crystal semiconductor film is fixed to the second substrate.
    Type: Application
    Filed: July 28, 2010
    Publication date: November 18, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Fumito ISAKA, Sho KATO, Kosei NEI, Ryu KOMATSU, Tatsuya MIZOI, Akihisa SHIMOMURA
  • Publication number: 20100291754
    Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masaki KOYAMA, Fumito ISAKA, Akihisa SHIMOMURA, Junpei MOMO
  • Patent number: 7833878
    Abstract: A hydrogen ion-implanted layer is formed on the surface side of a first substrate which is a single-crystal silicon substrate. At least one of the surface of a second substrate, which is a transparent insulating substrate, and the surface of the first substrate is subjected to surface activation treatment, and the two substrates are bonded together. The bonded substrate composed of the single-crystal Si substrate and the transparent insulating substrate thus obtained is mounted on a susceptor and is placed under an infrared lamp. Light having a wave number range including an Si—H bond absorption band is irradiated at the bonded substrate for a predetermined length of time to break the Si—H bonds localized within a “microbubble layer” in the hydrogen ion-implanted layer, thereby separating a silicon thin film layer.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: November 16, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Yuuji Tobisaka, Koichi Tanaka
  • Publication number: 20100283103
    Abstract: A method for manufacturing a semiconductor device includes: a first step of forming a base layer, which includes an element portion having a gate electrode and a flat interlayer insulating film formed so as to cover the gate electrode; a second step of ion implanting a delamination material into the base layer to form a delamination layer; a third step of bonding the base layer to a substrate; and a fourth step of separating and removing a part of the base layer along the delamination layer. An implantation depth of the delamination material in the gate electrode is substantially the same as that of the delamination material in the interlayer insulating film.
    Type: Application
    Filed: November 14, 2008
    Publication date: November 11, 2010
    Inventors: Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Masao Moriguchi, Yutaka Takafuji
  • Publication number: 20100283104
    Abstract: An element portion forming step includes an insulating film forming step of forming an insulating film on a surface of a base layer, a conductive layer forming step of uniformly forming a conductive layer on a surface of the insulating film, and an electrode forming step of patterning the conductive layer to form an electrode. A delamination layer forming step of ion implanting a delamination material into the base layer to form a delamination layer is performed before the electrode forming step.
    Type: Application
    Filed: November 25, 2008
    Publication date: November 11, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei, Kazuo Nakagawa, Shin Matsumoto
  • Patent number: 7829434
    Abstract: To provide a method for manufacturing an SOI substrate having a single crystal semiconductor layer having a small and uniform thickness over an insulating film. Further, time of adding hydrogen ions is reduced and time of manufacture per SOI substrate is reduced. A bond layer is formed over a surface of a first semiconductor wafer and a separation layer is formed below the bond layer by irradiating the first semiconductor wafer with H3+ ions by an ion doping apparatus. H3+ ions accelerated by high voltage are separated to be three H+ ions at a semiconductor wafer surface, and the H+ ions cannot enter deeply. Therefore, H+ ions are added into a shallower region in the semiconductor wafer at a higher concentration than the case of using a conventional ion implantation method.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: November 9, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd,
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Ko Inada, Yuji Iwaki
  • Patent number: 7829433
    Abstract: A manufacturing method of a semiconductor substrate is provided, in which a bonding strength can be increased even when a substrate having low heat resistant temperature, e.g., a glass substrate, is used. Heat treatment is conducted at a temperature higher than or equal to a strain point of a support substrate in an oxidation atmosphere containing halogen, so that a surface of a semiconductor substrate is covered with an insulating film. A separation layer is formed in the semiconductor substrate. A blocking layer is provided. Then, heat treatment is conducted in a state in which the semiconductor substrate and the support substrate are superposed with the silicon oxide film therebetween, at a temperature lower than or equal to the support substrate, so that a part of the semiconductor substrate is separated at the separation layer. In this manner, a single crystal semiconductor layer is formed on the support substrate.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: November 9, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki