With Separation/delamination Along Ion Implanted Layer, E.g., "smart-cut", "unibond" (epo) Patents (Class 257/E21.568)
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Publication number: 20110193201Abstract: The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate (1), an oxide layer (3) and a thin layer (2) of semiconducting material, according to which: 1) a mask is formed on said thin layer (2) so as to define exposed regions (20), on the surface of said layer, which are not covered by the mask; 2) heat treatment is applied so as to urge at least part of the oxygen of the oxide layer (3) to diffuse through the thin layer (2), leading to controlled removal of the oxide in the regions (30) of the oxide layer (3) corresponding to the desired pattern; characterized in that said carrier substrate (1) and thin layer (2) are arranged relative to each other so that their crystal lattices, in a plane parallel to their interface (I), together form an angle called a “twist angle” of no more than 1°, and in a plane perpendicular to their interface (I) an angle called a “tilt angle” of no more than 1°, and in that a thType: ApplicationFiled: October 9, 2009Publication date: August 11, 2011Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Oleg Kononchuk, Eric Guiot, Fabrice Gritti, Didier Landru, Christelle Veytizou
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Publication number: 20110193190Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: April 18, 2011Publication date: August 11, 2011Inventors: Nishant Sinha, Gurtej S. Sandhu, John Smythe
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Publication number: 20110193149Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.Type: ApplicationFiled: April 25, 2011Publication date: August 11, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas Walter Dyer, Junedong Lee, Dominic J. Schepis
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Patent number: 7994023Abstract: A manufacturing method of an SOI substrate and a manufacturing method of a semiconductor device are provided. When a large-area single crystalline semiconductor film is formed over an enlarged substrate having an insulating surface, e.g., a glass substrate by an SOI technique, the large-area single crystalline semiconductor film is formed without any gap between plural single crystalline semiconductor films, even when plural silicon wafers are used. An aspect of the manufacturing method includes the steps of disposing a first seed substrate over a fixing substrate; tightly arranging a plurality of single crystalline semiconductor substrates over the first seed substrate to form a second seed substrate; forming a large-area continuous single crystalline semiconductor film by an ion implantation separation method and an epitaxial growth method; forming a large-area single crystalline semiconductor film without any gap over a large glass substrate by an ion implantation separation method again.Type: GrantFiled: August 20, 2010Date of Patent: August 9, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tomoaki Moriwaka
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Publication number: 20110186958Abstract: A bond substrate is irradiated with ions, so that an embrittlement layer is formed, then, the bond substrate is bonded to a base substrate. Next, a part of a region of the bonded bond substrate is heated at a temperature higher than a temperature of the other part of the region of the bond substrate, or alternatively, a first heat treatment is performed on the bonded bond substrate as a whole at a first temperature; and a second heat treatment is performed on a part of a region of the bonded bond substrate at a second temperature higher than the first temperature, so that separation of the bond substrate proceeds from the part of the region of the bond substrate to the other part of the region of the bond substrate in the embrittlement layer. Accordingly, a semiconductor layer is formed over the base substrate.Type: ApplicationFiled: January 31, 2011Publication date: August 4, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Naoki OKUNO, Hajime TOKUNAGA
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Patent number: 7989316Abstract: To provide a method of manufacturing a semiconductor device in which the space between semiconductor films transferred at plural locations is narrowed. A first bonding substrate having first projections is attached to a base substrate. Then, the first bonding substrate is separated at the first projections so that first semiconductor films are formed over the base substrate. Next, a second bonding substrate having second projections is attached to the base substrate so that the second projections are placed in regions different from regions where the first semiconductor films are formed. Subsequently, the second bonding substrate is separated at the second projections so that second semiconductor films are formed over the base substrate. In the second bonding substrate, the width of each second projection in a direction (a depth direction) perpendicular to the second bonding substrate is larger than the film thickness of each first semiconductor film formed first.Type: GrantFiled: June 28, 2010Date of Patent: August 2, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Tatsuya Mizoi, Hidekazu Miyairi, Koichiro Tanaka
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Patent number: 7989315Abstract: When printing is performed on a base substrate with a laser after a single crystal silicon layer is transferred to the base substrate, there are problems such as ablation of the single crystal silicon layer in the peripheral portion of a printed dot or attachment of glass chips or the like to the surface of the single crystal silicon layer. After printing is performed on the bonding surface of a silicon wafer with a laser, the surface of the silicon wafer is polished by CMP (chemical mechanical polishing), so that the projection in the peripheral portion of the printed dot is removed. After that, the silicon wafer is bonded to the base substrate. Since the depression of the printed dot remains to some extent by a chemical etching effect even after the polishing by CMP, the single crystal silicon layer is not transferred only at the depression portion at the time of the transfer; accordingly, the information is left on the base substrate.Type: GrantFiled: November 24, 2009Date of Patent: August 2, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuya Kakehata, Takashi Kudo
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Publication number: 20110183493Abstract: The present invention relates to a process for manufacturing a structure comprising a germanium layer (3) on a support substrate (1), characterised in that it comprises the following steps: (a) formation of an intermediate structure (10) comprising said support substrate (1), a silicon oxide layer (20) and said germanium layer (3), the silicon oxide layer (20) being in direct contact with the germanium layer (3), (b) application to said intermediate structure (10) of a heat treatment, in a neutral or reducing atmosphere, at a defined temperature and for a defined time, to diffuse at least part of the oxygen from the silicon oxide layer (20) through the germanium layer (3).Type: ApplicationFiled: June 12, 2009Publication date: July 28, 2011Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Nicolas Daval, Oleg Kononchuk, Eric Guiot, Cecile Aulnette, Fabrice Lallement, Christophe Figuet, Didier Landru
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Publication number: 20110183494Abstract: Manufacturing cost of an SOI substrate is reduced. Yield of an SOI substrate is improved. A method for manufacturing an SOI substrate includes the steps of irradiating a single crystal semiconductor substrate with ions to form an embrittled region in the single crystal semiconductor substrate, bonding the single crystal semiconductor substrate to a base substrate with an insulating film therebetween, and separating the single crystal semiconductor substrate and the base substrate at the embrittled region to form a semiconductor layer over the base substrate with the insulating film therebetween. In the step of forming the embrittled region, ion species which are not mass-separated are used as the ions and a temperature of the single crystal semiconductor substrate is set to 250° C. or higher at the time of irradiation with the ions.Type: ApplicationFiled: January 21, 2011Publication date: July 28, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Junichi KOEZUKA, Hideto OHNUMA
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Patent number: 7985660Abstract: The present invention provides a method for manufacturing an SOI wafer, including: a step of preparing a base wafer consisting of a p+ silicon single crystal wafer and a bond wafer consisting of a silicon single crystal wafer containing a dopant at a lower concentration than that in the base wafer; a step of forming a silicon oxide film on an entire surface of the base wafer based on thermal oxidation; a step of bonding the bond wafer to the base wafer through the silicon oxide film; and a step of reducing a thickness of the bond wafer to form an SOI layer, wherein a step of forming a CVD insulator film on a surface on an opposite side of a bonding surface of the base wafer is provided before the thermal oxidation step for the base wafer.Type: GrantFiled: April 16, 2008Date of Patent: July 26, 2011Assignee: Shin Etsu Handotai Co., Ltd.Inventors: Isao Yokokawa, Hiroshi Takeno, Nobuhiko Noto
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Publication number: 20110175146Abstract: It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Hideto OHNUMA
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Patent number: 7981754Abstract: To provide a manufacturing method of a semiconductor substrate and a manufacturing method of a semiconductor device, which prevent reduction in breakdown voltage of a gate oxide film of a device formed in a semiconductor substrate to improve a reliability of the gate oxide film. A manufacturing method of a semiconductor substrate according to the present invention includes: exposing a silicon surface of an active layer substrate 1 made of single-crystal silicon, to which a semiconductor device is formed; forming an oxide film on a support substrate 2 made of single-crystal silicon; and bonding the silicon surface of the active layer substrate 1 to the oxide film formed on the support substrate 2. The silicon surface of the active layer substrate 1 is exposed by removing a spontaneous oxidation film 7 formed on the surface.Type: GrantFiled: August 13, 2007Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventor: Hiroaki Katou
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Publication number: 20110171791Abstract: A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.Type: ApplicationFiled: March 23, 2011Publication date: July 14, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto OHNUMA, Noritsugu NOMURA
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Publication number: 20110169051Abstract: A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.Type: ApplicationFiled: January 8, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Steven Koester, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 7977206Abstract: A heat treatment apparatus is disclosed, which enables suppression of a warp of a base substrate to which a plurality of single crystal semiconductor substrates are bonded. An example of the apparatus comprises a treatment chamber, a supporting base provided in the treatment chamber, a plurality of supports which are provided over the supporting base and are arranged to support the base substrate, and a heating unit for heating the base substrate, where each position of the plurality of supports can be changed over the supporting base. The use of this apparatus contributes to the reduction in the region where the base substrate and the supports are in contact with each other, which allows uniform heating of the base substrate, leading to the formation of an SOI substrate with high quality.Type: GrantFiled: January 8, 2009Date of Patent: July 12, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 7977209Abstract: A heating plate having a smooth surface is placed on a hot plate which constitutes a heating section, and the smooth surface of the heating plate is closely adhered on the rear surface of a single-crystal Si substrate bonded to a transparent insulating substrate. The temperature of the heating plate is kept at 200° C. or higher but not higher than 350° C. When the rear surface of the single-crystal Si substrate bonded to the insulating substrate is closely adhered on the heating plate, the single-crystal Si substrate is heated by thermal conduction, and a temperature difference is generated between the single-crystal Si substrate and the transparent insulating substrate. A large stress is generated between the both substrates due to rapid expansion of the single-crystal Si substrate, thus separation takes place at a hydrogen ion-implanted interface.Type: GrantFiled: February 8, 2007Date of Patent: July 12, 2011Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Yuuji Tobisaka, Koichi Tanaka
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Patent number: 7976629Abstract: Processes and machines for producing large area sheets or films of crystalline, polycrystalline, or amorphous material are set forth; the production of such sheets being valuable for the manufacturing of solar photovoltaic cells, flat panel displays and the like. The surface of rotating cylindrical workpiece (10) is implanted with ion beam (30), whereby a layer of weakened material is formed below the surface. Sheet (20) is detached and peeled off, producing arbitrarily large, monolithic sheets. The sheet may be supported on a temporary or permanent handle (50) such as a glass sheet or a polymer film. Pinch roller (60) may assist in the lamination of handle (50) to sheet (20) before or after the point of separation of sheet (20) from workpiece (10). The implantation, annealing and separation processes are adapted to encourage the material to separate along the implanted layer rather than a particular crystal plane.Type: GrantFiled: February 18, 2008Date of Patent: July 12, 2011Inventor: Adam Alexander Brailove
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Publication number: 20110165758Abstract: The invention relates to a method for making a structure for use ion applications in the fields of electronics, optics or optoelectronics. The structure includes a thin layer of semiconducting material on a supporting substrate. The method includes bonding the thin layer onto the supporting substrate by molecular adhesion at a bonding interface to obtain a structure; implanting ions at the bonding interface to transfer atoms from the thin layer to transfer atoms between the thin layer and the supporting substrate or vice versa; and heat-treating the structure in order to stabilize the bonding interface.Type: ApplicationFiled: July 3, 2009Publication date: July 7, 2011Inventors: Konstantin Bourdelle, Didier Landru, Karine Landry
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Publication number: 20110163410Abstract: A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling.Type: ApplicationFiled: June 6, 2008Publication date: July 7, 2011Applicants: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Thomas Signamarcheix, Franck Fournel, Hubert Moriceau
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Patent number: 7972938Abstract: Methods of producing CdZnTe (CZT) layers for the epitaxial growth of HgCdTe thereon include implanting ions into a CZT substrate at a low temperature to form a damaged layer underneath a CZT surface layer, bonding a wafer to the CZT substrate about the CZT surface layer using a bonding material, and, annealing the CZT substrate for a time sufficient to facilitate the splitting of the CZT substrate at the damaged layer from the CZT surface layer.Type: GrantFiled: June 5, 2009Date of Patent: July 5, 2011Assignee: UES, Inc.Inventors: Rabi S. Bhattacharya, Yongli Xu
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Patent number: 7972939Abstract: A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor wafer providing a layer of material to be transferred to the receiving handle wafer. Next, at least one of the first surfaces is treated to provide increased bonding energy when the first surfaces are bonded together; the surfaces are then bonded together to form an intermediate multilayer structure; and a portion of the donor wafer is removed to transfer the thin layer to the receiving handle wafer and form the semiconductor structure. This method avoids or minimizes contamination of the second surface of the receiving handle wafer by treating only the first surface of the donor wafer prior to bonding by exposure to a plasma, and by conducting any thermal treatments after plasma activation at a temperature of 300° C.Type: GrantFiled: September 24, 2009Date of Patent: July 5, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Sébastien Kerdiles, Christophe Maleville, Fabrice Letertre, Olivier Rayssac
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Patent number: 7972935Abstract: When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.Type: GrantFiled: August 18, 2010Date of Patent: July 5, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Ikuko Kawamata, Yasuyuki Arai
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Publication number: 20110156045Abstract: A crystal manufacturing apparatus capable of manufacturing a crystal in a desired position on a substrate is provided. A spring has one end fixed to a mount and the other end coupled to a magnetic body. The magnetic body has one end coupled to the spring and the other end coupled to a piston. A coil is wound around the magnetic body and electrically connected between a power supply circuit and a ground node (GND). The piston has a linear member inserted in a cylinder. The cylinder has a hollow columnar shape and a small hole at a bottom surface. The cylinder holds a silicon melt. A substrate is supported by an XY stage to be opposed to the small hole of the cylinder. The power supply circuit passes pulse shaped current through the coil to move the piston in an up-down direction (DR1). As a result, a droplet is discharged toward the substrate from the small hole at an initial speed of 1.02 m/s.Type: ApplicationFiled: August 28, 2009Publication date: June 30, 2011Applicant: HIROSHIMA UNIVERSITYInventors: Seiichiro Higashi, Naohiro Koba
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Patent number: 7968909Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.Type: GrantFiled: November 4, 2010Date of Patent: June 28, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Frederic Dupont
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Publication number: 20110151643Abstract: A method for manufacturing a bonded wafer by forming an ion implanted layer in a bond wafer; bonding an ion implanted surface of the bond wafer to a surface of a base wafer directly or through a silicon oxide film; and performing a delamination heat treatment. After the formation of the ion implanted layer and before the bonding, a plasma treatment is carried out with respect to a bonding surface of at least one of the bond wafer and the base wafer. The delamination heat treatment is carried out at a fixed temperature by directly putting the bonded wafer into a heat-treating furnace whose furnace temperature is set to the fixed temperature less than 475° C. without a temperature increasing step.Type: ApplicationFiled: August 4, 2009Publication date: June 23, 2011Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro Kobayashi, Hiroji Aga, Tohru Ishizuka
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Publication number: 20110136320Abstract: To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOL substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered.Type: ApplicationFiled: February 2, 2011Publication date: June 9, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Eiji HIGA, Yoji NAGANO, Tatsuya MIZOI, Akihisa SHIMOMURA
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Publication number: 20110136321Abstract: Provided is a method for manufacturing a lamination type semiconductor integrated device that can simultaneously attain grinding force resistance during back side grinding of a semiconductor wafer, heat resistance during anisotropic dry etching and the like, chemical resistance during plating and etching, smooth debonding of a support substrate for processing at the end, and low adherend staining; the method comprises at least a step of back side grinding of a first semiconductor wafer having a device formed on its surface and a step of laminating by electrical bonding the first semiconductor wafer with a second semiconductor wafer having a device formed on its surface, wherein, at the time of back side grinding of the first semiconductor wafer, back of the first semiconductor wafer is ground after surface of formed device on the first semiconductor wafer is bonded to a support substrate for processing by using a pressure-sensitive silicone adhesive.Type: ApplicationFiled: November 19, 2010Publication date: June 9, 2011Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Yasuyoshi KURODA, Kazunori KONDO, Hideto KATO
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Publication number: 20110129989Abstract: Even when a substrate for treatment is joined with a supporting substrate having an outer shape larger than that of the substrate for treatment, with a photothermal conversion layer and an adhesive layer interposed, and the surface of the substrate for treatment on the side opposite this joined surface is treated, the occurrence of a defective external appearance on the treatment surface of the substrate for treatment is prevented. An adhesive layer 4 is formed on one surface of a substrate for treatment 3, a photothermal conversion layer 2 is formed on one surface of a supporting substrate 1 having a surface with an outer shape larger than that of the surface of the substrate for treatment, and the substrate for treatment 3 is bonded onto the surface of the photothermal conversion layer 2 with the adhesive layer 4 interposed, to obtain a layered member.Type: ApplicationFiled: April 15, 2009Publication date: June 2, 2011Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.Inventors: Yuichi Urano, Kenichi Kazama
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Publication number: 20110129987Abstract: To provide a structure and a manufacturing method for efficiently forming a transistor to which tensile strain is preferably applied and a transistor to which compressive strain is preferably applied over the same substrate when stress is applied to a semiconductor layer in order to improve mobility of the transistors in a semiconductor device. Plural kinds of transistors which are separated from a single-crystal semiconductor substrate and include single-crystal semiconductor layers bonded to a substrate having an insulating surface with a bonding layer interposed therebetween are provided over the same substrate. One of the transistors uses a single-crystal semiconductor layer as an active layer, to which tensile strain is applied. The other transistors use single-crystal semiconductor layers as active layers, to which compressive strain using part of heat shrink generated by heat treatment of the base substrate after bonding is applied.Type: ApplicationFiled: February 10, 2011Publication date: June 2, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Yoshifumi TANADA
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Publication number: 20110129988Abstract: A method of implanting atoms and/or ions into a substrate, including: a) a first implantation of ions or atoms at a first depth in the substrate, to form a first implantation plane, b) at least one second implantation of ions or atoms at a second depth in the substrate, which is different from the first depth, to form at least one second implantation plane.Type: ApplicationFiled: July 7, 2009Publication date: June 2, 2011Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Thomas Signamarcheix, Chrystel Deguet, Frederic Mazen
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Patent number: 7951690Abstract: An image sensor includes circuitry, a metal interconnection, a first substrate, a metal ion-implanted insulating layer, and a photodiode. The circuitry is formed on and/or over the first substrate, and the metal ion-implanted insulating layer is formed on and/or over the metal interconnection. The photodiode is formed in a crystalline semiconductor layer over the metal ion-implanted insulating layer.Type: GrantFiled: December 18, 2008Date of Patent: May 31, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Sang Uk Lee
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Patent number: 7951656Abstract: A stack including at least an insulating layer, a first electrode, and a first impurity semiconductor layer is provided over a supporting substrate; a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed over the first impurity semiconductor layer; a second semiconductor layer to which an impurity element imparting the one conductivity type is added is formed over the first semiconductor layer under a condition different from that of the first semiconductor layer; crystallinity of the first semiconductor layer and crystallinity of the second semiconductor layer are improved by a solid-phase growth method to form a second impurity semiconductor layer; an impurity element imparting the one conductivity type and an impurity element imparting a conductivity type different from the one conductivity type are added to the second impurity semiconductor layer; and a gate electrode layer is formed via a gate insulating layer.Type: GrantFiled: May 18, 2009Date of Patent: May 31, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sho Kato, Satoshi Toriumi, Fumito Isaka, Hideto Ohnuma
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Patent number: 7951692Abstract: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not more than 50 nm in thickness to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate through the oxide film, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer.Type: GrantFiled: November 13, 2008Date of Patent: May 31, 2011Assignee: Sumco CorporationInventors: Satoshi Murakami, Nobuyuki Morimoto, Hideki Nishihata, Akihiko Endo
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Publication number: 20110124164Abstract: An amorphous semiconductor layer is formed over a first single crystal semiconductor layer provided over a glass substrate or a plastic substrate with an insulating layer therebetween. The amorphous semiconductor layer is formed by a CVD method at a deposition temperature of higher than or equal to 100° C. and lower than or equal to 275° C. with use of a silane-based gas not diluted. Heat treatment is performed so that the amorphous semiconductor layer solid-phase epitaxially grows. In such a manner, an SOI substrate including a thick single crystal semiconductor layer is manufactured.Type: ApplicationFiled: November 18, 2010Publication date: May 26, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kosei NODA, Toshihiko TAKEUCHI, Makoto ISHIKAWA
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Patent number: 7947571Abstract: The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3×106 atoms per cm2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.Type: GrantFiled: June 4, 2009Date of Patent: May 24, 2011Assignee: S.O.I. Tec Silicon on Insulator TechnologiesInventors: Luciana Capello, Oleg Kononchuk, Eric Neyret, Alexandra Abbadie, Walter Schwarzenbach
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Publication number: 20110114998Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.Type: ApplicationFiled: January 25, 2011Publication date: May 19, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Tomoaki MORIWAKA
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Publication number: 20110117727Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer, the method configured to grow an epitaxial layer on an SOI layer of the SOI wafer having the SOI layer on a BOX layer to increase a thickness of the SOI layer, wherein epitaxial growth is carried out by using an SOI wafer whose infrared reflectance in an infrared wavelength range of 800 to 1300 nm falls within the range of 20% to 40% as the SOI wafer on which the epitaxial layer is grown. As a result, a high-quality SOI wafer with less slip dislocation and others can be provided with excellent productivity at a low cost as the SOI wafer including the SOI layer having a thickness increased by growing the epitaxial layer, and a manufacturing method thereof can be also provide.Type: ApplicationFiled: July 29, 2009Publication date: May 19, 2011Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Satoshi Oka, Susumu Kuwabara
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Patent number: 7943485Abstract: Method for producing composite wafers with thin high-quality semiconductor films atomically attached to synthetic diamond wafers is disclosed. Synthetic diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited on bulk semiconductor wafer which has been prepared to allow separation of the thin semiconductor film from the remaining bulk semiconductor wafer. The remaining semiconductor wafer is available for reuse. The synthetic diamond substrate serves as heat spreader and a mechanical substrate.Type: GrantFiled: January 22, 2008Date of Patent: May 17, 2011Assignee: Group4 Labs, LLCInventors: Daniel Francis, Felix Ejeckam, John Wasserbauer, Firooz Faili, Dubravko Babic
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Patent number: 7943414Abstract: An object of an embodiment of the present invention to be disclosed is to prevent oxygen from being taken in a single crystal semiconductor layer in laser irradiation even when crystallinity of the single crystal semiconductor layer is repaired by irradiation with a laser beam; and to make substantially equal or reduce an oxygen concentration in the semiconductor layer after the laser irradiation comparing before the laser irradiation. A single crystal semiconductor layer which is provided over a base substrate by bonding is irradiated with a laser beam, whereby the crystallinity of the single crystal semiconductor layer is repaired. The laser irradiation is performed under a reducing atmosphere or an inert atmosphere.Type: GrantFiled: July 30, 2009Date of Patent: May 17, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Hideto Ohnuma, Junpei Momo, Shunpei Yamazaki
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Publication number: 20110111575Abstract: A heating plate having a smooth surface is placed on a hot plate which constitutes a heating section, and the smooth surface of the heating plate is closely adhered on the rear surface of a single-crystal Si substrate bonded to a transparent insulating substrate. The temperature of the heating plate is kept at 200° C. or higher but not higher than 350° C. When the rear surface of the single-crystal Si substrate bonded to the insulating substrate is closely adhered on the heating plate, the single-crystal Si substrate is heated by thermal conduction, and a temperature difference is generated between the single-crystal Si substrate and the transparent insulating substrate. A large stress is generated between the both substrates due to rapid expansion of the single-crystal Si substrate, thus separation takes place at a hydrogen ion-implanted interface.Type: ApplicationFiled: January 20, 2011Publication date: May 12, 2011Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Yuuji Tobisaka, Koichi Tanaka
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Patent number: 7939428Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: GrantFiled: October 28, 2010Date of Patent: May 10, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
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Publication number: 20110104871Abstract: Provided is a method for manufacturing a bonded wafer with a good thin film over the entire substrate surface, especially in the vicinity of the lamination terminal point. The method for manufacturing a bonded wafer comprises at least the following steps of: forming an ion-implanted region by implanting a hydrogen ion or a rare gas ion, or the both types of ions from a surface of a first substrate which is a semiconductor substrate; subjecting at least one of an ion-implanted surface of the first substrate and a surface of a second substrate to be attached to a surface activation treatment; laminating the ion-implanted surface of the first substrate and the surface of the second substrate in an atmosphere with a humidity of 30% or less and/or a moisture content of 6 g/m3 or less; and a splitting the first substrate at the ion-implanted region so as to reduce thickness of the first substrate, thereby manufacturing a bonded wafer with a thin film on the second substrate.Type: ApplicationFiled: April 10, 2009Publication date: May 5, 2011Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Yuji Tobisaka, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Shoji Akiyama, Hiroshi Tamura
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Publication number: 20110104870Abstract: A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.Type: ApplicationFiled: February 17, 2009Publication date: May 5, 2011Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro Kobayashi, Tohru Ishizuka, Hiroji Aga, Nobuhiko Noto
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Publication number: 20110097871Abstract: Methods for forming semiconductor structures comprising a layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect of defects, and resulting structures therefrom. For example, a semiconductor on insulator (SeOI) structure can be formed by a method comprising: —providing a donor substrate (1) having a first density of vacancy clusters; —providing an insulating layer (3); —transferring a thin layer (10) from the donor substrate (1) to a support substrate (2) with the insulating layer (3) thereon; —curing the transferred thin layer (10) to reduce the first density of vacancy clusters to a second density; and being characterized in that the step of providing an insulating layer (30) comprises providing an oxygen barrier layer (4) to be in contact with the transferred thin layer (10), said oxygen barrier layer limiting diffusion of oxygen towards the thin layer during the curing.Type: ApplicationFiled: October 27, 2006Publication date: April 28, 2011Inventors: Eric Neyret, Oleg Kononchuk
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Publication number: 20110092050Abstract: A first embrittlement layer is formed by doping a first single-crystal semiconductor substrate with a first ion; a second embrittlement layer is formed by doping a second single-crystal semiconductor substrate with a second ion; the first and second single-crystal semiconductor substrates are bonded to each other; the first single-crystal semiconductor film is formed over the second single-crystal semiconductor substrate by a first heat treatment; an insulating substrate is bonded over the first single-crystal semiconductor film; and the first and second single-crystal semiconductor films are formed over the insulating substrate by a second heat treatment. A dose of the first ion is higher than that of the second ion and a temperature of the first heat treatment is lower than that of the second heat treatment.Type: ApplicationFiled: October 8, 2010Publication date: April 21, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Akihisa SHIMOMURA, Naoki OKUNO, Masaki KOYAMA, Yasuhiro JINBO
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Patent number: 7927975Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: February 4, 2009Date of Patent: April 19, 2011Assignee: Micron Technology, Inc.Inventors: Nishant Sinha, Gurtej S. Sandhu, John Smythe
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Patent number: 7927970Abstract: Disclosed are methods for making SOI and SOG structures using purified ion shower for implanting ions to the donor substrate. The purified ion shower provides expedient, efficient, low-cost and effective ion implantation while minimizing damage to the exfoliation film.Type: GrantFiled: February 11, 2009Date of Patent: April 19, 2011Assignee: Corning IncorporatedInventors: Jeffrey Scott Cites, Kishor Purushottam Gadkaree, Richard Orr Maschmeyer
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Patent number: 7923348Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFF, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.Type: GrantFiled: June 9, 2009Date of Patent: April 12, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
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Patent number: 7919391Abstract: The invention concerns a method of treating one or both bonding surfaces of first and second substrates and in particular, the surfaces of donor and receiver wafers that are intended to be bonded together. A simultaneous cleaning and activation step is carried out immediately prior to bonding the wafers together, by applying to one or both bonding surfaces an activation solution of ammonia (NH4OH) in water, preferably deionized, at a concentration by weight in the range from about 0.05% to 2%. The method is applicable to fabricating structures used in the optics, electronics, or optoelectronics fields.Type: GrantFiled: June 2, 2005Date of Patent: April 5, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Cécile Delattre, Frédéric Metral, Daniel Delprat, Christophe Maleville
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Publication number: 20110076836Abstract: A method for forming a plurality of thin films from a microtechnological donar substrate with a view to recycling of the donor substrate, the method including exposing a face of the donor substrate by fracturing the donor substrate along a layer weakened by implantation and placing the exposed face in a bath and applying ultrasound with a frequency of between 10 kHz and 80 kHz under conditions suitable for causing cavitation along the exposed face. In the case of a silicon donor substrate, the bath is exposed to an ultrasound power per unit volume of greater than 5 W/I, at a power of greater than 10 W with a duration of greater than 1 minute, and at a temperature between 1° C. and 100° C.Type: ApplicationFiled: September 23, 2010Publication date: March 31, 2011Inventor: Aurelie Tauzin