With Separation/delamination Along Porous Layer (epo) Patents (Class 257/E21.57)
  • Publication number: 20110309467
    Abstract: Disclosed is a semiconductor device including a substrate for bonding (10a), and a semiconductor element part (25aa) which is bonded to the substrate (10a), and in which an element pattern (T) is formed, wherein in a bonded interface between the substrate (10a) and the semiconductor element part (25aa), recessed portions (23a) are formed in at least one of the substrate (10a) and the semiconductor element part (25aa).
    Type: Application
    Filed: November 25, 2009
    Publication date: December 22, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shin Matsumoto, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Kenshi Tada
  • Patent number: 8058146
    Abstract: The present invention provides a method for manufacturing massively and efficiently a minute device which can receive or send data in contact, preferably, out of contact by forming an integrated circuit which is formed by a thin film over a large glass substrate and by peeling the integrated circuit from the substrate. Especially, an integrated circuit which is formed by a thin film is extremely thin, and so there is a threat that the integrated circuit is flied when transporting, and so handling thereof is difficult. In accordance with the present invention, a separating layer (also referred to as a peeling layer) is damaged at a plurality of times by at least two different kinds of methods (a damage due to laser light irradiation, a damage due to etching, or a damage due to a physical means), subsequently, the layer to be peeled can be efficiently peeled from a substrate. Further, handling of individual devices becomes easy by arching the peeled device.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: November 15, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideaki Kuwabara
  • Patent number: 8053331
    Abstract: Processes for transferring a semiconductor material to a polymer substrate to provide flexible semiconductor material include implanting ions to a predetermined depth in a semiconductor substrate, heat-treating the ion-implanted semiconductor substrate for a period of time and at a temperature effective to cause defect formation and enlargement of the implanted ion defect, adhering the ion-implanted, heat-treated substrate to a polymer substrate, and separating a semiconductor film such as a single crystal silicon film from the semiconductor substrate; and devices having single crystal silicon films disposed directly or indirectly on polymer films.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: November 8, 2011
    Assignee: Corning Incorporated
    Inventor: Kishor P. Gadkaree
  • Patent number: 8048770
    Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yohei Monma, Atsuhiro Tani, Misako Hirosue, Kenichi Hashimoto, Yasuharu Hosaka
  • Patent number: 8043936
    Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: October 25, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yohei Monma, Atsuhiro Tani, Misako Hirosue, Kenichi Hashimoto, Yasuharu Hosaka
  • Patent number: 8039362
    Abstract: Provided is a method for fabricating a light emitting device. The method comprises forming a gallium oxide layer, forming a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the gallium oxide layer, forming a conductive substrate on the second conductive type semiconductor layer, separating the gallium oxide layer, and forming a first electrode on the first conductive type semiconductor layer.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: October 18, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Yong Tae Moon
  • Patent number: 8021959
    Abstract: A method for forming a plurality of thin films from a microtechnological donar substrate with a view to recycling of the donor substrate, the method including exposing a face of the donor substrate by fracturing the donor substrate along a layer weakened by implantation and placing the exposed face in a bath and applying ultrasound with a frequency of between 10 kHz and 80 kHz under conditions suitable for causing cavitation along the exposed face. In the case of a silicon donor substrate, the bath is exposed to an ultrasound power per unit volume of greater than 5 W/I, at a power of greater than 10 W with a duration of greater than 1 minute, and at a temperature between 1° C. and 100° C.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: September 20, 2011
    Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
    Inventor: Aurelie Tauzin
  • Patent number: 8021960
    Abstract: A chip provided with a layer for separation of a surface region and a hydrophilic surface is manufactured. One or both of a hydrophilic region and a hydrophobic region are formed on a substrate surface where the chip is placed. Liquid is dropped onto the hydrophilic region on the substrate surface, and the chip is placed thereon. The substrate and the chip are heated while being pressure-bonded so that the chip is fixed on the substrate surface, and then the surface region of the chip is separated. By providing a liquid layer in a position where the chip is placed, the chip can be placed on the substrate with high accuracy and thus productivity can be increased.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: September 20, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8021962
    Abstract: A method of manufacturing a functional film by which a functional film formed on a film formation substrate can be easily peeled from the film formation substrate. The method includes the steps of: (a) forming a separation layer on a substrate by using an inorganic material which is decomposed to generate a gas by being applied with an electromagnetic wave; (b) forming a layer to be peeled containing a functional film, which is formed by using a functional material, on the separation layer; and (c) applying the electromagnetic wave toward the separation layer so as to peel the layer to be peeled from the substrate or reduce bonding strength between the layer to be peeled and the substrate.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: September 20, 2011
    Assignee: Fujifilm Corporation
    Inventor: Yukio Sakashita
  • Patent number: 8012852
    Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: September 6, 2011
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Patent number: 8003491
    Abstract: Methods and apparatus provide for forming a semiconductor-on-insulator (SOI) structure, including subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that at least one parameter of the weakened slice varies spatially across the weakened slice in at least one of X- and Y-axial directions.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: August 23, 2011
    Assignee: Corning Incorporated
    Inventors: Sarko Cherekdjian, Jeffrey Scott Cites, James Gregory Couillard, Richard Orr Maschmeyer, Michael John Moore, Alex Usenko
  • Patent number: 7981754
    Abstract: To provide a manufacturing method of a semiconductor substrate and a manufacturing method of a semiconductor device, which prevent reduction in breakdown voltage of a gate oxide film of a device formed in a semiconductor substrate to improve a reliability of the gate oxide film. A manufacturing method of a semiconductor substrate according to the present invention includes: exposing a silicon surface of an active layer substrate 1 made of single-crystal silicon, to which a semiconductor device is formed; forming an oxide film on a support substrate 2 made of single-crystal silicon; and bonding the silicon surface of the active layer substrate 1 to the oxide film formed on the support substrate 2. The silicon surface of the active layer substrate 1 is exposed by removing a spontaneous oxidation film 7 formed on the surface.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroaki Katou
  • Patent number: 7977206
    Abstract: A heat treatment apparatus is disclosed, which enables suppression of a warp of a base substrate to which a plurality of single crystal semiconductor substrates are bonded. An example of the apparatus comprises a treatment chamber, a supporting base provided in the treatment chamber, a plurality of supports which are provided over the supporting base and are arranged to support the base substrate, and a heating unit for heating the base substrate, where each position of the plurality of supports can be changed over the supporting base. The use of this apparatus contributes to the reduction in the region where the base substrate and the supports are in contact with each other, which allows uniform heating of the base substrate, leading to the formation of an SOI substrate with high quality.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: July 12, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7968382
    Abstract: An object of the invention is to provide a method for manufacturing semiconductor devices that are flexible in which elements fabricated using a comparatively low-temperature (less than 500° C.) process are separated from a substrate. After a molybdenum film is formed over a glass substrate, a molybdenum oxide film is formed over the molybdenum film, a nonmetal inorganic film and an organic compound film are stacked over the molybdenum oxide film, and elements fabricated by a comparatively low-temperature (less than 500° C.) process are formed using existing manufacturing equipment for large glass substrates, the elements are separated from the glass substrate.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: June 28, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Toshiyuki Isa, Tatsuya Honda
  • Patent number: 7951692
    Abstract: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not more than 50 nm in thickness to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate through the oxide film, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: May 31, 2011
    Assignee: Sumco Corporation
    Inventors: Satoshi Murakami, Nobuyuki Morimoto, Hideki Nishihata, Akihiko Endo
  • Patent number: 7951691
    Abstract: In a method for producing a thin film chip including an integrated circuit, a semi-conductor wafer having a first surface is provided. At least one cavity is produced under a defined section of the first surface by means of porous silicon. A circuit structure is produced in the defined section. The defined wafer section is subsequently released from the semiconductor wafer by severing local web-like connections, which hold the wafer section above the cavity and on the remaining semiconductor wafer.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: May 31, 2011
    Assignee: Institut fuer Mikroelektronik Stuttgart
    Inventors: Joachim N. Burghartz, Martin Zimmermann, Wolfgang Appel
  • Patent number: 7947572
    Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: May 24, 2011
    Assignees: Sumitomo Mitsubishi Silicon Corp., Jeagun Park
    Inventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama
  • Patent number: 7943485
    Abstract: Method for producing composite wafers with thin high-quality semiconductor films atomically attached to synthetic diamond wafers is disclosed. Synthetic diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited on bulk semiconductor wafer which has been prepared to allow separation of the thin semiconductor film from the remaining bulk semiconductor wafer. The remaining semiconductor wafer is available for reuse. The synthetic diamond substrate serves as heat spreader and a mechanical substrate.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: May 17, 2011
    Assignee: Group4 Labs, LLC
    Inventors: Daniel Francis, Felix Ejeckam, John Wasserbauer, Firooz Faili, Dubravko Babic
  • Patent number: 7939428
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: May 10, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
  • Patent number: 7919391
    Abstract: The invention concerns a method of treating one or both bonding surfaces of first and second substrates and in particular, the surfaces of donor and receiver wafers that are intended to be bonded together. A simultaneous cleaning and activation step is carried out immediately prior to bonding the wafers together, by applying to one or both bonding surfaces an activation solution of ammonia (NH4OH) in water, preferably deionized, at a concentration by weight in the range from about 0.05% to 2%. The method is applicable to fabricating structures used in the optics, electronics, or optoelectronics fields.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: April 5, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Cécile Delattre, Frédéric Metral, Daniel Delprat, Christophe Maleville
  • Patent number: 7919392
    Abstract: On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substrate. Subsequently, the SOI substrate is cleaved at the hydrogen ion implantation section by carrying out heat treatment, so that an unnecessary part of the SOI substrate is removed, Furthermore, the BOX layer remaining on the single-crystal silicon thin-film transistor is removed by etching. With this, it is possible to from a single-crystal silicon thin-film device on an insulating substrate, without using an adhesive. Moreover, it is possible to provide a semiconductor device which has no surface damage and includes a single-crystal silicon thin film which is thin and uniform in thickness.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: April 5, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Takashi Itoga
  • Patent number: 7897427
    Abstract: There is provided a method for manufacturing a solid-state image device which includes the steps of: forming a silicon epitaxial growth layer on a silicon substrate; forming photoelectric conversion portions, transfer gates, and a peripheral circuit portion in and/or on the silicon epitaxial growth layer and further forming a wiring layer on the silicon epitaxial growth layer; forming a split layer in the silicon substrate at a side of the silicon epitaxial growth layer; forming a support substrate on the wiring layer; peeling the silicon substrate from the split layer so as to leave a silicon layer formed of a part of the silicon substrate at a side of the support substrate; and planarizing the surface of the silicon layer.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: March 1, 2011
    Assignee: Sony Corporation
    Inventor: Chiaki Sakai
  • Patent number: 7863155
    Abstract: It is an object of the present invention to obtain a large-sized SOI substrate by providing a single-crystal silicon layer over a large-sized glass substrate in a large area. After a plurality of rectangular single-crystal semiconductor substrates each provided with a separation layer are aligned over a dummy substrate and both of the substrates are fixed with a low-temperature coagulant, the plurality of single-crystal semiconductor substrates are bonded to a support substrate; the temperature is raised up to a temperature, at which the low-temperature coagulant does not to have a bonding effect, so as to isolate the dummy substrate and the single-crystal semiconductor substrates; heat treatment is performed to separate part of the single-crystal semiconductor substrates, along a boundary of the respective separation layers; and single-crystal semiconductor layers are provided over the support substrate.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: January 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Patent number: 7846818
    Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: December 7, 2010
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Patent number: 7838392
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: November 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 7839001
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 23, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Giséle Rayssac, legal representative
  • Patent number: 7829433
    Abstract: A manufacturing method of a semiconductor substrate is provided, in which a bonding strength can be increased even when a substrate having low heat resistant temperature, e.g., a glass substrate, is used. Heat treatment is conducted at a temperature higher than or equal to a strain point of a support substrate in an oxidation atmosphere containing halogen, so that a surface of a semiconductor substrate is covered with an insulating film. A separation layer is formed in the semiconductor substrate. A blocking layer is provided. Then, heat treatment is conducted in a state in which the semiconductor substrate and the support substrate are superposed with the silicon oxide film therebetween, at a temperature lower than or equal to the support substrate, so that a part of the semiconductor substrate is separated at the separation layer. In this manner, a single crystal semiconductor layer is formed on the support substrate.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: November 9, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7820527
    Abstract: An approach for providing a cleave initiation using a varying ion implant dose is described. In one embodiment, there is a method of forming a substrate. In this embodiment, a semiconductor material is provided and implanted with a spatially varying dose of one or more ion species. A handler substrate is attached to the implanted semiconductor material. A cleave of the implanted semiconductor material is initiated from the handler substrate at a preferential location that is a function of a dose gradient that develops from the spatially varying dose of one or more ion species implanted into the semiconductor material.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: October 26, 2010
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Peter Nunan, Steven R. Walther, Yuri Erokhin, Paul J. Sullivan
  • Patent number: 7799656
    Abstract: A method is disclosed for making a MEMS device wherein anhydrous HF exposed silicon nitride is used as a temporary adhesion layer allowing the transfer of a layer from a Carrier Wafer to a Device Wafer.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: September 21, 2010
    Assignee: DALSA Semiconductor Inc.
    Inventors: Luc Ouellet, Patrick Wright
  • Patent number: 7795117
    Abstract: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not more than 50 nm in thickness to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate through the oxide film, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: September 14, 2010
    Assignee: Sumco Corporation
    Inventors: Satoshi Murakami, Nobuyuki Morimoto, Hideki Nishihata, Akihiko Endo
  • Patent number: 7790565
    Abstract: Methods and apparatus for producing a semiconductor on glass (SiOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing at least one cleaved surface; and subjecting the at least one cleaved surface to a wet etching process.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: September 7, 2010
    Assignee: Corning Incorporated
    Inventors: Kishor Purushottam Gadkaree, Michael John Moore, Mark Andrew Stocker, Jiangwei Feng, Joseph Frank Mach
  • Patent number: 7776717
    Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: August 17, 2010
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Patent number: 7772087
    Abstract: The invention relates to a method of catastrophic transfer of a thin film including implanting in a source substrate a first species of ions or gas at a given depth and a second species of ions or gas, the first species being adapted to generate defects and the second species being adapted to occupy those defects. The process further includes applying a stiffener in intimate contact with the source substrate, applying a heat treatment to that source substrate, at a given temperature for a given time, so as to create, substantially at the given depth, a buried weakened zone, without initiating the thermal splitting of a thin film, and applying a localized amount of energy, for example mechanical stresses, to that source substrate so as to provoke the catastrophic splitting of a thin film, the thin film having a substantially planar face opposite to the face surface of the source substrate.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: August 10, 2010
    Assignees: Commissariat A l'Energie Atomique, S.O.I. Tec Silicon On Insulator Technologies
    Inventors: Nguyet-Phuong Nguyen, Ian Cayrefourcq, Christelle Lagahe-Blanchard
  • Patent number: 7759217
    Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: July 20, 2010
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Patent number: 7741193
    Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: June 22, 2010
    Assignees: Sumitomo Mitsubishi Silicon Corp., Jeagun Park
    Inventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama
  • Patent number: 7713839
    Abstract: Electronic assemblies and methods for forming assemblies including a diamond substrate are described. One embodiment includes providing a diamond support and forming a porous layer of SiO2 on the diamond support. A diamond layer is formed by chemical vapor deposition on the porous layer so that the porous layer is between the diamond support and the diamond layer. A polycrystalline silicon layer is formed on the diamond layer. The polycrystalline silicon layer is polished to form a planarized surface. A semiconductor layer is coupled to the polysilicon layer. After coupling the semiconductor layer to the polysilicon layer, the diamond support is detached from the diamond layer by breaking the porous layer. The semiconductor layer on the diamond layer substrate is then further processed to form a semiconductor device.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Gregory M. Chrysler, Daoqiang Lu
  • Patent number: 7696065
    Abstract: A semiconductor device manufacturing method is disclosed. A semiconductor substrate having a separation region and a semiconductor region which covers the separation region entirely is prepared. One or a plurality of circuit elements are formed in the semiconductor region. The semiconductor substrate is split at the separation region.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: April 13, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuhiko Sato, Shigeru Kido, Kazutaka Momoi
  • Patent number: 7687303
    Abstract: A method for determining an effect of via/contact pattern density in via/contact etch rate of a wafer includes determining a neutral etchant species number flux intersecting each via/contact mouth as a function of local layout characteristics and determining variations in the neutral etchant species flux number as a function of the via/contact pattern density in a wafer scale. The comparison of these number fluxes provides the capability to discriminate an underetched or an overetched via/contact from normal vias/contacts satisfying an etch tolerance criterion. Chip designers can modify the layout design to minimize via/contact failures. Chip manufacturers can modify the etching process to minimize via/contact failures.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: March 30, 2010
    Assignee: Mentor Graphics Corporation
    Inventors: Valeriy Sukharev, Ara Markosian
  • Patent number: 7622363
    Abstract: A semiconductor substrate including a gallium arsenide layer is obtained by executing a step of preparing a first substrate having a separating layer constituted of germanium and a gallium arsenide layer on the separating layer, a step of preparing a bonded substrate by bonding the first substrate and a second substrate, and a step of dividing the bonded substrate at a portion of the separating layer.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: November 24, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Yoshinobu Sekiguci
  • Patent number: 7615467
    Abstract: This method for manufacturing an SOI wafer includes: a step of subjecting a mirror-polished active layer wafer to a rapid thermal annealing treatment; a step of forming insulating films in a front surface and a rear surface of the active layer wafer; a step of bonding the active layer wafer and a support wafer with the insulating film therebetween so as to form a bonded wafer; a step of loading the bonded wafer on a wafer boat in a state such that a portion of the active layer wafer is in contact with the wafer boat, and then subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer in the bonded wafer; and a step of thinning a portion of the active layer wafer.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: November 10, 2009
    Assignee: Sumco Corporation
    Inventors: Takaaki Shiota, Yasuhiro Oura
  • Patent number: 7615468
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: November 10, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
  • Publication number: 20090269907
    Abstract: On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substrate. Subsequently, the SOI substrate is cleaved at the hydrogen ion implantation section by carrying out heat treatment, so that an unnecessary part of the SOI substrate is removed, Furthermore, the BOX layer remaining on the single-crystal silicon thin-film transistor is removed by etching. With this, it is possible to from a single-crystal silicon thin-film device on an insulating substrate, without using an adhesive. Moreover, it is possible to provide a semiconductor device which has no surface damage and includes a single-crystal silicon thin film which is thin and uniform in thickness.
    Type: Application
    Filed: July 9, 2009
    Publication date: October 29, 2009
    Applicant: Sharp Kabushiki Kaishi
    Inventors: Yutaka Takafuji, Takashi Itoga
  • Patent number: 7588994
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: September 15, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Publication number: 20090179299
    Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.
    Type: Application
    Filed: February 25, 2009
    Publication date: July 16, 2009
    Inventors: Olivier RAYSSAC, Takeshi Akatsu
  • Patent number: 7550305
    Abstract: An object of the present invention is to provide a method of forming a light-emitting element at a lower cost than a conventional cost with suppressing the deterioration of the substrate due to thermal distortion in comparison with a conventional method of recycling a substrate and further having an effect equal to that of the method of recycling a substrate.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: June 23, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takao Yonehara, Yoshinobu Sekiguchi, Kojiro Nishi
  • Patent number: 7544585
    Abstract: Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO2 layer.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: June 9, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-soo Park, Wenxu Xianyu, Takashi Noguchi
  • Patent number: 7541263
    Abstract: The invention relates to a method for producing a semiconducting structure on a semiconducting substrate, one surface of which has a topology, this method including: a) a step for forming a first layer (24) in a first insulating material on said surface, b) a step for forming a second layer in a second insulating material (28), less dense than the first insulating material, with a thickness between 2.5 p and 3.5 p, c) a step for planarization of the assembly.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: June 2, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Christophe Morales, Marc Zussy, Jerome Dechamp
  • Publication number: 20090111247
    Abstract: A method for forming a single crystal semiconductor layer in which a first porous layer and a second porous layer are formed over a single crystal semiconductor ingot, a groove is formed in a part of the second porous layer and a single crystal semiconductor layer is formed over the second porous layer, the single crystal semiconductor ingot is attached onto a large insulating substrate, water jet is directed to the interface between the first porous layer and the second porous layer, and the single crystal semiconductor layer is attached to the large insulating substrate, or a method for forming a crystalline semiconductor layer in which a crystalline semiconductor ingot is irradiated with hydrogen ions to form a hydrogen ion irradiation region in the crystalline semiconductor ingot, the crystalline semiconductor ingot is rolled over the large insulating substrate while being heated, the crystalline semiconductor layer is separated from the hydrogen ion irradiation region, and the crystalline semiconductor l
    Type: Application
    Filed: October 24, 2008
    Publication date: April 30, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Koichiro TANAKA, Satoru OKAMOTO
  • Patent number: 7494899
    Abstract: This method for manufacturing a semiconductor substrate is characterized in that the method includes: a step of ion-implanting light element to a predetermined depth position in a single-crystal wafer of which a surface is a cleavage plane; and a step of heat-treating the single-crystal wafer so as to form light-element bubbles along a cleavage plane parallel to the surface of the single-crystal wafer within an ion-implanted region and thereby splitting off a portion of the single-crystal wafer on an ion-implanted side.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: February 24, 2009
    Assignee: Sumco Corporation
    Inventors: Akihiko Endo, Nobuyuki Morimoto
  • Patent number: RE42830
    Abstract: A porous Si layer is formed on a single-crystal Si substrate, and then a p+-type Si layer, p-type Si layer and n+-type Si layer which all make up a solar cell layer. After a protective film is made on the n+-type Si layer, the rear surface of the single-crystal Si substrate is bonded to a tool, and another tool is bonded to the front surface of the protective film. Then, the tools are pulled in opposite directions to mechanically rupture the porous Si layer and to separate the solar cell layer from the single-crystal substrate. The solar cell layer is subsequently sandwiched between two plastic substrates to make a flexible thin-film solar cell.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: October 11, 2011
    Assignee: Sony Corporation
    Inventors: Takeshi Matsushita, Hiroshi Tayanaka