With Separation/delamination Along Porous Layer (epo) Patents (Class 257/E21.57)
  • Patent number: 10141218
    Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: November 27, 2018
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Qin-Yi Tong, Paul M. Enquist, Anthony Scot Rose
  • Patent number: 9514926
    Abstract: Embodiments of the disclosure relate to a substrate recycling method and a recycled substrate. The method includes separating a first surface of a substrate from an epitaxial layer; forming a protective layer on an opposing second surface of the substrate; electrochemically etching the first surface of the substrate; and chemically etching the electrochemically etched first surface of the substrate.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: December 6, 2016
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Su Youn Hong, Joo Won Choi, Jeong Hun Heo, Su Jin Shin, Choong Min Lee
  • Patent number: 9427948
    Abstract: A method for manufacturing a flexible structure including implanting ionic species in first and second source substrates so as to form first and second embrittlement regions respectively, delimiting first and second thin films, providing a flexible substrate, the stiffness R of which is less than or equal to 107 GPa·?m3, securing the first and second thin films to the first and second faces of the flexible substrate respectively so as to form a stack including the flexible structure delimited by the first and second embrittlement regions, the flexible structure having a stiffening effect suitable for allowing transfers of the first and second thin films, and applying a thermal budget so as to transfer the first and second thin films onto the flexible substrate.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 30, 2016
    Assignee: COMMISSARIATE A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Hubert Moriceau, Maxime Argoud, Frank Fournel, Frederic Mazen, Christophe Morales
  • Patent number: 8975749
    Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8969997
    Abstract: A method of forming of a semiconductor structure has isolation structures. A substrate having a first region and a second region is provided. The first region and the second region are implanted with neutral dopants to form a first etching stop feature and a second stop feature in the first region and the second region, respectively. The first etching stop feature has a depth D1 and the second etching stop feature has a depth D2. D1 is less than D2. The substrate in the first region and the second region are etched to form a first trench and a second trench respectively. The first trench and the second trench land on the first etching stop feature and the second etching stop feature, respectively.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chang-Sheng Tsao
  • Patent number: 8951887
    Abstract: The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Soitec
    Inventors: Fabrice Letertre, Didier Landru
  • Patent number: 8895345
    Abstract: The present invention provides a dicing method that achieves excellent dicing properties at low costs by removing a metal film through a metal processing operation with a diamond tool and then performing pulse laser beam irradiation. The dicing method is a method of dicing a substrate to be processed, devices being formed in the substrate to be processed, a metal film being formed on one surface of the substrate to be processed.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: November 25, 2014
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventor: Takanobu Akiyama
  • Patent number: 8890321
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through the trimmed patterned photoresist layer to form a dielectric feature. A sacrificing energy decomposable layer (SEDL) is deposited on the dielectric feature and etched to form a SEDL spacer on sides of the dielectric feature. A second dielectric layer is deposited on the SEDL spacer and etched to form a dielectric spacer. The SEDL spacer is decomposed to form a trench.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao
  • Patent number: 8841203
    Abstract: The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana, Davood Shahrjerdi
  • Patent number: 8822308
    Abstract: A method is disclosed which includes: forming at least one layer of material on at least part of a surface of a first substrate, wherein a first surface of the at least one layer of material is in contact with the first substrate thereby defining an interface; attaching a second substrate to a second surface of the at least one layer of material; forming bubbles at the interface; and applying mechanical force; whereby the second substrate and the at least one layer of material are jointly separated from the first substrate. Related arrangements are also described.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: September 2, 2014
    Assignee: Graphene Frontiers
    Inventor: Bruce Ira Willner
  • Patent number: 8778771
    Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuo Kokumai
  • Patent number: 8728912
    Abstract: The present invention is directed to a method for manufacturing an SOI wafer, the method by which treatment that removes the outer periphery of a buried oxide film to obtain a structure in which a peripheral end of an SOI layer of an SOI wafer is located outside a peripheral end of the buried oxide film, and, after heat treatment is performed on the SOI wafer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, an epitaxial layer is formed on a surface of the SOI layer. As a result, there is provided a method that can manufacture an SOI wafer having a desired SOI layer thickness by performing epitaxial growth without allowing a valley-shaped step to be generated in an SOI wafer with no silicon oxide film in a terrace portion, the SOI wafer fabricated by an ion implantation delamination method.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 20, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Isao Yokokawa, Satoshi Oka
  • Patent number: 8709914
    Abstract: A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 8673740
    Abstract: A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 18, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien Cuzzocrea, Laurent-Luc Chapelon
  • Patent number: 8673739
    Abstract: It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective film that is likely to damage an element if the protective film is formed on the element directly) is previously formed on a heat-resistant substrate other than a substrate with the element formed thereon. The protective film is peeled off from the heat-resistant substrate, and transferred over the substrate with the element formed thereon so as to seal the element.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: March 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Yuugo Goto, Yumiko Fukumoto, Junya Maruyama, Takuya Tsurume
  • Patent number: 8664087
    Abstract: A method of manufacturing a semiconductor structure is disclosed, which includes providing a substrate comprising a bottom surface and a growth surface opposite to the bottom surface; forming a buffer layer comprising a first surface which is not a C-plane substantially parallel with the bottom surface on the growth surface; forming a semiconductor structure on the buffer layer; forming at least one cavity in the buffer layer; extending the cavity along a main extending direction; separating the substrate and the semiconductor structure; wherein the main extending direction is substantially not parallel with the normal direction of the first surface.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: March 4, 2014
    Assignee: EPISTAR Corporation
    Inventors: Shih-Pang Chang, Hung-Chi Yang, Yu-Jiun Shen
  • Patent number: 8653664
    Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8598013
    Abstract: To provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like is used. The semiconductor layer is transferred to a supporting substrate by the steps of irradiating a semiconductor wafer with ions from one surface to form a damaged layer; forming an insulating layer over one surface of the semiconductor wafer; attaching one surface of the supporting substrate to the insulating layer formed over the semiconductor wafer and performing heat treatment to bond the supporting substrate to the semiconductor wafer; and performing separation at the damaged layer into the semiconductor wafer and the supporting substrate. The damaged layer remaining partially over the semiconductor layer is removed by wet etching and a surface of the semiconductor layer is irradiated with a laser beam.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: December 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Yoichi Iikubo, Yoshiaki Yamamoto, Kenichiro Makino
  • Patent number: 8546238
    Abstract: A method for transferring a micro-technological layer includes preparing a substrate having a porous layer buried beneath a useful surface, forming an embrittled zone between it and the surface, bonding the substrate to a supporting substrate, causing detachment at the porous layer by mechanical stress to obtain a first substrate remnant, and a bare surfaced detached layer joined to the supporting substrate, performing technological steps on the bared surface of the detached layer, bonding the detached layer, by the surface to which the technological steps had been applied, to a second supporting substrate, causing detachment, at the embrittled zone, by heat treatment to obtain a detached layer remnant joined to the second supporting substrate, and the detached layer remnant joined to the first supporting substrate.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: October 1, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies
    Inventors: Aurelie Tauzin, Anne-Sophie Stragier
  • Patent number: 8546242
    Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neng-Kuo Chen, Chih-Hsiang Chang, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
  • Patent number: 8530336
    Abstract: Defects in a semiconductor substrate are reduced. A semiconductor substrate with fewer defects is manufactured with high yield. Further, a semiconductor device is manufactured with high yield. A semiconductor layer is formed over a supporting substrate with an oxide insulating layer interposed therebetween, adhesiveness between the supporting substrate and the oxide insulating layer in an edge portion of the semiconductor layer is increased, an insulating layer over a surface of the semiconductor layer is removed, and the semiconductor layer is irradiated with laser light, so that a planarized semiconductor layer is obtained. For increasing the adhesiveness between the supporting substrate and the oxide insulating layer in the edge portion of the semiconductor layer, laser light irradiation is performed from the surface of the semiconductor layer.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Nei, Akihisa Shimomura
  • Patent number: 8501587
    Abstract: Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Jao Sheng Huang
  • Patent number: 8486772
    Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: July 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideki Tsuya, Masaharu Nagai
  • Patent number: 8476146
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: July 2, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
  • Patent number: 8470689
    Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3 or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: June 25, 2013
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien Desplobain, Frederic-Xavier Gaillard, Yves Morand, Fabrice Nemouchi
  • Patent number: 8470690
    Abstract: Method of fabricating a multilayer film having at least one ultrathin layer of crystalline silicon, the film being fabricated from a substrate having a crystalline structure and including a previously-cleaned surface. The method includes the steps of: a) exposing the cleaned surface to a radiofrequency plasma generated in a gaseous mixture of SiF4, hydrogen, and argon, so as to form an ultrathin layer of crystalline silicon having an interface sublayer in contact with the substrate and containing microcavities; b) depositing at least one layer of material on the ultrathin layer of crystalline silicon so as form a multilayer film, the multilayer film including at least one mechanically strong layer; and c) annealing the substrate covered in the multilayer film at a temperature higher than 400° C., thereby enabling the multilayer film to be separated from the substrate.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: June 25, 2013
    Assignees: Centre National de la Recherche Scientifique, Ecole Polytechnique
    Inventors: Pere Roca I Cabarrocas, Mario Moreno
  • Publication number: 20130084687
    Abstract: A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 4, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien CUZZOCREA, Laurent-Luc CHAPELON
  • Publication number: 20130045583
    Abstract: A method for measuring defects in a silicon substrate obtained by silicon ingot pulling, wherein the defects have a size of less than 20 nm. The method includes applying a first defect consolidation heat treatment to the substrate at a temperature of between 750 and 850° C. for a time of between 30 minutes and 1 hour to consolidate the defects; applying a second defect enlargement heat treatment to the substrate at a temperature of between 900 and 1000° C. for a time of between 1 hour and 10 hour to enlarge the defects to a size of greater than or equal to 20 nm, with the enlarged defects containing oxygen precipitates; measuring size and density of the enlarged defects in a surface layer of the substrate; and calculating the initial size of the defects on the basis of the measurements of the enlarged defects.
    Type: Application
    Filed: July 12, 2012
    Publication date: February 21, 2013
    Applicant: SOITEC
    Inventors: Patrick Reynaud, Chirstophe Gourdel
  • Patent number: 8372727
    Abstract: Provided is a method for fabricating a light emitting device. The method includes forming a gallium oxide layer; forming a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the gallium oxide layer; forming a non-conductive substrate on the second conductive type semiconductor layer; separating the gallium oxide layer forming a conductive substrate on the first conductive type semiconductor layer; and separating the non-conductive substrate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: February 12, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Yong Tae Moon
  • Patent number: 8367440
    Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Mayumi Mizukami, Shunpei Yamazaki
  • Patent number: 8367524
    Abstract: A method of forming a semiconductor structure includes coupling a semiconductor structure to an interconnect region through a bonding region. The interconnect region includes a conductive line in communication with the bonding region. The bonding region includes a metal layer which covers the interconnect region. The semiconductor structure is processed to form a vertically oriented semiconductor device.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: February 5, 2013
    Inventor: Sang-Yun Lee
  • Patent number: 8367517
    Abstract: An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideki Tsuya, Yoshihiro Komatsu
  • Patent number: 8314006
    Abstract: Provided is a method for manufacturing a bonded wafer with a good thin film over the entire substrate surface, especially in the vicinity of the lamination terminal point. The method for manufacturing a bonded wafer comprises at least the following steps of: forming an ion-implanted region by implanting a hydrogen ion or a rare gas ion, or the both types of ions from a surface of a first substrate which is a semiconductor substrate; subjecting at least one of an ion-implanted surface of the first substrate and a surface of a second substrate to be attached to a surface activation treatment; laminating the ion-implanted surface of the first substrate and the surface of the second substrate in an atmosphere with a humidity of 30% or less and/or a moisture content of 6 g/m3 or less; and a splitting the first substrate at the ion-implanted region so as to reduce thickness of the first substrate, thereby manufacturing a bonded wafer with a thin film on the second substrate.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: November 20, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Yuji Tobisaka, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Shoji Akiyama, Hiroshi Tamura
  • Patent number: 8288245
    Abstract: An object of an embodiment of the disclosed invention is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: October 16, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Kazuya Hanaoka
  • Patent number: 8278189
    Abstract: The present invention provides a method of thinning a wafer. First, a wafer is provided. The wafer includes an active surface, a back surface and a side surface. The active surface is disposed opposite to the back surface. The side surface is disposed between the active surface and the back surface and encompasses the peripheral of the wafer. Next, a protective structure is formed on the wafer to at least completely cover the side surface. Last, a thinning process is performed upon the wafer from the back surface.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: October 2, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Cheng-Yu Hsieh
  • Patent number: 8258043
    Abstract: A manufacturing method of a thin film semiconductor substrate includes implanting ions at a specified depth into a semiconductor substrate, forming a bubble layer in the semiconductor substrate by vaporizing the ions through heating, bonding an insulating substrate onto the semiconductor substrate, and cleaving the semiconductor substrate along the bubble layer to form a semiconductor thin film on a side of the insulating substrate. At the forming, the semiconductor substrate is heated at a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 ?s to 100 ms. The heating of the semiconductor substrate is performed by using, for example, a light beam.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: September 4, 2012
    Assignees: National University Corporation Tokyo University of Agriculture and Technology, Nissin Ion Equipment Co., Ltd.
    Inventors: Toshiyuki Sameshima, Yutaka Inouchi, Takeshi Matsumoto, Yuko Fujimoto
  • Patent number: 8242021
    Abstract: A method for manufacturing a semiconductor device includes forming a hard mask pattern and a spacer at both sides of the hard mask pattern. The method also includes forming a spacer pattern, so that the spacer remains in one direction to form a spacer pattern, forming a photoresist pattern having a pad type overlapping a side of the spacer pattern, and etching an underlying layer, with the photoresist pattern and the spacer pattern as a mask, to form an isolated pattern. The method improves resolution and process margins to obtain a highly-integrated transistor.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: August 14, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae In Moon
  • Patent number: 8193076
    Abstract: The present disclosure relates to methods and apparatuses template. The method involves forming a mechanically weak layer conformally on a semiconductor template. Then forming a thin for releasing a thin semiconductor substrate from a reusable semiconductor substrate conformally on the mechanically weak layer. The thin semiconductor substrate, the mechanically weak layer and the template forming a wafer. Then defining the border of the thin-film semiconductor substrate to be released by exposing the peripheral of the mechanically weak layer. Then releasing the thin-film semiconductor substrate by applying a controlled air flow parallel to said mechanically weak layer wherein the controlled air flow separates the thin semiconductor substrate and template according to lifting forces.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: June 5, 2012
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang, Sam Tone Tor, Karl-Josef Kramer
  • Patent number: 8187948
    Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.
    Type: Grant
    Filed: February 18, 2008
    Date of Patent: May 29, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neng-Kuo Chen, Chih-Hsiang Chang, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
  • Patent number: 8178426
    Abstract: A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: May 15, 2012
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Yves Morand, Yves Campidelli, Olivier Kermarrec
  • Patent number: 8168481
    Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: May 1, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideki Tsuya, Masaharu Nagai
  • Patent number: 8163599
    Abstract: A flip-chip mounting apparatus has a shield film (18) on the side of a pressurizing film (10b) of a tool protection sheet (10). When a semiconductor chip (1) is heated and pressurized via the tool protection sheet (10), the pressurizing film (10b) is released from a mold by a sheet fixing jig (9), and is expanded by a pressurizing/heating tool (11) to abut against an insulating resin film (5) protruding from the periphery of the semiconductor chip (1) and cure the insulating resin film (5) with an external pressure being applied.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomura, Kentaro Kumazawa, Takayuki Higuchi, Koujiro Nakamura
  • Patent number: 8119499
    Abstract: A semiconductor substrate fabrication method according to the first aspect of this invention is characterized by including a preparation step of preparing an underlying substrate, a stacking step of stacking, on the underlying substrate, at least two multilayered films each including a peeling layer and a semiconductor layer, and a separation step of separating the semiconductor layer.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: February 21, 2012
    Assignees: Tohoku Techno Arch Co., Ltd., Furukawa Co., Ltd., Mitsubishi Chemical Corporation, Dowa Holdings Co., Ltd., Epivalley Co., Ltd., Wavesquare Inc.
    Inventors: Takafumi Yao, Meoung-Whan Cho
  • Patent number: 8101439
    Abstract: The present invention is characterized in that a transistor with its L/W set to 10 or larger is employed, and that |VDS| of the transistor is set equal to or larger than 1 V and equal to or less than |VGS?Vth|. The transistor is used as a resistor so that the resistance of a light emitting element can be held by the transistor. This slows down an increase in internal resistance of the light emitting element and the resultant current value reduction. Accordingly, a change with time in light emission luminance is reduced and the reliability is improved.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: January 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsuaki Osame, Jun Koyama
  • Patent number: 8097523
    Abstract: A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: January 17, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Tohru Ishizuka, Hiroji Aga, Nobuhiko Noto
  • Publication number: 20110309467
    Abstract: Disclosed is a semiconductor device including a substrate for bonding (10a), and a semiconductor element part (25aa) which is bonded to the substrate (10a), and in which an element pattern (T) is formed, wherein in a bonded interface between the substrate (10a) and the semiconductor element part (25aa), recessed portions (23a) are formed in at least one of the substrate (10a) and the semiconductor element part (25aa).
    Type: Application
    Filed: November 25, 2009
    Publication date: December 22, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shin Matsumoto, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Kenshi Tada
  • Patent number: 8058146
    Abstract: The present invention provides a method for manufacturing massively and efficiently a minute device which can receive or send data in contact, preferably, out of contact by forming an integrated circuit which is formed by a thin film over a large glass substrate and by peeling the integrated circuit from the substrate. Especially, an integrated circuit which is formed by a thin film is extremely thin, and so there is a threat that the integrated circuit is flied when transporting, and so handling thereof is difficult. In accordance with the present invention, a separating layer (also referred to as a peeling layer) is damaged at a plurality of times by at least two different kinds of methods (a damage due to laser light irradiation, a damage due to etching, or a damage due to a physical means), subsequently, the layer to be peeled can be efficiently peeled from a substrate. Further, handling of individual devices becomes easy by arching the peeled device.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: November 15, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideaki Kuwabara
  • Patent number: 8053331
    Abstract: Processes for transferring a semiconductor material to a polymer substrate to provide flexible semiconductor material include implanting ions to a predetermined depth in a semiconductor substrate, heat-treating the ion-implanted semiconductor substrate for a period of time and at a temperature effective to cause defect formation and enlargement of the implanted ion defect, adhering the ion-implanted, heat-treated substrate to a polymer substrate, and separating a semiconductor film such as a single crystal silicon film from the semiconductor substrate; and devices having single crystal silicon films disposed directly or indirectly on polymer films.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: November 8, 2011
    Assignee: Corning Incorporated
    Inventor: Kishor P. Gadkaree
  • Patent number: 8048770
    Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yohei Monma, Atsuhiro Tani, Misako Hirosue, Kenichi Hashimoto, Yasuharu Hosaka
  • Patent number: RE45017
    Abstract: A porous Si layer is formed on a single-crystal Si substrate, and then a p+-type Si layer, p-type Si layer and n+-type Si layer which all make up a solar cell layer. After a protective film is made on the n+-type Si layer, the rear surface of the single-crystal Si substrate is bonded to a tool, and another tool is bonded to the front surface of the protective film. Theo, the tools are pulled in opposite directions to mechanically rupture the porous Si layer and to separate the solar cell layer from the single-crystal substrate. The solar cell layer is subsequently sandwiched between two plastic substrates to make a flexible thin-film solar cell.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: July 15, 2014
    Assignee: Sony Corporation
    Inventors: Takeshi Matsushita, Hiroshi Tayanaka