With Particular Manufacturing Method Of Source Or Drain, E.g., Specific S Or D Implants Or Silicided S Or D Structures Or Raised S Or D Structures (epo) Patents (Class 257/E21.619)
  • Patent number: 10573642
    Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 25, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10276570
    Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Hyung-Jong Lee, Sung-Min Kim, Chong-Kwang Chang
  • Patent number: 10269899
    Abstract: An apparatus comprises a first semiconductor fin, a second semiconductor fin and a third semiconductor fin over a substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region and the second semiconductor fin and the third semiconductor fin are separated by a second isolation region, and wherein a width of the first isolation region is greater than a width of the second isolation region.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Blandine Duriez, Martin Christopher Holland
  • Patent number: 10249713
    Abstract: A semiconductor device includes a MOS transistor and an ESD protection element comprised of an NMOS off transistor having a gate potential equal to a ground potential or a well potential. The off transistor has an N-type drain region and a P-type drain region in a drain active region thereof. The P-type region has a potential that is the potential of a P well or a P-type semiconductor substrate. A junction withstand voltage of a PN junction in the drain active region is the withstand voltage of the ESD protection element.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: April 2, 2019
    Assignee: ABLIC Inc.
    Inventor: Hideo Yoshino
  • Patent number: 10096698
    Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 9985015
    Abstract: A semiconductor device includes a semiconductor substrate having a core device and an IO device. The core device includes a gate interface layer and a high-k dielectric layer on the gate interface layer. The IO device includes a gate interface layer and a high-k dielectric layer on the gate interface layer. The gate interface layer of the core device and the gate interface layer of the IO device each are doped with fluoride ions.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: May 29, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Xinyun Xie
  • Patent number: 9893052
    Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng, Han-Jen Yang, Arabinda Das
  • Patent number: 9842943
    Abstract: Provided is a method for manufacturing a semiconductor device including a film to be treated having a high flatness. A semiconductor substrate having a surface and including a first region and a second region on the surface is prepared, the first region being a region in which a plurality of first level difference portions are formed, the second region being a region in which a plurality of second level difference portions arranged more sparsely than the plurality of first level difference portions are formed, or a region in which no level difference portion is formed. A photosensitive film is formed on a portion of the second region to surround a periphery of the first region as seen in plan view. An applied film having flowability is formed to cover the first region and the photosensitive film. A portion of the applied film at least on the first region is removed.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Daisuke Umeda
  • Patent number: 9799769
    Abstract: A semiconductor device includes: a substrate having a first fin-shaped structure and a second fin-shaped structure thereon, a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure, a gate isolation directly on the second fin-shaped structure, and a gate line on the STI and the first fin-shaped structure. Preferably, the gate line includes a L-shaped structure.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Ting Lin
  • Patent number: 9741830
    Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 22, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Patent number: 9698057
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Feng Nieh, Ming-Huan Tsai, Wei-Han Fan, Yimin Huang, Chun-Fai Cheng, Han-Ting Tsai, Chii-Ming Wu
  • Patent number: 9613811
    Abstract: A first protective layer, a mask layer, a second protective layer and a photoresist layer are sequentially formed on a substrate. A photoresist pattern is formed by partially removing the photoresist layer. An ion implantation mask is formed by sequentially etching the second protective layer, the mask layer and the first protective layer using the photoresist pattern. The ion implantation mask exposes the substrate. Impurities are implanted in an upper portion of the substrate exposed by the ion implantation mask.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jik Baek, Sang-Jine Park, Bo-Un Yoon, Young-Sang Youn, Ji-Min Jeong, Ji-Hoon Cha
  • Patent number: 9543387
    Abstract: A semiconductor device includes a gate structure located on a substrate and a raised source/drain region adjacent to the gate structure. The raised source/drain region includes: a first epitaxial-grown doped layer of the raised source/drain region in contact with the substrate; a second epitaxial-grown doped layer on the first epitaxial-grown doped layer and including a same dopant species as the first epitaxial-grown doped layer, wherein the second epitaxial-grown doped layer includes a higher dopant concentration than the first epitaxial-grown doped layer and interfacing the gate structure by using a predetermined distance; and a third epitaxial-grown doped layer on the second epitaxial-grown doped layer and including the same dopant species as the first epitaxial-grown doped layer, wherein the third epitaxial-grown doped layer includes a higher dopant concentration than the second epitaxial-grown doped layer.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Chieh Chang, Ying-Min Chou, Yi-Ming Huang, Wen-Chu Hsiao, Hsiu-Ting Chen, Huai-Tei Yang
  • Patent number: 9520458
    Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung Gil Kang, Dongwon Kim, Ilryong Kim, Changwoo Oh, Keun Hwi Cho, Toshinori Fukai
  • Patent number: 9419089
    Abstract: The present invention provides a semiconductor structure, which includes a substrate, at least two gate structures disposed on the substrate, a first recess, disposed in the substrate between two gate structures, the first recess having a U-shaped cross section profile, and a second recess, disposed on the first recess, the second recess having a polygonal shaped cross section profile, and has at least two tips on two sides of the second recess, the first recess and the second recess forming an epitaxial recess.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: August 16, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Kuang-Hsiu Chen, Ted Ming-Lang Guo, Yu-Ren Wang
  • Patent number: 9349650
    Abstract: A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kevin K. Chan, Yue Ke, Annie Levesque, Dae-Gyu Park, Ravikumar Ramachandran, Amanda L. Tessier, Min Yang
  • Patent number: 8999798
    Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include (a) providing a substrate having a p-type silicon region; (b) depositing a silicon seed layer atop the p-type silicon region; (c) depositing a silicon-containing bulk layer comprising silicon, silicon and a lattice adjusting element or silicon and an n-type dopant atop the silicon seed layer; (d) implanting at least one of the lattice adjusting element or the n-type dopant which is absent from the silicon-containing bulk layer deposited in (c) into the silicon-containing bulk layer; and (e) annealing the silicon-containing bulk layer with an energy beam after implantation in (d). In some embodiments, the substrate may comprise a partially fabricated NMOS transistor device having a source/drain region defined therein.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Mitchell C. Taylor, Susan B. Felch
  • Patent number: 8994003
    Abstract: To provide a power MISFET using oxide semiconductor. A gate electrode, a source electrode, and a drain electrode are formed so as to interpose a semiconductor layer therebetween, and a region of the semiconductor layer where the gate electrode and the drain electrode do not overlap with each other is provided between the gate electrode and the drain electrode. The length of the region is from 0.5 ?m to 5 ?m. In such a power MISFET, a power source of 100 V or higher and a load are connected in series between the drain electrode and the source electrode, and a control signal is input to the gate electrode.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8993390
    Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 31, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
  • Patent number: 8987144
    Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Hans-Juergen Thees
  • Patent number: 8980719
    Abstract: An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Yu-Lien Huang, De-Wei Yu
  • Patent number: 8956937
    Abstract: The present invention discloses to a method of depositing the metal barrier layer comprising silicon dioxide. It is applied in the transistor device comprising a silicon substrate, a gate and a gate side wall. The method comprises the following steps: ions are implanted into the silicon substrate to form an active region in the said silicon substrate; a first dense silicon dioxide film is deposited; a second normal silicon dioxide film is deposited; the said transistor device is high temperature annealed. The present invention ensures that the implanted ion is not separated out of the substrate during the annealing. And it prevents the warping and fragment of the silicon surface.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: February 17, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: GuoFang Xuan, Fei Luo
  • Patent number: 8946037
    Abstract: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ronald Kakoschke, Helmut Tews
  • Patent number: 8946028
    Abstract: FinFETs are merged together by a metal. The method of manufacturing the FinFETs include forming a plurality of fin bodies on a substrate and merging the fin bodies with a metal. The method further includes implanting source and drain regions through the metal.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Zhibin Ren, Xinhui Wang, Keith Kwong Hon Wong
  • Patent number: 8936989
    Abstract: A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: January 20, 2015
    Inventor: Tzu-Yin Chiu
  • Patent number: 8912568
    Abstract: A semiconductor device and manufacturing method therefor includes a ?-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a ?-shaped recess.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Huanxin Liu, Huojin Tu
  • Patent number: 8889510
    Abstract: A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 18, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: De Yuan Xiao, Lily Jiang, Gary Chen, Roger Lee
  • Patent number: 8883651
    Abstract: A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokhoon Kim, Sangsu Kim, Chung Geun Koh, Byeongchan Lee, Sunghil Lee, Jinyeong Joe
  • Patent number: 8877604
    Abstract: A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8877583
    Abstract: In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Young-Pil Kim, Kwan-Heum Lee, Sun-Ghil Lee
  • Patent number: 8853037
    Abstract: Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A plurality of trenches is etched into the first and second layers. Portions of the second layer that are disposed between the plurality of trenches define a plurality of fins. A gate structure is formed overlying the plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is at least partially supported in position adjacent to the gap spaces by the gate structure. The gap spaces are filled with an insulating material.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Jin Cho
  • Patent number: 8842400
    Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: September 23, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Shih-Hung Chen, Kun-Hsien Lin
  • Patent number: 8835995
    Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Patent number: 8836036
    Abstract: A method for fabricating a semiconductor device is presented. The method comprises providing a gate stack including a gate dielectric and gate electrode over a substrate. Stressor regions comprising stressor material incorporated into substitutional sites of the substrate are formed within the substrate on opposed sides of the gate stack. A first stressor layer having a first stress value is formed over the semiconductor device after forming the stressor regions followed by an anneal to memorize at least a portion of the first stress value in the semiconductor device, wherein the anneal is conducted at a low temperature.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: September 16, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Lee Wee Teo
  • Patent number: 8835268
    Abstract: A method for manufacturing a semiconductor device includes forming a mask film on a partial region of a semiconductor substrate; forming a mask member above the semiconductor substrate in both the region where the mask film is formed and a region where the mask film is not formed; patterning the mask film and an upper portion of the semiconductor substrate by performing etching using the mask member as a mask. The method further includes removing part of the patterned upper portion of the semiconductor substrate by performing etching using the patterned mask film as a mask.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Patent number: 8822284
    Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: September 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Patent number: 8815736
    Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Javorka, Stefan Flachowsky, Clemens Fitz
  • Patent number: 8809174
    Abstract: A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machiness Corporation
    Inventors: Soon-Cheon Seo, Bruce B. Doris, Chih-Chao Yang
  • Patent number: 8796788
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
  • Patent number: 8796143
    Abstract: A semiconductor device in which a metal silicide layer is formed by a salicide process is improved in reliability. By a salicide process according to a partial reaction method, metal silicide layers are formed over respective surfaces of gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions. In a first heat treatment when the metal silicide layers are formed, a heat-conduction type anneal apparatus is used for the heat treatment of a semiconductor wafer. In a second heat treatment, a microwave anneal apparatus is used for the heat treatment of the semiconductor wafer, thereby reducing the temperature of the second heat treatment and preventing abnormal growth of the metal silicide layers. Thus, a junction leakage current in the metal silicide layers is reduced.
    Type: Grant
    Filed: November 12, 2011
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tadashi Yamaguchi
  • Patent number: 8791509
    Abstract: In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Patrick Press, Rainer Giedigkeit, Jan Hoentschel
  • Patent number: 8778744
    Abstract: The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 15, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huajie Zhou, Qiuxia Xu
  • Patent number: 8772119
    Abstract: A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 8, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Kuo-Hui Su, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8729607
    Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Itokawa, Akira Hokazono
  • Patent number: 8722545
    Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 13, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Hong-Gap Chua, Yee-Chung Chan, Mei-Yu Muk
  • Publication number: 20140124869
    Abstract: A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Ming Zhu
  • Patent number: 8716090
    Abstract: The present invention provides a manufacturing method for a semiconductor device having epitaxial source/drain regions, in which a diffusion barrier layer of the source/drain regions made of epitaxial silicon-carbon or germanium silicon-carbon are added on the basis of epitaxially growing germanium-silicon of the source/drain regions in the prior art process, and the introduction of the diffusion barrier layer of the source/drain regions prevents diffusion of the dopant in the source/drain regions, thus mitigating the SCE and DIBL effect.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: May 6, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Changliang Qin, Huaxiang Yin
  • Publication number: 20140110783
    Abstract: A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Guowei ZHANG
  • Patent number: 8692335
    Abstract: An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: April 8, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8679928
    Abstract: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Arup Bhattacharyya, Leonard Forbes, Paul A. Farrar