Abstract: A desired property for a metal gate electrode layer is that it can cover a three-dimensional semiconductor structure having a microstructure with high step coverage. Another desired property for the metal gate electrode layer is that the surface of a deposited electrode layer is flat on a nanometer scale, enables a dielectric layer for electrical insulation to be coated without performing special planization after deposition of the electrode layer. Furthermore, another desired property for the metal gate electrode layer is that it has the similar etching workability to materials used in an ordinary semiconductor manufacturing process. Furthermore, another desired property for the metal gate electrode layer is that it has a structure in which diffusion of impurity is suppressed due to homogeneity thereof and the absence of grain boundaries.

Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Abstract: Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and material state in a manner that one of the two gate electrodes has a single-layer structure and the other one has a two-layer structure.

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.

Abstract: A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The method of manufacturing the multi-work function metal gate structure comprises forming a first type of metal with a first work function in a central region and forming a second type of metal with a second work function in at least one edge region adjacent the central region. The first work-function is different from the second work function.

Abstract: A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.

Abstract: Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon body of the memory cell. A layer of a high-k dielectric and at least a metal layer cover the silicon bodies and their overlying layers. Next, gain regions of the transistors are filled with polysilicon. Thus, a gate is formed on the top surface and both sidewalls of a tri-gate transistor. Thereafter, the high-k dielectric and the metal layer overlying the insulative layer of the memory cell are removed to expose the insulative layer. Thus, two electrically-isolated gates of the memory cell are formed.

Abstract: Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V.

Abstract: A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which high power source voltages are supplied contain an impurity at a relatively low concentration, so the gate electrodes are easily depleted at the time of application of the gate voltage; depletion of the gate electrodes is equivalent to increasing the thickness of the gate insulating films; the electrical effective thicknesses required of the gate insulating films can be made thicker; and the gate electrodes of high performance transistors for which a high speed and large drive current are required do not contain an impurity at a high concentration where depletion of the gate electrodes will not occur, so the electrical effective thickness of the gate insulating films

Abstract: A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.

Abstract: A method of fabricating a semiconductor device includes forming a first trench and a second trench on a semiconductor substrate and forming a first metal layer in the first and second trenches. The first metal layer is then removed, at least partially, from within the first trench but not the second trench. A second metal layer and a third metal layer are formed in the first and second trenches.

Abstract: A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to cover the first and second regions and a metal silicide film formed on the polycrystalline silicon film. The polycrystalline silicon film has a P-type part located on the first region and an N-type part coming into contact with the P-type part and located on the second region, and the P-type part is further doped with a heavier element than a P-type impurity that determines a conductivity type of the P-type part.

Abstract: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.

Abstract: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

Abstract: A semiconductor device is disclosed. The device comprises a first MOSFET transistor. The transistor comprises a substrate, a first high-k dielectric layer upon the substrate, a first dielectric capping layer upon the first high-k dielectric, and a first gate electrode made of a semiconductor material of a first doping level and a first conductivity type upon the first dielectric capping layer. The first dielectric capping layer comprises Scandium.

Abstract: The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.

Abstract: A method of manufacturing a dynamic random access memory cell includes: forming a substrate having an insulating region over a conductive region; forming a fin of a fin-type field effect transistor (FinFET) device over the insulating region; forming a storage capacitor at a first end of the fin; and forming a back-gate at a lateral side of the fin. The back-gate is in electrical contact with the conductive region and is structured and arranged to influence a threshold voltage of the fin.

Abstract: A method for manufacturing an EEPROM cell including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with a stack of first and second layers, forming at least one first opening in the second layer, forming, in the first layer, a second opening continuing the first opening, enlarging the first opening by isotropic etching, forming a first doped region in the substrate by implantation through the first enlarged opening, the first doped region taking part in the forming of the transistor drain or source, forming, in the third opening, a thinned-down insulating portion thinner than the first layer, and forming the gates of the MOS transistor at least partially extending over the thinned-down insulating portion.

Abstract: A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation.

Abstract: Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.

Abstract: A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.

Abstract: A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.

Abstract: A first gate, formed on a substrate, is surmounted by a hard layer designed, with first spacers surrounding the first gate, to act as etching mask to bound the channel and a pad that bounds a space subsequently used to form a gate cavity. The hard layer is preferably made of silicon nitride. Before flipping and bonding, a bounding layer, preferably made of amorphous silicon or polysilicon, is formed to bound drain and source areas. After flipping and bonding of the assembly on a second substrate, a second gate is formed in the gate cavity. At least partial silicidation of the bounding layer is then performed before the metal source and drain electrodes are produced.

Abstract: A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.

Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; a first gate dielectric layer provided on the semiconductor substrate, the relative dielectric constant ratio of the first gate dielectric layer being no less than 8; a second gate dielectric layer provided on the semiconductor substrate, the relative dielectric constant ratio of the second gate dielectric layer being no less than 8; a first gate electrode provided on the first gate dielectric layer and made of germanide which is a metallic compound containing a metal element of a rare earth metal; and a second gate electrode provided on the second gate dielectric layer and made of silicide which is a metallic compound containing the same metal element of a rare earth metal as the germanide in the first gate electrode.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

Abstract: In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A flash annealing process is performed on the ion-implanted semiconductor substrate. The metal layer, the conductive layer, and the gate insulating layer are patterned.

Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

Abstract: A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.

Abstract: A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.

Abstract: A method for fabricating a dual poly gate in a semiconductor device is disclosed.

Abstract: An organic thin film transistor includes a dual gate electrode on a substrate, a gate insulating layer on the dual gate electrode, source and drain electrodes on the gate insulating layer, and an organic semiconductor layer on the source and drain electrodes.

Abstract: A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.

Abstract: The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Abstract: Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.

Abstract: A fabrication method for a semiconductor device includes a step of forming a gate insulating film on a semiconductor layer, and a step of forming a first gate electrode layer on the gate insulating film. The fabrication method also includes a step of forming a pocket ion region under the first gate electrode layer, and a step of forming a second gate electrode layer overlaying the first gate electrode layer after forming the pocket ion region.

Abstract: A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.

Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Abstract: A self-aligned gate structure includes a first gate region and a second gate region. The first gate region extends in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions. The first gate region comprises a first conductive material. The second gate region is adjacent to the first gate region and extends above a surface of the semiconductor substrate. The second gate region includes a second conductive material.

Abstract: Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.

Abstract: A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

Abstract: A method of fabricating CMOS transistor is disclosed. Initially, a semiconductor substrate having at least a first active area and a second active area is provided. A high-strained thin film is formed on the semiconductor substrate, the first active area, and the second active area. Thereafter, a mask is formed to cover a part of the high-strained thin film, which is disposed on the first active area. An implantation is performed to implant dopants into the part of the high-strained thin film on the second active area and to modify the stress status thereof. After that, the mask is removed and a rapid thermal annealing process is performed. Then, the high-strained thin film is removed and the method of the present invention is accomplished.

Abstract: Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe simultaneously in first gate electrode source and drain openings. Second gate and second substrate portions are masked. SiGe is removed from an upper surface of the first gate to form a second opening therein. A metal deposited on the first and second gates forms a metal layer thereon. Annealing first and second gates to form FUSI first and second gate electrodes. A metal amount at an interface of the FUSI gate electrode layer and an underlying gate dielectric layer is greater than at a second interface of the second FUSI gate electrode layer and an underlying second gate dielectric layer.

Abstract: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.

Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.

Abstract: The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

Abstract: A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.

Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.