Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.

Abstract: In an insulated trench gate device, polysilicon in the trench is etched below the top surface of the trench, leaving a thin gate oxide layer exposed near the top of the trench. An angled implant is conducted that implants dopants through the exposed gate oxide and into the side of the trench. If the implanted dopants are n-type, this technique may be used to extend an n+ source region to be below the top of the polysilicon in the trench. If the implanted dopants are p?type, the dopants may be used to form a p-MOS device that turns on when the polysilicon is biased with a negative voltage. P-MOS and n-MOS devices can be formed in a single cell using this technique, where turning on the n-MOS device turns on a vertical power switch, and turning on the p-MOS device turns off the power switch.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate oxide layer on the first region, the second region, and the third region; and performing an etching process and an infrared treatment process at the same time to completely remove the first gate oxide layer on the second region for exposing the substrate.

Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

Abstract: A method of making a semiconductor device includes forming a first trench contact over a first source/drain region of a first transistor; forming a second trench contact over a second source/drain region of a second transistor; depositing a first liner material within the first trench contact; and depositing a second liner material within the second trench contact; wherein the first liner material and the second liner material include different materials.

Abstract: Semiconductor fins having isolation regions of different thicknesses on the same integrated circuit are disclosed. Nitride spacers protect the lower portion of some fins, while other fins do not have spacers on the lower portion. The exposed lower portion of the fins are oxidized to provide isolation regions of different thicknesses.

Abstract: The present disclosure provides one embodiment of a field effect transistor (FET) structure. The FET structure includes shallow trench isolation (STI) features formed in a semiconductor substrate; a plurality of semiconductor regions defined in the semiconductor substrate and isolated from each other by the STI features; and a multi-fin active region of a first semiconductor material disposed on one of the semiconductor regions of the semiconductor substrate.

Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.

Abstract: A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

Abstract: A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

Abstract: A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.

Abstract: Methods of forming semiconductor devices are provided. The methods may include forming a gate pattern on an active region of a substrate. The methods may further include performing a deoxidization treatment on the substrate.

Abstract: A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.

Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, first fins on the substrate, isolation regions on sides of the first fins, source/drain features on the substrate and dummy gate stacks separating the source/drain features on the substrate. The dummy gate stack is removed to expose the first fins and then the first fins are recessed to form channel trenches. A channel layer is deposited in the channel trenches and then is recessed. Then the isolation regions are recessed to laterally expose at least a portion of the recessed channel layer to form second fins. A high-k (HK) dielectric layer and a metal gate (MG) layer are deposited on the second fins.

Abstract: The present disclosure provides one embodiment of a field effect transistor (FET) structure. The FET structure includes shallow trench isolation (STI) features formed in a semiconductor substrate; a plurality of semiconductor regions defined in the semiconductor substrate and isolated from each other by the STI features; and a multi-fin active region of a first semiconductor material disposed on one of the semiconductor regions of the semiconductor substrate.

Abstract: An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

Abstract: A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

Abstract: Embodiment of the present invention provides a method of forming transistors such as narrow channel transistors. The method includes creating a transistor region in a substrate; the transistor region being separated from rest of the substrate, by one or more shallow trench isolation (STI) regions formed in the substrate, to include a channel region, a source region, and a drain region; the STI regions having a height higher than the transistor region of the substrate; and the channel region having a gate stack on top thereof; forming spacers at sidewalls of the STI regions above the transistor region; creating recesses in the source region and the drain region with the spacers preserving at least a portion of material of the substrate underneath the spacers along sidewalls of the STI regions; and epitaxially growing source and drain of the transistor in the recesses.

Abstract: A structure and methods of making the structure. The structure includes: first and a second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; a first gate electrode extending over the first semiconductor region and the region of the trench isolation; a second gate electrode extending over the second silicon region and the region of the trench isolation; a trench in the trench isolation; and a strap in the trench connecting the first and second gate electrodes.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region.

Abstract: A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.

Abstract: A method of manufacturing a semiconductor device comprises forming a first insulator in the first area of a substrate and a second insulator formed in a second area of the substrate; forming an etching preventing film extending over the first device region surrounded by the first area and the second device region surrounded by the second area removing the etching preventing film from the first device region and first area forming a first gate insulating film over the first device region while the second device region and the second area are covered by the etching preventing film; removing the etching preventing film over the second device region and the second area forming a second gate insulating film over the second device region; and forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film.

Abstract: A semiconductor device includes a first gate insulating film over a first device region, a second gate insulating film over a second device region, a first gate electrode over the first gate insulating film, a second gate electrode over the second gate insulating film, first source and drain regions in the first device region at both sides of the first gate electrode, second source and drain regions in the second device region at both sides of the second gate electrode, and a memory cell memory cell that further includes a tunnel insulating film formed over a third device region, a floating gate formed over the tunnel insulating film, an insulating film formed over the floating gate, a control gate formed over the tunnel insulating film, and third source and drain regions formed in third device region at both sides of the floating gate and the control gate.

Abstract: A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.

Abstract: A structure and methods of making the structure. The structure includes: first and a second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; a first gate electrode extending over the first semiconductor region and the region of the trench isolation; a second gate electrode extending over the second silicon region and the region of the trench isolation; a trench in the trench isolation; and a strap in the trench connecting the first and second gate electrodes.

Abstract: Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

Abstract: Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.

Abstract: An HDP-CVD process is described, including a deposition step conducted in an HDP-CVD chamber and a pre-heating step that is performed outside of the HDP-CVD chamber before the deposition step and pre-heats a wafer to a temperature higher than room temperature and required in the HDP-CVD process deposition step.

Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.

Abstract: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Abstract: A shallow trench isolation (STI) structure and method for forming the same is provided that reduces defects in a nitride film used as a field oxide mask and variations in pad oxide thickness. Generally, the method involves depositing a nitride over pad oxide on a substrate using plasma enhanced chemical vapor deposition (PECVD), and patterning the PECVD nitride to form a field oxide mask. In certain embodiments, patterning the PECVD nitride involves: (i) forming a patterned resist layer on the PECVD nitride; (ii) etching in a process chamber at least one opening through at least the PECVD nitride; and (iii) stripping the patterned resist layer in-situ in the same process chamber in which the at least one opening was etched through the PECVD nitride using a fluorine based plasma. Other embodiments are also disclosed.

Abstract: A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided.

Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.

Abstract: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

Abstract: A method for fabricating an isolation structure in a memory device includes forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. The method also includes oxidating the surface of the first and second trenches to form a sidewall oxide layer; depositing a tetraethylorthosilicate(TEOS) layer on the sidewall oxide layer; forming a silicon nitride layer and a silicon oxide layer on the TEOS layer; selectively removing portions of the silicon nitride and silicon oxide layers on the second trench to expose a portion of the underlying TEOS layer; coating a flowable insulation layer that fills the first and second trenches; and curing the flowable insulation layer.

Abstract: A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.

Abstract: An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.

Abstract: In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.

Abstract: The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory cell region 10; a device isolation region 20c formed in a trench 24 deeper than the trench 18 in the peripheral circuit region 12; a flash memory cell 46 including a floating gate 32 and a control gate 40 formed on the device region defined by the device isolation region 20a; and transistors 62, 66 formed on the device regions defined by the device isolation region 20c.

Abstract: An enhanced FET capable of controlling current above and below a gate of the FET. The FET is formed on a semiconductor substrate. A source and drain are formed in the substrate (or in a well in the substrate). A first epitaxial layer of similar doping to the source and drain are grown on the source and drain, the first epitaxial layer is thicker than the gate, but not so thick as to cover the top of the gate. A second epitaxial layer of opposite doping is grown on the first epitaxial layer thick enough to cover the top of the gate. The portion of the second epitaxial layer above the gate serves as a body through which the gate controls current flow between portions of the first epitaxial layer over the drain and the source.

Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.