Abstract: Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

Abstract: A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.

Abstract: A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.

Abstract: A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface.

Abstract: A method of forming an integrated circuit device structure having a design rule of less than 0.13 micron. The method includes providing a substrate and forming a pad oxide layer overlying the substrate. The method includes forming a nitride layer overlying the pad oxide layer and patterning the nitride layer and pad oxide layer. A trench structure is formed within a thickness of the substrate using the patterned nitride layer and pad oxide layer as hard mask. The method forms a first thickness of liner oxide within the trench structure using at least thermal oxidation of an exposed region of the trench structure to cover the trench structure. Such thermal oxidation causes a rounding region near corners of the trench structure. The method selectively removes the thickness of liner oxide within the trench structure. The method forms a second thickness of liner oxide within the trench structure using at least thermal oxidation to cover the trench structure.

Abstract: A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.

Abstract: By recessing the isolation structure of a transistor prior to silicidation, the series resistance may be reduced due to the increased amount of metal silicide formed in the vicinity of the isolation structure. By recessing the isolation structure prior to the formation of the gate electrode, an increased degree of poly wrap around may be obtained, thereby increasing the effective channel width.

Abstract: In one embodiment, a method of fabricating one or more transistors in an integrated circuit includes an annealing step prior to a gate oxidation step. The annealing step may comprise a rapid thermal annealing (RTA) step performed prior to a gate oxidation pre-clean step. Among other advantages, the annealing step reduces a step height difference between P-doped and N-doped regions of a field oxide of a shallow trench isolation structure. The shallow trench isolation structure may be separating a PMOS transistor and an NMOS transistor in the integrated circuit.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches for element isolation and a plurality of trenches for alignment mark on a substrate. The substrate has an active region. The method also includes laminating an oxide film on the substrate and over both of the trenches. The method also includes etching the oxide film using a resist mask that masks the element isolation trenches, so that the oxide film laminated in the active region and the oxide film laminated in the alignment mark trenches are removed. The method also includes polishing a surface of the substrate to planarize or smooth the surface of the substrate. Accordingly, those portions of the oxide film which project from the substrate surface are eliminated and the oxide film remains only inside the element isolation trenches. This divides the active region into a plurality of individual active regions for the respective semiconductor elements.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.

Abstract: A method for forming a shallow trench isolation (STI) of a semiconductor device comprises forming a nitride film pattern over a semiconductor substrate having a defined lower structure, etching a predetermined thickness of the semiconductor substrate using the nitride film pattern as a mask to form a trench having a vertical sidewall in a portion of the substrate predetermined to be a device isolation region, performing a plasma treatment process on the sidewall of the trench to form a plasma oxide film, forming an oxide film over the resulting structure to fill the trench, and performing a planarization process over the resulting structure.

Abstract: A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.

Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.

Abstract: A method for manufacturing a semiconductor device includes forming a bulb-type trench separated from a surrounding gate and forming a buried bit line in the bulb-type trench, thereby preventing electric short of a word line and the buried bit line. A semiconductor device includes a vertical pillar formed over a semiconductor substrate, a surrounding gate formed outside the vertical pillar, and a buried bit line separated from the surrounding gate.

Abstract: In this invention, the semiconductor device is provided with a gate electrode formed on a gate insulating film in a region sectioned by an element isolation formed on a semiconductor layer of the first conduction type, and a source region and a drain region of the second conduction type. At least one of the source region and the drain region has a first low concentration region and a high concentration region. Also, the semiconductor device of the present invention is provided with a second low concentration region of the second conduction type between a channel stopper region formed below the element isolation and the source region, and between the channel stopper region and the drain region. The semiconductor layer immediately below the gate electrode projects to the channel stopper region side along the gate electrode, and the semiconductor layer and the channel stopper region make contact with each other.

Abstract: One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.

Abstract: Provided may be a method of manufacturing a semiconductor device. The method may include forming a plurality of isolation patterns including conductive patterns on a semiconductor substrate and forming gaps between the isolation patterns, forming active patterns filling the gaps on the semiconductor substrate, forming a gate insulation layer on the isolation patterns and the active patterns, and forming gate patterns on the gate insulation layer.

Abstract: A method of forming nonvolatile memory devices according to example embodiments of the present invention includes forming a device isolation layer defining active regions in a semiconductor substrate; forming a plurality of transistors on the active regions, the plurality of transistors comprising a pair of adjacent string selection transistors, a pair of adjacent ground selection transistors, and a plurality of memory cell transistors connected in series between the string selection transistors and ground selection transistors; forming a common source line using SEG between a pair of adjacent ground selection transistors so that the common source line has a top surface lower than a top surface of the pair of adjacent ground selection transistors.

Abstract: A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.

Abstract: Methods for forming a contact hole in a semiconductor device are provided. An exposed portion of an isolation layer, which may be generated during a process of forming a borderless contact hole, can be covered with a material similar to that of the substrate.

Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.

Abstract: A method of manufacturing a semiconductor device providing insulation between a plurality of MOS transistors without device isolation regions. The method includes forming a first insulation layer on a substrate, exposing a portion of the substrate by etching the first insulation layer using a resist, growing an epitaxial layer on the exposed portion of the substrate, removing the patterned first insulation layer, and forming transistors on the substrate and epitaxial layer, respectively. The epitaxial layer is grown to a degree that an upper surface of the epitaxial layer is higher than that of the substrate.

Abstract: A semiconductor device includes a device isolation insulating film which is provided in a semiconductor substrate, and an insulated-gate field-effect transistor which is disposed adjacent to the device isolation insulating film in a gate length direction, the insulated-gate field-effect transistor including a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a pair of impurity diffusion layers which are provided spaced apart in the semiconductor substrate in a manner to sandwich the gate electrode, and a redundant impurity diffusion layer which is provided between the device isolation insulating film and one of the pair of impurity diffusion layers.

Abstract: A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherein the at least one shallow trench area includes an opening for exposing a portion of the SOI layer; applying diblock copolymer material over the pad nitride layer and the at least one shallow trench area; annealing the applied copolymer material to form self-organized patterns; and partially etching the shallow trench area using the diblock copolymer material as an etch mask. A semiconductor structures is also described having an isolation structure formed on a SOI layer of a semiconductor substrate the isolation structure having an oxidized substrate region; and a void region formed on the oxidized substrate region.

Abstract: Disclosed herein is a method of manufacturing semiconductor devices. After first isolation trenches are formed in a cell region, second isolation trenches are formed in a peripheral region by an etch process using a photoresist as a mask. As such, top corner portions of an active substrate of the peripheral region are rounded. It is thus possible to fundamentally prevent a hump phenomenon incurred by thinning of the gate oxide film.

Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions.

Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Abstract: In one aspect, the method comprises forming trenches in a semiconductor substrate and filling the trenches with a dielectric material. The process of filling the trenches includes depositing the dielectric material with a plasma gas mixture, etching the dielectric material with a chemical etch including nitrogen fluoride and using a passivation process to passivate the dielectric material after etching with a gas mixture that includes oxygen and hydrogen.

Abstract: A self-aligned gate structure includes a first gate region and a second gate region. The first gate region extends in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions. The first gate region comprises a first conductive material. The second gate region is adjacent to the first gate region and extends above a surface of the semiconductor substrate. The second gate region includes a second conductive material.

Abstract: A buried photodiode with shallow trench isolation technology is formed in a semiconductor substrate of a first conductive type. A trench having a bottom portion and a sidewall portion is formed in the semiconductor substrate. An isolation region is formed on the bottom portion of the trench. A gate structure covers the sidewall portion of the trench. A first doped region of a second conductive type is formed in the semiconductor substrate adjacent to the trench and the gate structure. A second doped region of the first conductive type is formed overlying the first doped region near the surface of the semiconductor substrate.

Abstract: A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the first trench dielectric and along inner surfaces of the trench. A second trench dielectric is deposited on the etch stop layer. The second trench dielectric and the etch stop layer are removed to expose the first trench dielectric in the trench. A conductive layer is formed on the first trench dielectric in the trench, such that the conductive layer, the first trench dielectric and the semiconductor substrate function as a trench capacitor.

Abstract: Disclosed method for forming void-free isolation comprises the steps of: forming a trench in an isolation region in a semiconductor substrate; and forming a filling oxide on the semiconductor substrate to fill the trench. The filling oxide is formed by HDP-CVD process and by using reactant gas mixture that includes O2, SiH4 and He. In an embodiment of the present invention, the formation of the filling oxide is carried out in two-step process which includes: first filling the trench with the filling oxide under the first processing condition that a first D/S value has a greater deposition rate than sputter etching rate; and second filling the trench with the filling oxide under the second processing condition that a second D/S value is smaller than the first D/S value. Here the D/S value is defined as “(net deposition rate+blanket sputter etching rate)/(blanket sputter etching rate)”.

Abstract: A semiconductor device is formed by providing a substrate. A trench is formed in the substrate. Beveled surfaces are formed at upper portions of sidewalls of the trench opposite a bottom surface of the trench, respectively. An oxide layer is formed in the trench such that the oxide layer is thicker on the beveled surfaces of the trench than on other surfaces of the trench.

Abstract: A semiconductor device includes: a semiconductor substrate; a separation region in the substrate; an embedded layer; a channel forming region; a source region; a drain region; a first electrode for the source region; a second electrode for the channel forming region; a third electrode for the drain region; a trench penetrating the channel forming region between the source region and the drain region; a trench gate electrode in the trench; an offset layer on a portion to be a current path provided by the trench gate electrode; and an electric field relaxation layer under the channel forming region and the offset layer connected to the channel forming region and covering a bottom of the trench.

Abstract: A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed.

Abstract: A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.

Abstract: A semiconductor device includes an active region and a dummy active region formed in a semiconductor substrate to have a distance from each other, an isolation region formed between the active region and the dummy active region and has a top surface lower than top surfaces of the active region and the dummy active region, a gate insulating film formed on the active region and a fully silicided gate electrode formed on the isolation region, the gate insulating film and the dummy active region through full silicidation of a silicon gate material film with metallic material.

Abstract: A semiconductor device includes a semiconductor substrate that has an oxide film selectively formed on a part thereof; a semiconductor layer that is formed on the oxide film by epitaxial growth; a first gate electrode that is formed on the semiconductor layer; first source/drain layers that are formed on the semiconductor layer so as to be disposed at both sides of the first gate electrode, respectively; a second gate electrode that is formed on the semiconductor substrate; and second source/drain layers that are formed on the semiconductor substrate so as to be disposed at both sides of the second gate electrode, respectively.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region of the semiconductor substrate; a fully silicided first gate line formed on the active region; a fully silicided second gate line formed on the isolation region; a first sidewall formed on a side of the first gate line; a second sidewall formed on a side of the second gate line. The length between the top and bottom surfaces of the first sidewall is different from that between the top and bottom surfaces of the second sidewall.

Abstract: A semiconductor device includes a MISFET, the MISFET having a shallow trench insulator (STI) formed in a surface layer of a semiconductor substrate to define a device forming region, a gate electrode formed above the device forming region via a gate insulating film, impurity diffusion layers composing a source and a drain formed in the surface layer of the device forming region using SiGe so as to sandwich the gate electrode, and a first metal silicide formed on the surfaces of the impurity diffusion layers. The surface height of the STI is substantially the same as the height of the first metal silicide.

Abstract: In fabrication of a semiconductor device which is provided with resistances and MOS transistors on the same substrate, preventing conduction failures of contacts and preventing leaching of wiring metal into a silicon substrate. Firstly, an underlying structure is prepared. Then, a silicon oxide layer is formed on the underlying structure. Then, a silicon nitride layer is formed on the silicon oxide layer. Then, an inter-layer insulation layer is formed on the silicon nitride layer. Then, a contact hole is formed penetrating through a laminate of the silicon oxide layer, the silicon nitride layer and the inter-layer insulation layer. A thickness of the silicon oxide layer is a value in a range from 32 to 48 nm.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the semiconductor device.

Abstract: A semiconductor device is formed with a lower field plate (32) and optional lateral field plates (34) around semiconductor (20) in which devices are formed, for example power FETs or other transistor or diode types. The semiconductor device is manufactured by forming trenches with insulated sidewalls, etching cavities (26) at the base of the trenches which join up and then filling the trenches with conductor (30).

Abstract: A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.