With Particular Manufacturing Method Of Gate Insulating Layer, E.g., Different Gate Insulating Layer Thicknesses, Particular Gate Insulator Materials Or Particular Gate Insulator Implants (epo) Patents (Class 257/E21.639)
  • Patent number: 11107689
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: August 31, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shi-You Liu, Tsai-Yu Wen, Ming-Shiou Hsieh, Rong-Sin Lin, Ching-I Li, Neng-Hui Yang
  • Patent number: 10748816
    Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming an isolation layer in the base substrate; forming dummy gate structures on the base substrate at two sides of the isolation layer; forming an additional gate structure on the isolation layer and a first protective layer on surfaces of the additional gate structure and the dummy gate structures; forming an interlayer dielectric layer covering side surfaces of the dummy gate structures, the additional gate structure and the first protective layer over the base substrate; removing a portion of the first protective layer over the additional gate structure; forming a second protective layer on the additional gate structure; removing portions of the first protective layer over the dummy gate structures using the second protective layer as a mask; and removing the dummy gate structures to form openings in the interlayer dielectric layer.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 18, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10714396
    Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10373835
    Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Robert H. Dennard, Martin M. Frank
  • Patent number: 10263091
    Abstract: A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Chih Chieh Yeh, Chih-Hsin Ko, Cheng-Hsien Wu, Liang-Yin Chen, Xiong-Fei Yu, Yen-Ming Chen, Chan-Lon Yang
  • Patent number: 10050147
    Abstract: A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Sheng Liang, Shih-Hsun Chang
  • Patent number: 10026653
    Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 9941128
    Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Robert H. Dennard, Martin M. Frank
  • Patent number: 9893060
    Abstract: A semiconductor device includes a substrate, a core device, and an input/output (I/O) device. The core device is disposed on the substrate. The core device includes a first gate electrode having a bottom surface and at least one sidewall. The bottom surface of the first gate electrode and the sidewall of the first gate electrode intersect to form a first interior angle. The I/O device is disposed on the substrate. The I/O device includes a second gate electrode having a bottom surface and at least one sidewall. The bottom surface of the second gate electrode and the sidewall of the second gate electrode intersect to form a second interior angle greater than the first interior angle of the first gate electrode.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9809881
    Abstract: Embodiments of the present invention provide a method and apparatus for plasma processing a substrate to form a film on the substrate and devices disposed thereon by controlling the ratio of ions to radicals in the plasma at a given pressure. A given pressure may be maintained to promote ion production using one plasma source, and a second plasma source may be used to provide additional radicals. In one embodiment, a low pressure plasma is generated in a processing region having the substrate positioned therein, and a high pressure plasma is generated in separate region. Radicals from the high pressure plasma are injected into the processing region having the low pressure plasma, thus, altering the natural distribution of radicals to ions at a given operating pressure.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: November 7, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Matthew Scott Rogers, Zhong Qiang Hua, Christopher S. Olsen
  • Patent number: 9627544
    Abstract: A method of forming a semiconductor device is disclosed. At least one suspended first semiconductor nanowire and two first semiconductor blocks at two ends of the first semiconductor nanowire are formed in a first area, and at least one suspended second semiconductor nanowire and two second semiconductor blocks at two ends of the second semiconductor nanowire are formed in a second area. A transforming process is performed, so the first semiconductor nanowire is transformed into a nanowire with stress, and the second semiconductor blocks are simultaneously transformed into two blocks with stress. First and second gate dielectric layers are formed respectively on surfaces of the nanowire with stress and the second semiconductor nanowire. First and second gates are formed respectively across the nanowire with stress and the second semiconductor nanowire.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: April 18, 2017
    Assignee: United Microelectronics Corp.
    Inventor: Po-Yu Yang
  • Patent number: 9628081
    Abstract: An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: April 18, 2017
    Assignee: XILINX, INC.
    Inventors: Praful Jain, Michael J. Hart
  • Patent number: 9466492
    Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: October 11, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Robert H. Dennard, Martin M. Frank
  • Patent number: 9041116
    Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Steven J. Holmes, Ali Khakifirooz, Pranita Kulkarni, Shom Ponoth, Raghavasimhan Sreenivasan, Stefan Schmitz
  • Patent number: 9034709
    Abstract: A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: May 19, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Shogo Katsuki, Toshiro Sakamoto
  • Patent number: 8987080
    Abstract: Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xinliang Lu, Seshadri Ganguli, Atif Noori, Maitreyee Mahajani, Shih Chung Chen, Yu Lei, Xinyu Fu, Wei Tang, Srinivas Gandikota
  • Patent number: 8980703
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: March 17, 2015
    Assignee: Maxchip Electronics Corp.
    Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
  • Patent number: 8952458
    Abstract: A semiconductor device includes a substrate having a first active region, a first gate structure over the first active region, wherein the first gate structure includes a first interfacial layer having a convex top surface, a first high-k dielectric over the first interfacial layer, and a first gate electrode over the first high-k dielectric.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yang Lee, Xiong-Fei Yu, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 8941184
    Abstract: A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: January 27, 2015
    Assignees: International Business Machines Corporation, Global Foundries, Inc.
    Inventors: Takashi Ando, Changhwan Choi, Kisik Choi, Vijay Narayanan
  • Patent number: 8901674
    Abstract: A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Keith Kwong Hon Wong, Dechao Guo, Unoh Kwon, Christopher Carr Parks, Yun-Yu Wang
  • Patent number: 8823110
    Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: September 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Shimamoto, Jiro Yugami, Masao Inoue, Masaharu Mizutani
  • Patent number: 8809148
    Abstract: A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 19, 2014
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter Wung Lee, Fu-Chang Hsu
  • Patent number: 8778750
    Abstract: A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.
    Type: Grant
    Filed: May 5, 2012
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Eduard Albert Cartier, Michael P. Chudzik, Andreas Kerber, Siddarth Krishnan, Naim Moumen
  • Patent number: 8759131
    Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
  • Patent number: 8735244
    Abstract: A method of forming a dielectric stack devoid of an interfacial layer includes subjecting an exposed interfacial layer provided on a semiconductor material to a low pressure thermal anneal process for a predetermined time period at a temperature of about 900° C. to about 1000° C. with an inert gas purge. A semiconductor structure is also disclosed, with a dielectric stack devoid of an interfacial layer.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Min Dai
  • Patent number: 8728925
    Abstract: Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 20, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, William K. Henson, Unoh Kwon
  • Patent number: 8716807
    Abstract: A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Eduard A. Cartier, Martin M. Frank, Marwan H. Khater
  • Patent number: 8716074
    Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Witold Maszara, Hemant Adhikari
  • Patent number: 8685815
    Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8664066
    Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Pal, Stephan-Detlef Kronholz
  • Patent number: 8617954
    Abstract: Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: December 31, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Manoj Mehrotra
  • Patent number: 8597995
    Abstract: A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate, source and drain features on the semiconductor substrate, and a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes an interfacial layer (IL) layer, a high-k (HK) dielectric layer formed over the semiconductor substrate, an oxygen scavenging metal formed on top of the HK dielectric layer, a scaling equivalent oxide thickness (EOT) formed by using a low temperature oxygen scavenging technique, and a stack of metals gate layers deposited over the oxygen scavenging metal layer.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: December 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jeff J. Xu
  • Publication number: 20130313643
    Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Applicant: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Steven J. Holmes, Ali Khakifirooz, Pranita Kulkarni, Shom Ponoth, Raghavasimhan Sreenivasan, Stefan Schmitz
  • Patent number: 8569812
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 29, 2013
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David L. Kencke, Ibrahim Ban
  • Patent number: 8563444
    Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a silicon source chemical, metal source chemical, and an oxidizing agent, wherein the metal source chemical is the next reactant provided after the silicon source chemical. Methods according to some embodiments can be used to form silicon-rich hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surface.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: October 22, 2013
    Assignee: ASM America, Inc.
    Inventors: Chang-Gong Wang, Eric Shero, Glen Wilk
  • Publication number: 20130270647
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Jin-Aun Ng, Chi-Wen Liu
  • Patent number: 8552507
    Abstract: A p-type MIS transistor Qp arranged in a pMIS region Rp of a silicon substrate 1 includes a pMIS gate electrode GEp formed so as to interpose a pMIS gate insulating film GIp formed of a first insulating film z1 and a first high-dielectric film hk1, and an n-type MIS transistor Qn arranged in an nMIS region Rn includes an nMIS gate electrode GEn formed so as to interpose an nMIS gate insulating film GIn formed of a first insulating film z1 and a second high-dielectric film hk2. The first high-dielectric film hk1 is formed of an insulating film mainly made of hafnium and oxygen with containing aluminum, titanium, or tantalum. Also, the second high-dielectric film hk2 is formed of an insulating film mainly made of hafnium, silicon, and oxygen with containing an element of any of group Ia, group IIa, and group IIIa.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: October 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Jiro Yugami
  • Patent number: 8546271
    Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: October 1, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Yoshitaka Yokota, Norman Tam, Balasubramanian Ramachandran, Martin John Ripley
  • Patent number: 8546211
    Abstract: Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Keith Kwong Hon Wong, Michael P. Chudzik, Unoh Kwon
  • Publication number: 20130249010
    Abstract: Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: Jin-Aun Ng, Ming Zhu, Chi-Wen Liu
  • Patent number: 8541275
    Abstract: A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sivananda Kanakasabapathy, Hemanth Jagannathan, Matthew Copel
  • Patent number: 8536005
    Abstract: Various methods are proposed for forming a gate insulation film, a metal gate layer, and others separately in an N-channel region and a P-channel region of an integrated circuit device having a CMIS or CMOS structure using a metal gate. One of the problems of the methods however has been that the process becomes complex. The present invention is that, in a manufacturing method of a CMOS integrated circuit device, a titanium-based nitride film for adjusting the electrical properties of a high-permittivity gate insulation film before a gate electrode film is formed includes a lower film containing a comparatively large quantity of titanium and an upper film containing a comparatively large quantity of nitrogen in an N-channel region and a P-channel region.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Maruyama, Masao Inoue
  • Patent number: 8530286
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 10, 2013
    Assignee: SuVolta, Inc.
    Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang
  • Patent number: 8524554
    Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: September 3, 2013
    Assignees: IMEC, Samsung Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hag-Ju Cho, Anabela Veloso, HongYu Yu, Stefan Kubicek, Shou-Zen Chang
  • Patent number: 8513076
    Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 8501558
    Abstract: Manufacturing technique for a semiconductor device having a first MISFET of an n channel-type and a second MISFET of a p channel type, including forming a first insulating film composed of a silicon oxide film or a silicon oxynitride film on a semiconductor substrate for forming a gate insulating film of the respective MISFETs; depositing metal elements on the first insulating film; forming of a silicon film on the first insulating film for the forming of a gate electrode of the respective MISFETs; and producing the respective gate electrodes by patterning the silicon film. The depositing of the metal films on the first insulating film is such that there is produced in the vicinity of the interface between the gate electrode and the gate insulating film a surface density of the metal elements within a range of 1×1013 to 5×1014 atoms/cm2.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: August 6, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Shimamoto, Jiro Yugami, Masao Inoue, Masaharu Mizutani
  • Patent number: 8487384
    Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: July 16, 2013
    Assignee: Fujitsu Limited
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Keiji Watanabe
  • Patent number: 8445344
    Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: May 21, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Richard Carter, Falk Graetsch, Martin Trentzsch, Sven Beyer, Berthold Reimer, Robert Binder, Boris Bayha
  • Patent number: 8440521
    Abstract: A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: May 14, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Naomi Fukumaki, Eiji Hasegawa, Toshihiro Iizuka, Ichiro Yamamoto
  • Patent number: 8435848
    Abstract: A process of forming a CMOS integrated circuit including integrating SiGe source/drains in the PMOS transistor after source/drain and LDD implants and anneals. A dual layer hard mask is formed on a polysilicon gate layer. The bottom layer prevents SiGe growth on the polysilicon gate. The top layer protects the bottom layer during source/drain spacer removal. A stress memorization layer may be formed on the integrated circuit prior to a source/drain anneal and removed prior to forming a SiGe blocking layer over the NMOS. SiGe spacers may be formed on the PMOS gate to laterally offset the SiGe recesses.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: May 7, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Manoj Mehrotra