Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first stack of a pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET). which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The IFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Abstract: System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment comprises manufacturing an integrated circuit, comprising forming a trench in an integrated circuit substrate, forming a cavity within the integrated circuit substrate, wherein the cavity is linked to the trench, depositing a dielectric layer within the cavity, and depositing polycrystalline silicon over the dielectric layer, wherein an inherent stress is induced in the polycrystalline silicon that grows on the dielectric layer. The dielectric layer may be, for example, silicon aluminum oxynitride (SiAlON), mullite (3Al2O3.2SiO2), and alumina (Al2O3).

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

Abstract: In the method of forming a mask structure, a first mask is formed on a substrate where the first mask includes a first mask pattern having a plurality of mask pattern portions having openings therebetween and a second mask pattern having a corner portion of which an inner side wall that is curved. A sacrificial layer is formed on the first mask. A hard mask layer is formed on the sacrificial layer. After the hard mask layer is partially removed until the sacrificial layer adjacent to the corner portion is exposed, a second mask is formed from the hard mask layer remaining in the space after removing the sacrificial layer. A minute pattern having a fine structure may be easily formed on the substrate.

Abstract: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. The method includes an independent work function adjustment process that implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants Lanthanide series dopants into a gate polysilicon layer of NMOS.

Abstract: A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A HfAlOx film and a polycrystalline silicon layer are laminated on the substrate. A gate electrode is formed by patterning the polycrystalline silicon layer. After a n-type extension region is formed by implanting arsenic ions by using the gate electrode as a mask, sidewall spacers are formed on sides of the gate electrode. Arsenic ions are implanted by using the sidewall spacers and the gate electrode as masks, whereby n-type source/drain regions are formed.

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO2 or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high dielectric constant of least seven or greater (also referred to as a high-k dielectric) is deposited on the interfacial oxide. The high-k dielectric is covered with a thin monolayer of metal oxide (i.e., aluminum oxide, Al2O3) that is removed from the NMOS regions, but remains in the PMOS regions. The resulting NMOS transistor diffusion regions contain predominately metal to silicon bonds that create predominately Fermi level pinning near the valence band while the resulting PMOS transistor diffusion regions contain metal to silicon bonds that create predominately Fermi level pinning near the conduction band.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).

Abstract: Disclosed herein is a method of manufacturing a gate insulator and a thin film transistor (“TFT”) incorporating the gate insulator, including forming an oxygen-containing, conductive gate on a substrate; forming a gate insulator material layer on the substrate so as to cover the gate; and applying a heat treatment so as to diffuse oxygen from the oxygen-containing gate layer into the gate insulating material layer thereby forming the gate insulator.

Abstract: The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region through a first resist opening portion of a first resist pattern; forming a second gate insulating film in the second active region; forming on the silicon substrate a second resist pattern having a second resist portion larger than the first resist opening portion; wet-etching the first gate insulating film of the third active region through a second resist opening portion of the second resist pattern; and forming a third gate insulating film in the third active region.

Abstract: A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas of the substrate for future isolation regions of the semiconductor device. Portions of the substrate are removed in the areas for future isolation regions, thereby forming two or more trenches. A second mask layer is formed overlying a first portion of the hard mask layer and at least one first trench, and a second portion of the hard mask layer and at least one second trench are left uncovered. Additional substrate material is removed from the at least one second trench so that the at least one second trench is deeper than the at least one first trench. The hard mask layer and the second mask are removed substantially concurrently.

Abstract: Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.

Abstract: A substrate-processing apparatus (100, 40) comprises a radical-forming unit (26) for forming the nitrogen radicals and oxygen radicals through a high-frequency plasma, a processing vessel (21) in which a substrate (W) to be processed is held, and a gas-supplying unit (30) which is connected to the radical-forming unit. The gas-supplying unit (30) controls the mixture ratio between a first raw material gas containing the nitrogen and a second raw material gas containing oxygen, and supplies a mixture gas of a desired mixture ratio to the radical-forming unit. By supplying the nitrogen radicals and oxygen radicals mixed at the controlled mixture ratio to the surface of the substrate, an insulating film having a desired nitrogen concentration is formed on the surface of the substrate.

Abstract: A method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer is provided to prevent degradation of gate dielectric properties due to plasma-induced charges. In the method, the oxide layer is thermally grown on a silicon substrate under oxygen gas atmosphere to have a first thickness, and then the oxy-nitride layer is thermally grown on the oxide layer under nitrogen monoxide gas atmosphere to have a second thickness smaller than the first thickness. The substrate may have a high voltage area and a low voltage area, and the oxide layer may be partially etched in the low voltage area so as to have a reduced thickness. The oxy-nitride layer behaves like a barrier, blocking the inflow of the plasma-induced charges.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.

Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Abstract: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, in a semiconductor substrate; simultaneously forming a second well in the LV/MV region for a logic device and a drift region for one of the HV devices using the same mask; and respectively forming gate oxide layers on the semiconductor substrate in the HV/MV/LV regions. According to the present invention, the number of photolithography processes can be reduced by replacing or combining an additional mask for forming an extended drain region of a high voltage depletion-enhancement CMOS (DECMOS) with a mask for forming a typical well of a logic device, so productivity of the total process of the device can be enhanced.

Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Abstract: A CMOS device is provided which comprises (a) a substrate (103); (b) a gate dielectric layer (107) disposed on the substrate, the gate dielectric comprising a metal oxide; (c) an NMOS electrode (105) disposed on a first region of said gate dielectric; and (d) a PMOS electrode (115) disposed on a second region of said gate dielectric, the PMOS electrode comprising a conductive metal oxide; wherein the surface of said second region of said gate dielectric comprises a material selected from the group consisting of metal oxynitrides and metal silicon-oxynitrides.

Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

Abstract: Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxides formed from elements such as yttrium and gadolinium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

Abstract: Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset D2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

Abstract: Numerous methods for forming various semiconductor structures are disclosed. In one embodiment, a layered dielectric structure of alternating sub-layers of a first dielectric material and a second dielectric material is formed on a suitable semiconductor substrate. In this embodiment, the layered dielectric structure comprises an alternating pattern of at least two sub-layers of a first dielectric material which is a high-K dielectric material and at least one layer of a second dielectric material which is a standard-K dielectric material, wherein at least one of the one or more second dielectric material sub-layers contain nitrogen implanted therein using a nitridation step.

Abstract: A process for forming a hafnium oxide-containing film on a substrate such as silicon that includes introducing an anhydrous hafnium nitrate-containing precursor into a reactor containing the substrate, and converting the precursor into the hafnium oxide-containing film on the substrate by chemical vapor deposition.