Isolation Region Manufacturing Related Aspects, E.g., To Avoid Interaction Of Isolation Region With Adjacent Structure (epo) Patents (Class 257/E21.642)
  • Patent number: 9337205
    Abstract: The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Tzyh-Cheang Lee
  • Patent number: 8912055
    Abstract: Disclosed are methods for forming hybrid metal-oxide-semiconductor field effect transistors (MOSFETs) and the hybrid MOSFETS thus obtained. In one embodiment, a method is disclosed that includes providing a first substrate comprising a first region and a second region, providing a second substrate comprising a second semiconductor layer and an insulating layer overlaying the second semiconductor layer, and direct substrate bonding the second substrate to the first substrate, thereby contacting the first region and the second region with the insulating layer. The method further includes selectively removing the second semiconductor layer and the insulating layer in the first region, thereby exposing the first semiconductor layer in the first region, forming a first gate stack of a first MOSFET on the exposed first semiconductor layer in the first region, and forming a second gate stack of a second MOSFET on the second semiconductor layer in the second region.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: December 16, 2014
    Assignee: IMEC
    Inventors: Thomas Y. Hoffman, Matty Caymax, Niamh Waldron, Geert Hellings
  • Patent number: 8901690
    Abstract: A semiconductor structure for photon detection, comprising a substrate composed of a semiconductor material having a first doping, a contact region fitted at the frontside of the substrate, a bias layer composed of a semiconductor material having a second doping, which is arranged on the backside of the substrate at a distance from the contact region, wherein the contact region at least partly lies opposite the bias layer, such that an overlap region is present in a lateral direction, a guard ring, which is arranged at the frontside of the substrate and surrounds the contact region, wherein a reverse voltage can be applied between the contact region and the guard ring. In order to enable more cost-effective production, the overlap region has a lateral extent amounting to at least one quarter of the distance between contact region and bias layer.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: December 2, 2014
    Assignee: ESPROS Photonics AG
    Inventors: Martin Popp, Beat De Coi, Marco Annese
  • Patent number: 8884375
    Abstract: A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: November 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Nakai, Masato Suga, Jusuke Ogura
  • Patent number: 8778752
    Abstract: A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: July 15, 2014
    Assignee: Fujitu Semiconductor Limited
    Inventor: Yasunobu Torii
  • Patent number: 8772127
    Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: July 8, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huicai Zhong, Huilong Zhu, Zhijiong Luo
  • Patent number: 8685830
    Abstract: A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: April 1, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Fan Chen, Xiongbin Chen, Kai Xue, Keran Zhou, Jia Pan, Hao Li, Yongcheng Wang
  • Patent number: 8679938
    Abstract: A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sunfei Fang, Oleg Gluschenkov, Byeong Y. Kim, Rishikesh Krishnan, Daewon Yang
  • Patent number: 8673724
    Abstract: Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Doo-Sung Yun, Bo-Un Yoon, Jeong-Nam Han
  • Publication number: 20130175614
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device includes a substrate having a first region including a first element and a second region including a second element and including a lower substrate and an upper substrate bonded to each other, an epitaxial layer and an insulating layer disposed between the lower substrate and the upper substrate, the epitaxial layer disposed in the first region, and the insulating layer disposed in the second region, a device isolation pattern separating the first element from the second element, and a doped pattern disposed between the upper substrate and the insulating layer and between the upper substrate and the epitaxial layer. The first element is electrically connected to the lower substrate through the doped pattern and the epitaxial layer. The second element is electrically insulated from the lower substrate by the doped pattern and the insulating layer.
    Type: Application
    Filed: September 10, 2012
    Publication date: July 11, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: KYOUNG IL NA
  • Publication number: 20130102117
    Abstract: One embodiment relates to a method of semiconductor manufacture. In this method, a strain inducing layer is formed over a p-type field effect transistor structure and an n-type field effect transistor structure. The strain inducing layer is removed from over the p-type field effect transistor while the strain inducing layer over the n-type field effect transistor is left in place. A treatment of the strain inducing layer over the n-type field effect transistor is performed after the strain-inducing layer has been removed from over the p-type field effect transistor.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventor: Kai-Shiung Hsu
  • Patent number: 8404537
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Patent number: 8338919
    Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Shigeo Satoh
  • Patent number: 8299538
    Abstract: Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: October 30, 2012
    Assignee: Internantional Business Machines Corporation
    Inventors: Brent A. Anderson, Suk Hoon Ku, Edward J. Nowak
  • Publication number: 20120205749
    Abstract: Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 16, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashima B. Chakravarti, Abhishek Dube, Dominic J. Schepis
  • Patent number: 8232178
    Abstract: A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S11); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S12); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S13); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S14). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: July 31, 2012
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu
  • Publication number: 20120178227
    Abstract: A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.
    Type: Application
    Filed: March 22, 2012
    Publication date: July 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Haining S. Yang
  • Publication number: 20120025319
    Abstract: In one embodiment, a method of providing a semiconductor device is provided, in which instead of forming isolation regions before the formation of the semiconductor devices, the isolation regions are formed after the semiconductor devices. In one embodiment, the method includes forming a semiconductor device on a semiconductor substrate. A placeholder dielectric is formed on a portion of a first surface of the substrate adjacent to the semiconductor device. A trench is etched into the substrate from a second surface of the substrate that is opposite the first surface of the substrate, wherein the trench terminates on the placeholder dielectric. The trench is filled with a dielectric material.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huilong Zhu, Qingqing Liang, Zhijiong Luo, Haizhou Yin
  • Patent number: 8102030
    Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: January 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Shigeo Satoh
  • Patent number: 8097503
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: January 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Patent number: 8053303
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kerry Bernstein, Francis R. White
  • Patent number: 8053305
    Abstract: The invention provides a method for producing a semiconductor device that can reduce the number of mask steps. In a CMOS production process, gate electrodes are formed in regions for forming an NMOS and a PMOS at the same time with a common mask pattern, and after the gate electrodes have been formed, a well, and source and drain regions are formed by impurity ion implantations with a common mask pattern in each region of the NMOS and the PMOS, using the gate electrode as a mask, whereby the number of mask steps is reduced.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: November 8, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiko Yanagi
  • Patent number: 8039338
    Abstract: By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Manfred Horstmann, Peter Javorka, Karsten Wieczorek, Kerstin Ruttloff
  • Patent number: 8003458
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: August 23, 2011
    Assignee: Infineon Technologies AG
    Inventors: Frank Huebinger, Richard Lindsay
  • Patent number: 7998811
    Abstract: A semiconductor device includes a semiconductor substrate, a memory cell region provided on the semiconductor substrate, a word line provided on the memory cell region, a first gate insulating film provided in the memory cell region beneath the word line, a first floating gate electrode provided on the first gate insulating film, a second gate insulating film provided in the memory cell region beneath the word line, the second gate insulating film being different from the first gate insulating film in thickness, and a second floating gate electrode provided on the second gate insulating film.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Takahashi
  • Patent number: 7981800
    Abstract: A shallow trench isolation (STI) structure and method for forming the same is provided that reduces defects in a nitride film used as a field oxide mask and variations in pad oxide thickness. Generally, the method involves depositing a nitride over pad oxide on a substrate using plasma enhanced chemical vapor deposition (PECVD), and patterning the PECVD nitride to form a field oxide mask. In certain embodiments, patterning the PECVD nitride involves: (i) forming a patterned resist layer on the PECVD nitride; (ii) etching in a process chamber at least one opening through at least the PECVD nitride; and (iii) stripping the patterned resist layer in-situ in the same process chamber in which the at least one opening was etched through the PECVD nitride using a fluorine based plasma. Other embodiments are also disclosed.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: July 19, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Geethakrishnan Narasimhan, Mehran Sedigh
  • Patent number: 7943455
    Abstract: CMOS image sensors and methods of fabricating the same. The CMOS image sensors include a pixel array region having an active pixel portion and an optical block pixel portion which encloses the active pixel portion. The optical block pixel portion includes an optical block metal pattern for blocking light. The optical block metal pattern may be connected to a ground portion.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ui-sik Kim
  • Patent number: 7932143
    Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: April 26, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Rohit Pal, Michael Hargrove, Frank Bin Yang
  • Publication number: 20110086473
    Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane <110> direction of the (011) DSB layer is aligned with an in-plane <110> direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane <100> directions of the (001) base substrate, followed by recrystallization using the base substrate as a template.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Haizhou Yin, John A. Ott, Katherine L. Saenger, Chun-Yung Sung
  • Publication number: 20110084324
    Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 14, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Emily Ann Donnelly, Byron Neville Burgess, Randolph W. Kahn, Todd Douglas Stubblefield
  • Publication number: 20110086478
    Abstract: Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
    Type: Application
    Filed: December 14, 2010
    Publication date: April 14, 2011
    Inventors: Kleanthes G. Koniaris, Robert Paul Masleid, James B. Burr
  • Patent number: 7910423
    Abstract: A semiconductor device includes an SOI substrate, a first STI-type isolation region, a second STI-type isolation region, and an alignment mark region. The SOI substrate includes a support substrate, an insulating layer deposited on the support substrate, and a semiconductor layer which includes a thin film region and a thick film region. The thin film region includes a first semiconductor layer deposited on the support substrate, and the thick film region includes the first semiconductor layer and a second semiconductor layer deposited on a part of the first semiconductor layer. The first STI-type isolation region is disposed at the thin film region. The second STI-type isolation region is disposed at the thick film region. The alignment mark region is disposed at the thick film region. An alignment mark to be used for alignment of the second STI-type isolation region is disposed at the alignment mark region.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: March 22, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Shinji Ohara
  • Patent number: 7902020
    Abstract: A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from th
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: March 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Il-Yong Park
  • Patent number: 7902037
    Abstract: A method for fabricating an isolation structure in a memory device includes forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. The method also includes oxidating the surface of the first and second trenches to form a sidewall oxide layer; depositing a tetraethylorthosilicate(TEOS) layer on the sidewall oxide layer; forming a silicon nitride layer and a silicon oxide layer on the TEOS layer; selectively removing portions of the silicon nitride and silicon oxide layers on the second trench to expose a portion of the underlying TEOS layer; coating a flowable insulation layer that fills the first and second trenches; and curing the flowable insulation layer.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: March 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Byung Soo Eun
  • Publication number: 20110053325
    Abstract: The invention provides a method for producing a semiconductor device that can reduce the number of mask steps. In a CMOS production process, gate electrodes are formed in regions for forming an NMOS and a PMOS at the same time with a common mask pattern, and after the gate electrodes have been formed, a well, and source and drain regions are formed by impurity ion implantations with a common mask pattern in each region of the NMOS and the PMOS, using the gate electrode as a mask, whereby the number of mask steps is reduced.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 3, 2011
    Inventor: Masahiko Yanagi
  • Patent number: 7892929
    Abstract: A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai, Jeffrey Junhao Xu
  • Patent number: 7880261
    Abstract: An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: February 1, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Ann Gabrys
  • Publication number: 20110006372
    Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
    Type: Application
    Filed: July 12, 2010
    Publication date: January 13, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Mark Helm, Xianfeng Zhou
  • Patent number: 7868413
    Abstract: It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: January 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Okuda, Toshio Kumamoto
  • Publication number: 20100327335
    Abstract: Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 30, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kamel BENAISSA, Greg C. BALDWIN
  • Patent number: 7858467
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Publication number: 20100317165
    Abstract: A method for forming a bipolar junction transistor comprises forming a first well of a second conductive type for forming a collector region in a substrate including device isolation layers, wherein the substrate comprises a first conductive type, forming a second well of the first conductive type for a metal-oxide-semiconductor transistor of the second conductive type within the first well of the second conductive type, wherein the second well of the first conductive type is formed deeper than the device isolation layers, forming a shallow third well of the first conductive type for a base region within the first well of the second conductive type, wherein the shallow third well of the first conductive type is formed shallower than the device isolation layers, and simultaneously forming an emitter region within the shallow third well of the first conductive type and a plurality of collector contacts within the first well of the second conductive type by performing an ion implantation process for forming sour
    Type: Application
    Filed: June 4, 2010
    Publication date: December 16, 2010
    Inventor: JE-DON KIM
  • Patent number: 7846789
    Abstract: A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: December 7, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, John Lin, Philip L. Hower, Steven L. Merchant
  • Patent number: 7842577
    Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: November 30, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ka-Hing Fung
  • Patent number: 7838355
    Abstract: Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Suk Hoon Ku, Edward J. Nowak
  • Patent number: 7824999
    Abstract: A CMOS device with polysilicon protection tiles is shown in FIG. 2. LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18, respectively. On the upper surface of the LOCOS regions 12.1, 12.2 are polysilicon tiles 14.1, 14.2, respectively. At the corner of the gate polysilicon 14.3 and the polysilicon tiles 14.1 and 14.2 are oxide spacers 60.1-60.6. The polysilicon tiles 14.1, 14.2 have silicide layers 50.1, 50.2. Other silicide layers 50.4-50.6 are on the tops of the source, drain and polysilicon gate. An insulation layer 32 covers the substrate and metal contacts 36, 34, 38 extend from the surface of the layer 32 to the silicide layers on the source, gate and drain, respectively. The polysilicon tiles are made from the same layer of polysilicon as the gate and they are formed simultaneously with the gates. The intention of the polysilicon tiles is to reduce erosion of the field oxide between closely spaced active regions.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: November 2, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Steven Leibiger, Daniel J. Hahn
  • Publication number: 20100240177
    Abstract: A method of manufacturing a semiconductor device includes, forming an isolation region defining a first region and a second region, injecting a first impurity of a first conductivity type into the first region and the second region, forming a first gate insulating film and a first gate electrode over the first region, forming a second gate insulating film and a second gate electrode over the second region, forming a first mask layer over a first portion of the second region to expose a second portion of the second region and the first region, and injecting a second impurity of the first conductivity type into the semiconductor substrate from a direction diagonal to a surface of the semiconductor substrate.
    Type: Application
    Filed: February 12, 2010
    Publication date: September 23, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Masashi Shima
  • Publication number: 20100203691
    Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.
    Type: Application
    Filed: April 14, 2010
    Publication date: August 12, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
  • Patent number: 7772027
    Abstract: Embodiments of the invention provide a barrier region for isolating devices of an image sensor. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region is adjacent to at least one pixel cell of a pixel array. The charge accumulation region accumulates charge and prevents charge transference from a pixel cell or peripheral circuitry on one side of the barrier region to a pixel cell on another side of the barrier region.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: August 10, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Howard E. Rhodes, Richard A. Mauritzson, William T. Quinlin
  • Publication number: 20100197090
    Abstract: Provided is a method of fabricating a semiconductor device having a transistor. The method includes forming a first gate trench in a first active region of a semiconductor substrate. A first gate layer partially filling the first gate trench is formed. Ions may be implanted in the first gate layer and in the first active region on both sides of the first gate layer such that the first gate layer becomes a first gate electrode of a first conductivity type and first impurity regions of the first conductivity type are formed on both sides of the first gate electrode.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 5, 2010
    Inventor: Young-Mok Kim