Abstract: A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer in which a capacitive lower electrode of the DRAM is formed and in a layer or above the layer in which the bitline is formed. For example, the cross couple connection of the SRAM is formed in a same layer as a capacitive contact.

Abstract: The present invention relates to a method of forming contact plugs of a semiconductor device. According to the method, a first insulating layer is formed over a semiconductor substrate in which a cell region and a peri region are defined and a first contact plug is formed in the peri region. The first insulating layer is etched using an etch process, thus forming contact holes through which junctions are exposed in the cell region and the first contact plug is exposed in the peri region. Second contact plugs are formed in the contact holes. The second contact plug formed within the contact hole of the peri region are removed using an etch process. A spacer is formed on sidewalls of the contact holes. Third contact plugs are formed within the contact holes.

Abstract: A semiconductor memory device capable of preventing bridge formations in a peripheral circuit region includes: a cell region; a peripheral circuit region adjacent to the cell region; and a plurality of line patterns formed in the cell region and the peripheral circuit region, wherein a spacing distance between the line patterns is at least onefold greater than a width of the line pattern.

Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.

Abstract: A semiconductor device includes a lower conductive layer formed on a semiconductor substrate, an interlayer insulating film that at least substantially covers the lower conductive layer, a plurality of contact holes formed in the interlayer insulating film to expose an upper surface of the lower conductive layer so that at least some of the contact holes are closer to each other in a long-axis direction than in a short-axis direction; and contact plugs that plug the contact holes. Upper portions of at least some of the contact holes have an oval shape or shapes. A method of manufacturing the semiconductor device includes forming the lower conductive layer, forming the interlayer insulating film, forming the plurality of contact holes in the interlayer insulating film to expose the upper surface of the lower conductive layer, and plugging the contact holes to form the contact plugs.

Abstract: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.

Abstract: A method of fabricating a semiconductor memory device and a structure that forms both a resistor and an etching protection layer to reduce a contact resistance. The method of fabricating a semiconductor memory device according to the invention includes forming an insulation layer on a semiconductor substrate having a cell array region, a core region, and a peripheral region, each having at least one transistor formed therein, and forming both a first landing pad in the core region on the insulation layer and a second landing pad in the peripheral region, the first landing pad being overlapped with a part of a first conductive line. The invention reduces the contact resistance and prevents or minimizes a device failure caused by a misalignment, with the simplified process.

Abstract: A manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure is disclosed. The method includes forming a peripheral circuitry in a peripheral device region, wherein the peripheral circuitry includes a peripheral transistor at least partially formed in the semiconductor substrate and having a first gate dielectric formed in a first high temperature process step. The method further includes forming a plurality of memory cells in a memory cell region, each of said memory cells including an access transistor at least partially formed in a semiconductor substrate and having a second gate dielectric formed in a second high temperature process step and having a metallic gate conductor. The first and second high temperature process steps are performed before a step of forming the metallic gate conductor.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved.

Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.

Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Abstract: Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After gate spacers are formed on sidewalls of the gate patterns, an ion implantation process that uses the gate patterns and the gate spacers as an ion mask is performed to form a plug doped region in a portion of the semiconductor substrate that is located below the wide opening. At this point, the gate spacers are formed to expose a portion of a bottom surface of the wide opening and to fill a lower portion of the narrow opening.

Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned. In this case, the silicon film is patterned to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area.

Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate as ring oscillators increasing the effective circuit frequency of the test module allowing higher frequency circuit testing, and shortening the time it takes to perform life cycle testing. Visibly marking cells, combined with electrically isolating error prone circuit segments makes, identifying defects much more efficient. The accessibility of many testing methods allows quick location of root cause failures, which allows improvements to be made to the manufacturing process.

Abstract: The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.

Abstract: A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.

Abstract: Methods of making memory devices/cells are disclosed. A memory cell contains first and second electrode layers and a controllably conductive media therebetween. The controllably conductive media contains a copper sulfide-containing passive layer and active layer containing a Cu-doped tantalum oxide and/or titanium oxide layer. Methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.

Abstract: A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

Abstract: A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacitor formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation film covering the transistor and is electrically connected to the transistor; a bit contact which is formed on a second interlayer insulation film provided on the first interlayer insulation film and is electrically connected to the cell contact; a bit line which is formed on the second interlayer insulation film and is connected to the bit contact; a capacitor which is formed on a third interlayer insulation film covering the bit line; a capacitor contact which is formed through the third and second interlayer insulation film and makes a connection between the capacitor and the cell contact; and a side wall which has an etching selectivity with the second and third interlayer insulation films formed on the surface of the bit line.

Abstract: A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical embodiment, the diffusion regions are formed at the bottom of the trenches and the tops of the mesas formed by the trenches. An enriched region is formed in the substrate adjacent to and substantially surrounding each diffusion region in the substrate. Each enriched region has a matching conductivity type with the substrate. A gate insulator stack is formed over the substrate and each of the plurality of select gates. A word line is formed over the gate insulator stack.

Abstract: A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. From these layers, the gate electrodes in the memory region are formed, the source and drain regions are implanted and the memory region is covered in a planarizing manner with an insulation material. Afterward, the gate electrodes are formed from the semiconductor layer and the gate dielectric in the logic region.

Abstract: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

Abstract: An integrated circuit device is formed by forming a resistor pattern on a substrate. An interlayer dielectric layer is formed on the resistor pattern. The interlayer dielectric layer is patterned to form at least one opening that exposes the resistor pattern. A plug pattern is formed that fills the at least one opening and the plug pattern and resistor pattern are formed using a same material.

Abstract: In a nonvolatile semiconductor memory device having a memory cell array region and a strap region for providing voltage to the memory cell array region, in the memory cell array region, a plurality of word lines and a plurality of source lines are formed in a row direction, and one source line is formed between two word lines. In the strap region, the word lines and the source lines extend in the row direction and are collinear with, and without separation from, the word lines and the source lines of the memory cell array region, and each of the word lines and the source lines has a word line contact and a source line contact.

Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Abstract: Methods of forming dynamic random access memories (DRAM) are described. In one embodiment, an insulative layer is formed over a substrate having a plurality of conductive lines which extend within a memory array area and a peripheral area outward of the memory array. Capacitor container openings and contact openings are contemporaneously etched over the memory array and conductive line portions within the peripheral area respectively. In another embodiment, a patterned masking layer is formed over a substrate having a plurality of openings formed within an insulative layer, wherein some of the openings comprise capacitor container openings within a memory array and other of the openings comprise conductive line contact openings disposed over conductive lines within a peripheral area outward of the memory array.

Abstract: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.

Abstract: Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 1017 cm?3.