Substrate Is Nonsemiconductor Body, E.g., Insulating Body (epo) Patents (Class 257/E21.704)
  • Patent number: 8987071
    Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 24, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Min-Cheng Chen, Chang-Hsien Lin, Chia-Yi Lin, Tung-Yen Lai, Chia-Hua Ho
  • Patent number: 8987048
    Abstract: An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroyuki Miyake, Hideaki Kuwabara
  • Patent number: 8946005
    Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je-Hun Lee, Do-Hyun Kim, Eun-Guk Lee, Chang-Oh Jeong
  • Patent number: 8815654
    Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Gauthier, Jr., Junjun Li, Souvick Mitra, Mahmoud A Mousa, Christopher S. Putnam
  • Patent number: 8791459
    Abstract: An array substrate for a display device includes an insulation substrate, a gate line formed on the insulation substrate, a data line crossing the gate line to define a pixel area, a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode, a passivation layer covering the gate line, the data line and the thin film transistor and including a drain contact hole to expose the drain electrode, and a pixel electrode formed on the pixel area and being connected to the drain contact hole through the drain contact hole. Each of the data line, the source electrode and the drain electrode includes a lower layer having copper and an upper layer covering upper and side surfaces of the lower layer, and the upper layer is thinner than the lower layer.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 29, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Tae-Hyoung Moon, Kyu-Hwang Lee, Kyung-Ha Lee
  • Patent number: 8729550
    Abstract: An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroyuki Miyake, Hideaki Kuwabara
  • Patent number: 8716800
    Abstract: Semiconductor structure and methods for manufacturing the same are disclosed.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: May 6, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Haizhou Yin, Zhijong Luo, Qingqing Liang
  • Patent number: 8685806
    Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Junedong Lee, Dominic J. Schepis
  • Patent number: 8629504
    Abstract: An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8598664
    Abstract: Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Yu Zhu
  • Patent number: 8597991
    Abstract: A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8535996
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 17, 2013
    Assignee: SOITEC
    Inventors: Mohamad Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karin Landry, Carlos Mazure
  • Publication number: 20130221441
    Abstract: Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Vamsi K. Paruchuri
  • Patent number: 8507330
    Abstract: A method is proposed for producing a thin-film transistor (TFT), the method comprising forming a substrate, applying a ZnO-based precursor solution onto the substrate to form a ZnO-based channel layer, annealing the channel layer, forming a source electrode and a drain electrode on the channel layer, forming a dielectric layer on the channel layer and forming a gate electrode on the dielectric layer.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: August 13, 2013
    Assignee: Sony Corporation
    Inventors: Chunmei Wang, Wei Beng Ng, Takehisa Ishida
  • Publication number: 20130178021
    Abstract: A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.
    Type: Application
    Filed: September 13, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo CHENG, Bruce DORIS, Ali KHAKIFIROOZ, Ghavam G. SHAHIDI
  • Publication number: 20130168771
    Abstract: A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8470680
    Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: June 25, 2013
    Assignees: Kemet Electronics Corporation, Motorola, Inc.
    Inventors: John D. Prymak, Chris Stolarski, Alethia Melody, Antony P. Chacko, Gregory J. Dunn
  • Patent number: 8445965
    Abstract: A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8440523
    Abstract: A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a structure composed of a silicon layer disposed over an insulating layer that is disposed on a silicon substrate. The silicon layer is differentiated into a partially released region that will function as a portion of the electro-mechanical device. The method further includes forming a dielectric layer over the silicon layer; forming a hardmask over the dielectric layer, the hardmask being composed of hafnium oxide; opening a window to expose the partially released region; and fully releasing the partially released region using a dry etching process to remove the insulating layer disposed beneath the partially released region while using the hardmask to protect material covered by the hardmask. The step of fully releasing can be performed using a HF vapor.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: May 14, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael A Guillorn, Fei Liu, Ying Zhang
  • Publication number: 20130095619
    Abstract: Embodiment of the present invention provides a method of forming transistors such as narrow channel transistors. The method includes creating a transistor region in a substrate; the transistor region being separated from rest of the substrate, by one or more shallow trench isolation (STI) regions formed in the substrate, to include a channel region, a source region, and a drain region; the STI regions having a height higher than the transistor region of the substrate; and the channel region having a gate stack on top thereof; forming spacers at sidewalls of the STI regions above the transistor region; creating recesses in the source region and the drain region with the spacers preserving at least a portion of material of the substrate underneath the spacers along sidewalls of the STI regions; and epitaxially growing source and drain of the transistor in the recesses.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Deepal Wehella-Gamage, Viorel Ontalus
  • Patent number: 8420467
    Abstract: A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Nobutoshi Aoki
  • Publication number: 20130087855
    Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.
    Type: Application
    Filed: September 15, 2012
    Publication date: April 11, 2013
    Inventors: Hideki MAKIYAMA, Yoshiki YAMAMOTO
  • Publication number: 20130056827
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu
  • Patent number: 8390084
    Abstract: The MEMS sensor according to the present invention includes a diaphragm.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: March 5, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Goro Nakatani, Mizuho Okada, Nobuhisa Yamashita
  • Patent number: 8389976
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Arijit Raychowdhury, Ali Keshavarzi, Juanita Kurtin, Vivek De
  • Publication number: 20130049119
    Abstract: The present invention provides a multi-working voltages CMOS device with single gate oxide layer thickness, gate work functions of CMOS transistors are regulated by implanting ions with different work functions into metal oxide dielectric material layers of the CMOS transistors, thus to realize different flat-band voltages under the condition of single dielectric layer thickness, and realize a multi-working voltages CMOS structure under the condition of single dielectric layer thickness. The present invention overcomes the process complexity of multiple kinds of gate dielectric layer thicknesses needed by traditional multi-working voltages CMOS, simplifies the CMOS process, makes the manufacturing procedure simple and easy to execute, reduces the preparation cost and is suitable for industrial production.
    Type: Application
    Filed: December 29, 2011
    Publication date: February 28, 2013
    Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Xiaolu HUANG, Gang MAO, Yuwen CHEN, Xinyun XIE
  • Patent number: 8377743
    Abstract: A method of annealing a metal oxide on a temperature sensitive substrate formation includes the steps of providing a temperature sensitive substrate formation and forming a spacer layer on a surface of the substrate formation. A metal oxide semiconductor device is formed on the spacer layer, the device includes at least a layer of amorphous metal oxide semiconductor material, an interface of the amorphous metal oxide layer with a dielectric layer, and a gate metal layer adjacent the layer of amorphous metal oxide semiconductor material and the interface. The method then includes the step of at least partially annealing the layer of metal oxide semiconductor material by heating the adjacent gate metal layer with pulses of infra red radiation to improve the mobility and operating stability of the amorphous metal oxide semiconductor material while retaining at least the amorphous metal oxide semiconductor material adjacent the gate metal layer amorphous.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 19, 2013
    Assignee: CBRITE Inc.
    Inventors: Chan-Long Shieh, Hsing-Chung Lee
  • Patent number: 8373228
    Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: February 12, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Bin Yang, Rohit Pal, Michael Hargrove
  • Patent number: 8367485
    Abstract: A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20130026567
    Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.
    Type: Application
    Filed: October 8, 2012
    Publication date: January 31, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Patent number: 8334538
    Abstract: A thin film transistor array panel includes: an insulation substrate; a gate line disposed on the insulation substrate and including a compensation pattern protruding from the gate line; a first data line and a second data line both intersecting the gate line; a first thin film transistor connected to the gate line and the first data line; a second thin film transistor connected to the gate line and the second data line; and a first pixel electrode and a second pixel electrode connected to the first thin film transistor and the second thin film transistor, respectively. The first pixel electrode and the second pixel electrode share the compensation pattern.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ho-Jun Lee, Yeo-Geon Yoon, Hyoung-Wook Lee, Mi-Ae Lee
  • Patent number: 8293590
    Abstract: An active matrix substrate 40 according to the present invention includes a conductive film 44 and a wiring 80 for supplying a signal to the conductive film 44, characterized in that the wiring 80 includes a first conductive layer 61 and a second conductive layer 62 having a relatively large line width in comparison with the first conductive layer 61 and laminated so as to cover the first conductive layer 61, and the conductive film 44 is arranged in a matrix pattern, and at least a portion of the conductive film 44 is disposed overlapping the wiring 80.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 23, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hideaki Sunohara
  • Patent number: 8294211
    Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: October 23, 2012
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Bin Yang, Rohit Pal, Michael Hargrove
  • Publication number: 20120256242
    Abstract: An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 11, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8273629
    Abstract: The present invention, provides a semiconductor device including a substrate including a semiconductor layer overlying an insulating layer, wherein a back gate structure is present underlying the insulating layer and a front gate structure on the semiconductor layer; a channel dopant region underlying the front gate structure of the substrate, wherein the channel dopant region has a first concentration present at an interface of the semiconductor layer and the insulating layer and at least a second concentration present at the interface of the front gate structure and the semiconductor layer, wherein the first concentration is greater than the second concentration; and a source region and drain region present in the semiconductor layer of the substrate.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Geng Wang, Paul C. Parries
  • Patent number: 8273614
    Abstract: To reduce variation among TFTs in manufacture of a semiconductor device including n-type thin film transistors and p-type thin film transistors. Further, another object of the present invention is to reduce the number of masks and manufacturing steps, and manufacturing time. A method of manufacturing a semiconductor device includes forming an island-shaped semiconductor layer of a first thin film transistor, then, forming an island-shaped semiconductor layer of the second thin film transistor. In the formation of the island-shaped semiconductor layer of the second thin film transistor, a gate insulating film in contact with the island-shaped semiconductor layer of the second thin film transistor is used as a protection film (an etching stopper film) for the island-shaped semiconductor layer of the first thin film transistor.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kunio Hosoya, Saishi Fujikawa
  • Publication number: 20120217614
    Abstract: In one aspect, the present invention relates generally to integrated circuit (IC) packages and more specific to some embodiments of IC power convertor technologies. In particular, IC packages that have a high degree of scalability to handle high voltage or current levels, good heat dissipation properties, flexible adaptability to generate packages operable at a wide range of current levels and having a wide range of power adaptability, lends itself to rapid inexpensive prototyping, the ability to adapt various substrates and IC devices to one another without extensive retooling or custom designing of components, as well as other advantages.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 30, 2012
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Lajos Burgyan, Marc Davis-Marsh
  • Patent number: 8232599
    Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
  • Publication number: 20120171821
    Abstract: A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 5, 2012
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Publication number: 20120168866
    Abstract: A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.
    Type: Application
    Filed: January 3, 2011
    Publication date: July 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8178924
    Abstract: A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate is provided. A first buried dielectric layer interposed between the first buried patterns and the substrate and between the first buried patterns and the first active patterns is provided.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: May 15, 2012
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park
  • Patent number: 8178877
    Abstract: Disclosed are a thin film transistor having high reliability and providing a simplified fabricating process, and a method of fabricating the thin film transistor. In the method, a dielectric substrate is prepared, a semiconductor layer is formed on the dielectric substrate, a gate dielectric film is formed on the semiconductor layer, a first gate electrode is formed on the gate dielectric film, a second gate electrode contacting a side wall of the first gate electrode is formed, and impurities are implanted into the semiconductor layer using the first gate electrode as a mask.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: May 15, 2012
    Assignee: SNU R & DB Foundation
    Inventors: Sun Jae Kim, Min Koo Han
  • Publication number: 20120112284
    Abstract: A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8138031
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from the Fins, the gate electrode is common in the Fins on the gate insulation film; implanting an impurity into portions of the Fins by using the gate electrode as a mask to form a source-drain diffusion layer, the portions of the Fins extending on both sides of the gate electrodes; and depositing a conductive material on both sides of the Fins to connect the Fins to each other.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: March 20, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Yagishita
  • Publication number: 20120012933
    Abstract: A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORAPORATION
    Inventors: KANGGUO CHENG, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Publication number: 20120007181
    Abstract: A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region.
    Type: Application
    Filed: July 12, 2010
    Publication date: January 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Dechao Guo, Marwan H. Khater, Christian Lavoie, Zhen Zhang
  • Publication number: 20120007054
    Abstract: A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Dechao Guo, Shu-Jen Han, Chung-Hsun Lin
  • Publication number: 20120007051
    Abstract: Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.
    Type: Application
    Filed: July 6, 2010
    Publication date: January 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy Cohen, Michael A. Guillorn
  • Patent number: 8088670
    Abstract: When manufacturing a bonded substrate using an insulator substrate as a handle wafer, there is provided a method for manufacturing a bonded substrate which can be readily removed after carried and after mounted by roughening a back surface of the bonded substrate (corresponding to a back surface of the insulator substrate) and additionally whose front surface can be easily identified like a process of a silicon semiconductor wafer in case of the bonded substrate using a transparent insulator substrate as a handle wafer. There is provided a method for manufacturing a bonded substrate in which an insulator substrate is used as a handle wafer and a donor wafer is bonded to a front surface of the insulator substrate, the method comprises at least that a sandblast treatment is performed with respect to a back surface of the insulator substrate.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: January 3, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Publication number: 20110316061
    Abstract: Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph ERVIN, Jeffrey B. JOHNSON, Kevin MCSTAY, Paul C. PARRIES, Chengwen PEI, Geng WANG, Yanli ZHANG