Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package.

Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: Provided are a method of manufacturing a thin film transistor (TFT) substrate and a method of manufacturing an organic light emitting display apparatus, which increase the capacitance of a capacitor without increasing the probability of short circuits between wires. The method of manufacturing a TFT substrate includes (a) forming a capacitor electrode and a gate electrode on a substrate having a first region and a second region, so that the capacitor electrode is formed to correspond to the first region and the gate electrode is formed in a portion of the second region; (b) forming an interlayer insulating layer to cover the gate electrode and the capacitor electrode; and (c) etching a portion of the interlayer insulating layer in the first region by using a halftone mask to a thickness that is less than a thickness of a portion of the interlayer insulating layer in the second region.

Abstract: Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced.

Abstract: Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.

Abstract: A semiconductor device includes: an insulating layer; a semiconductor layer formed on the insulating layer; a first partially depleted transistor formed in the semiconductor layer; and a first diode formed in the semiconductor layer, wherein the first transistor has a first gate electrode formed above the semiconductor layer via an insulating film and a first source or a first drain of a first conductivity type formed in the semiconductor layer below both sides of the gate electrode, the first diode has a first impurity layer of a second conductivity type formed in a shallow portion of the semiconductor layer and a second impurity layer of the first conductivity type formed in a deep portion of the semiconductor layer, the first impurity layer and the second impurity layer are stacked in a depth direction of the semiconductor layer, and a side surface of the first impurity layer and a side surface of the second impurity layer are in contact with the semiconductor layer in a region just below the first gate el

Abstract: A MOSFET on SOI device includes an upper region having at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first conductive layer and a first portion of a second semi-conductor layer. A lower region includes at least one second MOSFET type semi-conductor device formed on a second portion of the second semi-conductor layer, a gate of the second semi-conductor device being formed by at least one conductive portion. The second semi-conductor layer is arranged on a second dielectric layer stacked on a second conductive layer.

Abstract: A mask that is capable of forming a thin-film transistor (TFT) with improved electrical characteristics is presented. The mask includes a drain mask pattern, a source mask pattern and a light-adjusting pattern. The drain mask pattern blocks light for forming a drain electrode. The source mask pattern blocks light for forming a source electrode and faces the drain mask pattern. A distance between the drain and source mask patterns is no more than the resolution of an exposing device. The light-adjusting pattern is formed between end portions of the source mask pattern and the drain mask pattern to block at least some light from entering a space between the source and drain mask patterns.

Abstract: Methods and apparatus for producing a semiconductor on glass (SOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing at least one cleaved surface; subjecting the at least one cleaved surface to an amorphization ion implantation process at a dose sufficient to amorphize at least some depth of the semiconductor material below the at least one cleaved surface; and re-growing the amorphized portion of the semiconductor material into a substantially single crystalline semiconductor layer using solid phase epitaxial re-growth

Abstract: A single crystal semiconductor layer is provided over a base substrate with a second insulating film, a first conductive film, and a first insulating film interposed therebetween; an impurity element having one conductivity type is selectively added to the single crystal semiconductor layer, using a first resist mask; the first resist mask is removed; a second conductive film is formed over the single crystal semiconductor layer; a second resist mask having a depression is formed over the second conductive film; a first etching is performed on the first insulating film, the first conductive film, the second insulating film, the single crystal semiconductor layer, and the second conductive film, using the second resist mask; and a second etching with accompanying side-etching is performed on a part of the first conductive film to form a pattern of a gate electrode layer.

Abstract: An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about ?70° to about +70°.

Abstract: Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process.

Abstract: A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second <110> crystal orientation perpendicular to the curre

Abstract: Including a process for forming a fin 12a having a first height and a fin 12b having a second height lower than the first height, a process for forming a silicon oxide film on the upper and side faces of each of the fins 12a and 12b, a process for forming a conductive poly silicon film on the silicon oxide film, a process for forming a gate insulating film 15 and a gate electrode 16 on from the upper face to the side face of each of the fins 12a and 12b by patterning the silicon oxide film and the poly silicon film, and a process for forming a couple of diffusion regions 14 in two regions clipping a region underneath the gate electrode of each of the fins 12a and 12b. According to the present invention, a semiconductor device manufacturing method and a semiconductor device including a fin-type FET having capability of changing the design of the gate width corresponding to an application can be realized.

Abstract: A method of fabricating a semiconductor device having a capacitorless one-transistor memory cell includes forming a first floating body pattern on a lower insulating layer of a substrate and a first gate pattern crossing over the first floating body pattern and covering sidewalls of the first floating body pattern is formed. The first floating body pattern at both sides of the first gate pattern is partially etched to form a protrusion portion extending between and above the partially etched regions, and first impurity regions are formed in the partially etched regions of the first floating body pattern.

Abstract: A purpose of the invention is to provide a method for leveling a semiconductor layer without increasing the number and the complication of manufacturing processes as well as without deteriorating a crystal characteristic, and a method for leveling a surface of a semiconductor layer to stabilize an interface between the surface of the semiconductor layer and a gate insulating film, in order to achieve a TFT having a good characteristic. In an atmosphere of one kind or a plural kinds of gas selected from hydrogen or inert gas (nitrogen, argon, helium, neon, krypton and xenon), radiation with a laser beam in the first, second and third conditions is carried out in order, wherein the first condition laser beam is radiated for crystallizing a semiconductor film or improving a crystal characteristic; the second condition laser beam is radiated for eliminating an oxide film; and the third condition laser beam is radiated for leveling a surface of the crystallized semiconductor film.

Abstract: Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.

Abstract: A method for fabricating an array substrate for a liquid crystal display (LCD) is provided. A semiconductor layer and a transparent lower electrode formed on a substrate is provided and covered by a first dielectric layer serving as a gate dielectric layer and a capacitor dielectric layer. A gate electrode and an upper electrode comprising a transparent electrode portion and a metal electrode portion are formed on the first dielectric layer and covered by a second dielectric layer. A source/drain electrode, a planarization layer, and a pixel electrode are sequentially formed on the second dielectric layer, in which the source/drain electrode is electrically connected to the semiconductor layer through the first and second dielectric layers and the pixel electrode is electrically connected to the source/drain electrode through the planarization layer. An array substrate for an LCD is also disclosed.

Abstract: A method to fabricate an integrated circuit (IC) that includes a plurality of MOSFETs including at least one common gate FinFET device and at least one split gate FinFET device. A substrate having a semiconductor surface is provided. A plurality of fins are formed from the semiconductor surface including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height. Gate slacks are formed on the taller and shorter fins such that a gate electrode for the taller fin is a split gate electrode and a gate electrode for the shorter fin is a common gate electrode. Fabrication of the IC is completed, wherein the split gate FinFET includes the split gate electrode and the common gate FinFET device includes the common gate electrode.

Abstract: A high voltage FET and process for fabricating such an FET are provided. An extended drain and thick gate oxide device design is implemented in a basic CMOS structure to enable higher operating voltages. The basic concept of the invention is well suited for the body-tie architecture often utilized in this technology and is also applicable to other SOI processes using similar isolation schemes.

Abstract: A semiconductor storage device includes: a MOSFET formed on an SOI layer of the transistor forming region; and a MOS capacitor formed on the SOI layer of the capacitor forming region. The MOSFET includes: a gate insulating film formed; a floating gate electrode; a source layer and a drain layer formed; a channel region; a high-concentration diffusion layer, and impurities of a same type as impurities which are diffused in the channel region are diffused at a high concentration in the high-concentration diffusion layer; and a silicide layer covering the high-concentration diffusion layer and the source layer. The MOS capacitor includes a capacitor electrode at the SOI layer. The capacitor electrode of the MOS capacitor is disposed so as to oppose an end portion of the floating gate electrode of the MOSFET, with the gate insulating film therebetween.

Abstract: The present invention provides a manufacturing method of a display device which can efficiently separate individual thin-thickness display devices from a large-sized mother substrate. Scribe marks for separating a plurality of display devices are preliminarily formed on back surfaces of a TFT mother substrate and a sealing mother substrate. By etching front surfaces of these mother substrates, etching portions reach the scribe marks so that a plurality of display devices each of which is constituted of a TFT substrate and a sealing substrate can be separated from each other.

Abstract: A fabricating method for a semiconductor device includes forming a heat spreading material on rear surface of the semiconductor wafer. The semiconductor wafer has a plurality of device areas and scribe lines which are arranged between the device areas. After the heat spreading material is formed on rear surface of the semiconductor wafer, the semiconductor wafer is separated at the scribe lines.

Abstract: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.

Abstract: A pixel structure includes a substrate, a first and a second patterned conductive layers, and a pixel electrode. The first patterned conductive layer, disposed on the substrate, includes at least one scan line, at least one gate, and at least one common electrode line. The second patterned conductive layer, disposed on the first patterned conductive layer, includes at least one data line, at least one source/drain, and at least one first patterned layer partly disposed on the common electrode line. The pixel electrode, disposed on the second patterned conductive layer, includes at least one first part and one second part. The first part partly covers the first patterned layer and the common electrode line. The second part, connected to the source/drain, covers the other part of the first patterned layer. The first and second patterned layers compose at least one first capacitance.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Abstract: A method of manufacturing a display substrate and a display substrate manufactured by the same that are capable of improving display quality are presented. The method includes forming a gate wiring, a data wiring, a thin film transistor connected to the gate wiring and the data wiring respectively, and a protective insulating layer covering the gate wiring, the data wiring and the thin film transistor; forming a first black matrix pattern on the protective insulating layer; forming a protective insulating layer pattern by etching a part of the protective insulating layer by using the first black matrix pattern as an etching mask; forming a second black matrix pattern exposing at least one pixel region by removing a part of the first black matrix pattern; forming a color filter on the pixel region; and forming a pixel electrode electrically connected to the thin film transistor on at least a part of the color filter.

Abstract: A substrate having a switching device and a storage capacitor thereon is provided. A protective layer is formed on the substrate. A patterned organic material layer is formed on the protective layer, wherein bump patterns are formed on a part of the patterned organic material layer and the patterned organic material layer has first openings to expose the partial protective layer. A reflective layer is formed on the patterned organic material layer and the exposed protective layer. A first patterned photoresist layer is formed on a part of the reflective layer, wherein the first patterned photoresist layer has second openings to expose a part of the reflective layer. The first patterned photoresist layer is used as an etching mask to form a first contact hole and a second contact hole. The first patterned photoresist layer is removed. A pixel electrode is formed on the patterned organic material layer.

Abstract: A compound semiconductor material for forming an active layer of a thin film transistor device is disclosed, which has a group II-VI compound doped with a dopant ranging from 0.1 to 30 mol %, wherein the dopant is selected from a group consisting of alkaline-earth metals, group IIIA elements, group IVA elements, group VA elements, group VIA elements, and transitional metals. The method for forming an active layer of a thin film transistor device by using the compound semiconductor material of the present invention is disclosed therewith.

Abstract: A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

Abstract: A method for fabricating a TFT array substrate including the following steps is provided. A substrate having a pixel region and a photosensitive region is provided. A first patterned conductive layer is formed on the substrate, wherein the first patterned conductive layer includes a gate electrode disposed in the pixel region and a first electrode disposed in the photosensitive region, and a photosensitive dielectric layer is formed on the first electrode. A gate insulation layer is formed to cover the gate electrode, the photosensitive dielectric layer and the first electrode. A patterned semiconductor layer is formed on the gate insulation layer above the gate electrode. A source electrode and a drain electrode are formed on the patterned semiconductor layer at two sides of the gate electrode, wherein the gate electrode, the source electrode, and the drain electrode constitute a TFT. A second electrode is formed on the photosensitive dielectric layer.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

Abstract: The present invention relates to a CMOS circuit device on a SOI substrate with an oriented silicon surface, comprising on a first substrate region a FET that has a FET channel region of a first conductivity type, and comprising on a second substrate region a FinFET that has a FinFET channel region of a second conductivity type which is opposite to the first conductivity type. The invention also relates to a method for fabricating such a CMOS circuit device. The fabrication of the multi-gate planar FET comprises, at an intermediate step, forming a FET channel stack with an alternating sequence of layers of a FET material and of a sacrificial material and containing main FET-channel faces, which have the same orientation as the oriented silicon surface. According to the invention, a co-integration of multi-gate FET devices is achieved that ensures high carrier mobilities for both NMOS and PMOS FETs.

Abstract: The present invention is a method for producing an SOI wafer comprising at least a step of forming an ion-implanted damaged layer by ion-implanting a neutral element electrically inactive in silicon from one surface of the base wafer or the bond wafer, in which ion-implanting in the step of forming the ion-implanted damaged layer is performed at a dosage of 1×1012 atoms/cm2 or more and less than 1×1015 atoms/cm2. As a result, there may be provided a method for producing an SOI wafer having sufficient gettering ability while the suppression of leak failure, degradation of oxide dielectric breakdown voltage or the like is provided.

Abstract: Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first gate on a channel region of the p-MOS transistor region, and a second gate insulating layer and a second gate on a channel region of the n-MOS transistor region, wherein a source region and a drain region of the p-MOS transistor region may be tensile-strained due to Ge condensation, and the channel region of the n-MOS transistor region may be tensile-strained due to the Ge condensation.

Abstract: A pixel structure of a liquid crystal display panel and the method thereof is provided. The gate electrode and data line of the pixel structure are formed by a first patterned conductive layer, the scan line is formed by a second patterned conductive layer, and the common electrode and the pixel electrode are formed on a substrate. The common electrode, the pixel electrode, and the insulating layer disposed therebetween compose a storage capacitor. Also, the pixel or the common electrode has a slit structure.

Abstract: The present invention relates to an organic light emitting device including a substrate, an insulating layer disposed on the substrate, a first electrode disposed on the insulating layer, an organic light emitting member disposed on the first electrode, and a second electrode disposed on the organic light emitting member. The insulating layer includes a furrow corresponding to at least one edge of the first electrode, and at least a portion of the second electrode is disposed in the furrow.

Abstract: A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.

Abstract: A liquid crystal display includes a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines intersecting the gate lines, a plurality of common voltage lines formed in the same layer as the data line and parallel to the data lines and transmitting a common voltage, a plurality of thin film transistors connected to the gate lines and the data lines, and a plurality of pixel electrodes respectively connected to the thin film transistors, arranged in a matrix shape, each of the plurality of pixels including a first edge parallel to the gate lines and a second edge having a shorter length than the first edge and neighboring the first edge.

Abstract: A system for display images comprising a thin film transistor array substrate is disclosed. The system for display images comprises a substrate having a pixel area, a source/drain region overlying the substrate within an active layer in the pixel area, a bottom electrode overlying the substrate in the pixel area, a top electrode overlying the bottom electrode, a first dielectric layer disposed on the active layer, a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the bottom electrode and the top electrode and a gate disposed overlying the active layer, wherein the first and second dielectric layers are interposed between the gate and the active layer.

Abstract: Provided are a semiconductor device capable of improving the drive capacity of a MOS transistor even if the SOI layer is thinned; and a manufacturing method of the device. In a NMOS transistor formed in a NMOS formation region, a source/drain region is formed to penetrate through a buried oxide film and reach a threshold voltage controlling diffusion layer of a semiconductor substrate. In a PMOS transistor formed in a PMOS formation region, a source/drain region is formed to penetrate through a buried oxide film and reach a threshold voltage control diffusion layer of the semiconductor substrate.

Abstract: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.

Abstract: A fabrication method of an active device array substrate is disclosed. A first metal material layer, a gate insulation material layer, a channel material layer, a second metal material layer, and a first photoresist layer are formed over a substrate sequentially. The first photoresist layer is patterned with a multi-tone mask to form a first patterned photoresist layer with two thicknesses. A first and second removing processes are performed sequentially using the first patterned photoresist layer as a mask to form a gate, a gate insulation layer, a channel layer, and a source/drain. The first patterned photoresist layer is removed. A passivation layer and a second patterned photoresist layer are formed over the substrate. A third removing process is performed to form a plurality of contact holes. A pixel electrode material layer is formed over the substrate. The second patterned photoresist layer is lifted off to form a pixel electrode.

Abstract: The invention relates to a BiCMOS device comprising a substrate having a first type of conductivity and a number of active regions that are provided therein and are delimited in a lateral direction by flat field-insulating regions. Vertical npn bipolar epitaxial base transistors are disposed in a first partial number of the active regions while vertical pnp bipolar epitaxial base transistors are arranged in a second partial number of the active regions of the BiCMOS device. One transistor type or both transistor types are provided with both a collector region and a collector contact region in one and the same respective active region. In order to improve the high frequency characteristics, an insulation doping region that is configured so as to electrically insulate the collector and the substrate is provided between the collector region and the substrate exclusively in a first transistor type in which the type of conductivity of the substrate corresponds to that of the collector region.

Abstract: The display device includes a substrate, a thin film transistor (TFT), which includes a gate electrode, a semiconductor layer, and source and drain electrodes, on the substrate member, a passivation layer on the TFT and having an opening to expose a portion of the drain electrode, and a pixel electrode directly on the drain electrode and only within the opening.

Abstract: A semiconductor device comprises: a) a multiple layered substrate including a semiconductor substrate, an insulation film formed on the semiconductor substrate, and a semiconductor film, b) a first inverter having a first n-channel type MISFET and a first p-channel type MISFET connected in series each other, being formed on a first region in the multiple layered substrate; c) a second inverter having a second n-channel type MISFET and a second p-channel type MISFET connected in series each other, being formed on a second region; d) a first wiring connecting the output of the first inverter to the input of the second inverter; e) a second wiring connecting the output of the second inverter to the input of the first inverter; f) a first back gate region formed on the first region in the semiconductor substrate; g) a second back gate region formed on the second region in the semiconductor substrate; (h) a first connecting portion between the first wiring and the second back gate region; and (i) a second connecti

Abstract: A display substrate includes a plurality of transistors, a plurality of color filters, a plurality of pixel electrodes, a plurality of supporting members, and a plurality of filling members. The transistors are connected to a plurality of gate lines extending in a first direction on a base substrate and a plurality of data lines extending in a second direction crossing the first direction. The color filters are disposed over the transistors, and have a plurality of holes. The pixel electrodes are disposed on the color filters, and electrically connect to the transistors. The supporting members are disposed on the color filters, and maintain a gap between the base substrate and a substrate opposing the base substrate. The filling members are comprised of the same material as the supporting members, and fill the holes.

Abstract: A thin film transistor (“TFT”) array panel according to an exemplary embodiment of the present invention includes a substrate, a first storage electrode formed on the substrate, a first TFT formed on the substrate and separated from the first storage electrode, a first insulating layer formed on the first storage electrode and the first TFT and having a first opening disposed on the first storage electrode, a pixel electrode connected to the first TFT and overlapping the first storage electrode in the first opening, and a second insulating layer disposed between the first storage electrode and the pixel electrode in the first opening, wherein at least a portion of the boundary of the pixel electrode overlaps the first storage electrode and is disposed in the first opening. Accordingly, storage appropriate capacitance is ensured and a reduction of the aperture ratio may be decreased.

Abstract: Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.