Abstract: A micro electro-mechanical system, which can be stably formed so as to prevent sticking of a movable part and which has a narrow gap, and a method of manufacturing the same are provided. The micro electro-mechanical system includes at least one fixed electrode formed above a principal surface of a semiconductor substrate and at least one movable electrode formed on the principal surface. The at least one movable electrode includes the movable part separated from the principal surface and the at least one fixed electrode. The movable part is movable with respect to the principal surface and the at least one fixed electrode.

Abstract: Conductions and vias between different, stacked metallic layers of a semiconductor device may be mechanically damaged by mechanical strain. According to an exemplary embodiment of the present invention, this mechanical strain may be transferred through the layer structure to the substrate by a grid of grounding structures and isolation and passivation layers which are connected by the grounding structures. This may provide for an enhancement of the lifetime of the semiconductor devices.

Abstract: An electronic package and a manufacturing method thereof are disclosed. The electronic package manufacturing method, which includes providing a printed circuit board (PCB) having one surface on which a first chip is mounted; attaching one surface of a second chip on the other surface of the PCB, a pad being formed in the other surface of the second chip; encapsulating the second chip by coating the other surface of the PCB with an insulation material; and processing a first via by punching a hole on the insulation material, the first via being electrically interconnected to the pad, can perform stable handling in a process of mounting a semiconductor chip, make it unnecessary to add a process for chip encapsulation and realize a system in package having high density and high reliability.

Abstract: A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts.

Abstract: A high frequency device module of an embodiment of a current invention includes: an insulation substrate in which electrodes are provided on the front surface thereof and a grounding substrate is provided on the rear surface thereof; a high frequency device provided on the insulation substrate with a terminal of the device connected to the electrodes; potting material for covering the high frequency device; and a metallic layer provided on the potting material and connected to the grounding substrate.

Abstract: A semiconductor device includes: a semiconductor substrate that has an integrated circuit, a passivation film formed above the integrated circuit, and an electrode electrically connected to the integrated circuit, the passivation film having an uneven surface, the electrode having at least a portion exposed through the passivation film; a first resin layer that is disposed on the passivation film; a second resin layer that covers the passivation film and the first resin layer; and a wiring that extends from the electrode to a first part of the second resin layer above the first resin layer, the electrode passing on a second part of the second resin layer above the passivation film.

Abstract: An encapsulated electronic part packaging structure includes a step of mounting an electronic part having a connection terminal and a passivating film to cover the connection terminal, mounted on a body to direct the connection terminal upward. An insulating layer is formed to cover the electronic part, and a via hole is formed in a portion of the passivating film and the insulating layer on the connection terminal to expose the connection terminal. A wiring pattern, which is connected electrically to the connection terminal via the via hole, is formed on the insulating layer.

Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.

Abstract: A method of fabricating multilevel interconnects comprising providing a substrate having a pixel array area and a logical circuit area, forming a first dielectric layer on the substrate, performing a first metallizing process on the first dielectric layer to form a first patterned metal layer and a second patterned metal layer above the pixel array area and the logical circuit area separately, forming a second dielectric layer on the first patterned metal layer, the second patterned metal layer, and the first dielectric layer, performing a second metallizing process on the second dielectric layer to form a third patterned metal layer and a fourth patterned metal layer above the pixel array area and the logical circuit area separately, patterns of the fourth and the second patterned metal layer interlacing to completely cover the logical circuit area, and depositing a dielectric layer on the third and the fourth patterned metal layer.

Abstract: The present invention relates to a display device. The display device includes a display panel having gate lines and data lines, a driving chip mounted on the display panel, and a flexible printed circuit film (FPC) attached to the display panel. The display panel includes a plurality of first to third pads, a first switching element, a second switching element, a first test pad, and a second test pad. The plurality of first to third pads are sequentially disposed and electrically connected with each other. The first switching element is interposed between the first pad and the second pad. The second switching element is connected to the third pad. The first test pad is commonly connected to control terminals of the first and second switching elements. The second test pad is connected to an input terminal of the second switching element. According to the present invention, processing time and production yield can be increased by improving the detection performance in a visual inspection test process.

Abstract: A difference in delay of signal transmission due to the wiring within a board is minimized. A wiring board includes wiring for connecting terminals included in one of a plurality of semiconductor chips to terminals included in another one of the plurality of semiconductor chips, through branch points. Each of the plurality of semiconductor chips includes first and second terminals. Moreover, a first wiring up to the first terminals and a second wiring up to the second terminals are in a positional relationship of being shifted parallel to each other in a planar direction of the wiring board so as not to come into electrical contact with each other.

Abstract: Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract: Means for Solution: This interposer (10) comprises the silicon substrate (12), a plurality of through-hole conductors (20) formed on the above-described silicon substrate, and a capacitor (15) formed with the upper electrodes (14) and the lower electrodes (18) formed by extending the land portions of the above-described through-hole conductors and the dielectric layer (16) formed between the both electrodes. The rewiring layers (23-1, 23-2) formed as desired are formed on the layers other than the above-described capacitor layer.

Abstract: The disclosure relates to a semiconductor device and a method for producing a semiconductor device, in particular a semiconductor device having a circuit region having at least one active component for processing a high-frequency electromagnetic signal.

Abstract: A semiconductor device is provided with a first conductivity type semiconductor substrate (10); a voltage supplying terminal (26) arranged on the semiconductors substrate (10); one or more elements (6) which include a second conductivity type well section (22) and are arranged on the semiconductor substrate (10); a second conductivity type first conductive layer (21), which is a lower layer of the one or more elements (6), is in contact with the second conductivity type well section (22), and connects the second conductivity type well section (22) of the one or more elements (6) with the voltage supplying terminal (26); and a first conductivity type second conductive layer (11) formed in contact with a lower side of the first conductive layer (21).

Abstract: Thinning and stacking are essential for circuit modules used for mobile devices of various kinds, smart cards, memory cards and the like. These demands make the manufacture of the circuit modules more complicated or less reliable due to delamination. A circuit module of a multilayer structure is provided which is formed by embedding semiconductor chips and passive components in a sheet made from a thermoplastic resin; folding a module sheet, which is formed of circuit blocks provided with wiring patterns thereon, at the boundaries of the circuit blocks so as to be stacked into layers; and thermal-bonding and integrating the module sheet by applying heat and pressure. As a result, a highly reliable circuit module can be manufactured in a simple manner.

Abstract: A wiring film including wires, a semiconductor package including the wiring film, and a method of fabricating the semiconductor package are provided. The wiring film comprises a base film and first wires arranged on a first surface of the base film. First bumps are respectively positioned at ends of the first wires. A first adhesive layer is also provided to cover the first wires and the first bumps.

Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.

Abstract: In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly projecting features. A layer of material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the outwardly projecting features of the surface topology and has a gap over the valley. The layer is etched, and the etching forms protective material within the gap while removing an outermost surface of the layer. The etching substantially does not remove the material from the bottom of the gap. In another aspect, the invention encompasses a semiconductor processing method of forming a material over metal-comprising lines. A first insulative material substrate is provided. A pair of spaced metal-comprising lines are formed over the substrate.

Abstract: When a conductive layer is formed, a first liquid composition containing a conductive material is applied on an outer side of a pattern that is desired to be formed (corresponding to a contour or an edge portion of a pattern), and a first conductive layer (insulating layer) having a frame-shape is formed. A second liquid composition containing a conductive material is applied so as to fill a space inside the first conductive layer having a frame-shape, whereby a second conductive layer is formed. The first conductive layer and the second conductive layer are formed so as to be in contact with each other, and the first conductive layer is formed so as to surround the second conductive layer. Therefore, the first conductive layer and the second conductive layer can be used as one continuous conductive layer.

Abstract: A packaged chip is provided which includes a package element on which a signal-bearing conductive trace has an edge laterally adjacent to an edge of a reference conductive trace (e.g., ground trace) on the same face of a dielectric element, the two traces together functioning as a capacitor. In a particular embodiment, the laterally adjacent traces provide shunt capacitance to compensate for an inductance in a signal path to the chip which includes the signal-bearing conductive trace. In a variation thereof, a transmission line or waveguide is provided which includes the signal-bearing conductive trace and reference trace. In further variations, transmission lines are provided which include one or more metal layers of a package element, separated from each other by a thickness of a dielectric element included in the package element or the air gap between the package and a circuit panel.

Abstract: There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in the opening of the SiON film. Such constitution provides the structure, in which the upper portion of the interfaces between the Cu pad areas and the insulating areas are covered by the SiON film.

Abstract: A chip (1) has a substrate (2), an integrated circuit (3) provided on the substrate (2), a plurality of conductor zones (ME1, ME2, ME3, ME4, ME5) and a passivating layer (5) provided to protect the conductor zones and the integrated circuit, through-holes (6, 7) being provided in the passivating layer (5) through which chip contacts (8, 9) are accessible, wherein additional chip contacts (10, 11) and connecting conductors (12, 13) are provided on the passivating layer (5) and wherein each additional chip contact has an electrically conductive connection to a chip contact via a connecting conductor.

Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

Abstract: Herein disclosed a semiconductor device in which a semiconductor chip is mounted over a substrate, the device including a plurality of through-interconnects configured to be formed inside each of through-holes that penetrate the substrate and be led from the semiconductor chip to a face of the substrate on an opposite side of the semiconductor chip.

Abstract: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

Abstract: A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first surface. Openings are formed through the levee film. Connection members which is filled but is not completely filled in the openings connect the electrodes and the extension layers.

Abstract: Structures employing siloxane epoxy polymers as diffusion barriers adjacent conductive metal layers are disclosed. The siloxane epoxy polymers exhibit excellent adhesion to conductive metals, such as copper, and provide an increase in the electromigration lifetime of metal lines. In addition, the siloxane epoxy polymers have dielectric constants less then 3, and thus, provide improved performance over conventional diffusion barriers.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

Abstract: A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours.

Abstract: Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by using a dual damascene process, and deposits a barrier layer along the bottom and the sidewalls of the trench and via hole.

Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

Abstract: A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper layer insulating film is provided on the first semiconductor construct and insulating layer. Upper layer wiring lines are provided on the upper layer insulating film so that the upper layer wiring line is electrically connected to the external connection electrode. A second semiconductor construct is joined to and installed on connection pad portions. All jointing portions of the second semiconductor construct for the connection pad portions of the upper layer wiring lines are disposed in a region corresponding to the first semiconductor construct.

Abstract: A process of making an electrical coupling stack is disclosed. A conductive structure is coupled to a substrate. The coupling includes a crystalline salicide first structure above the conductive structure, a nitrogen-containing amorphous salicide second structure above the crystalline salicide first structure, and a refractory metal third film above the nitrogen-containing amorphous salicide second structure. Processing includes depositing a refractory metal silicide first film over the conductive structure, depositing a refractory metal nitride second film over the refractory metal silicide first film, and depositing the refractory metal third film over the refractory metal nitride second film. Thermal processing is carried out to achieve the electrical coupling stack.

Abstract: A circuit structure for a package substrate or a circuit board is provided. The circuit structure has a dielectric layer with an upper surface and a lower surface, at least a first line and at least a second line. The first line is disposed on the dielectric layer on which a base of the first line is aligned with the upper surface. In addition, the second line is disposed on the dielectric layer on which a base of the second line is embedded below the upper surface. Since the second line is embedded into the dielectric layer, the distance with a reference plane is reduced and the crosstalk between the signals is further effectively reduced.

Abstract: A substrate used in a semiconductor device. The substrate includes a first wiring layer, a second wiring layer, and an interconnection-wiring layer. The first wiring layer includes a plurality of first pads, and the second wiring layer includes a plurality of second pads. The interconnection-wiring layer is set between the first and second wiring layer. In this case, at least one of the second pads that does not electrically connect to anyone of the first pads electrically connects to the interconnection-wiring layer. In another case, a shielding portion, which electrically connects the interconnection-wiring layer, is provided around the second pad that doesn't electrically connect to anyone of the first pads. Furthermore, this invention also discloses a semiconductor device including the substrate.

Abstract: A groove is formed on a semiconductor substrate having integrated circuits and electrodes from a first surface. An insulating layer is formed on an inner surface of the groove. A conductive layer is formed on the insulating layer above the inner surface of the groove. A second surface of the semiconductor substrate opposite to the first surface is ground until the groove is exposed to divide the semiconductor substrate into a plurality of semiconductor chips in which the conductive layer is exposed on a side surface of each semiconductor chip. The semiconductor chips are then stacked. The conductive layer of one of the semiconductor chips is electrically connected to the conductive layer of another one of the semiconductor chips.

Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.

Abstract: Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored in the semiconductor chip, the integrated circuit does not operate and it is impossible to analyze the information. Further, there is provided a processing detector circuit for detecting that the wiring lines have been tampered with. When the processing detector circuit detects a change in the state of the wiring lines, the integrated circuit is reset. Thus, it is possible to improve the security of information stored on the card.

Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.

Abstract: A wiring board includes a substrate made of an insulation material and wired by a conductive material. A plurality of electrodes is formed on a surface of the substrate. A non-Au electrode not having an Au surface layer and an Au electrode having the Au surface layer are formed as the electrodes.

Abstract: The present invention provides a method for manufacturing a substrate having a pattern that is capable of controlling the distance between adjacent film patterns, and also provides a method for manufacturing a substrate, particularly, having a pattern with a narrow width and a thickness that is capable of controlling the width between the film patterns. The present invention provides a method for manufacturing a substrate having a conductive film that serves as an antenna with a little variation in inductance and has a large electromotive force, and provides a method for manufacturing a semiconductor device with high yield. After forming a film in which silicon and oxygen are combined and an inactive group is combined with the silicon over a substrate, an insulating film, or a conductive film, a composition is printed by the printing method thereover, and is baked to form a film pattern.

Abstract: When an integrated circuit is formed in a semiconductor wafer, the integrated circuit is formed only in the central part of each chip region. In a case where packaging other than a chip size package is made, only the central part in which the integrated circuit is formed is cut from the wafer. In a case where a chip size package is made, the chip region is cut from the wafer after forming the redistribution wiring and external terminals and so forth over the whole of the chip region. As a result, the design of the integrated circuit and part of the fabrication process thereof can be shared by a chip which is mounted in a chip size package and a chip which is mounted in another type of package.

Abstract: A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first differential signal line associated with a differential signal line pair at a first redistribution layer in a direction along the common plane, and jogging a second differential signal line associated with the differential signal line pair at a second redistribution layer along the common plane in a same direction as the first differential signal line to provide a substantially balanced differential signal line pair.

Abstract: A packaged semiconductor device, in particular a gallium nitride semiconductor structure including a lower semiconductor layer and an upper semiconductor layer disposed over a portion of the lower semiconductor layer. The semiconductor structure includes a plurality of mesas projecting upwardly from the lower layer, each of the mesas including a portion of the upper layer and defining an upper contact surface separated form adjacent mesas by a portion of the lower layer surface. The device further includes a die mounting support, wherein the bottom surface of the die is attached to the top surface of the die mounting support; and a plurality of spaced external conductors extending from the support, at least once of said spaced external conductors having a bond wire post at one end thereof; with a bonding wire extending between the bond wire post and a contact region to the top surface of the plurality of mesas.

Abstract: A gate structure for a semiconductor device includes a shielding electrode and a switching electrode. Respective portions of the shielding electrode are disposed above said drain region and said well region. A first dielectric layer is disposed between the shielding electrode and the drain and well regions. The switching electrode includes respective portions that are disposed above said well region and said source region. A second dielectric layer is disposed between the switching electrode and the well and source regions. A third dielectric layer is disposed between the shielding electrode and the switching electrode.