Abstract: A lead frame may include a plurality of leads, each having a bonding portion electrically connected to a semiconductor chip and an attaching portion. A tape may be provided on the attaching portions of the leads. The attaching portion of each lead may have a width that is smaller than the width of another portion of the lead. A plating layer may be provided on the attaching portion. The lead frame may be implemented in a semiconductor package.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same are provided. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: A package for an electronic component according to one embodiment of the invention has a chip mounting area mounting a semiconductor chip in a hollow part of a metal plate and a plurality of connection electrodes to be connected to a substrate. The plurality of connection electrodes are formed in opposite sides of the rectangular metal plate and arranged asymmetrically with respect to a perpendicular bisector of the opposite sides.

Abstract: A metal substrate apparatus comprises a plurality of metal substrates forming an IC card module used in manufacturing transfer mold-type non-contact IC cards. The metal substrate apparatus comprises a thin metal strip of processing material, and each metal substrate has connecting parts. Each metal substrate has a die pad for loading an IC chip. Antenna terminals to connect antenna coils are located outside the die pad and a resin-sealed region. The antenna terminals of one metal substrate and those of a longitudinally adjacent metal substrate overlap a shared region of the processing material in a width direction. The metal substrates can be separated by sealing and then making longitudinal cuts on the processing material on the outer parts of the metal substrates along two connecting lines.

Abstract: A semiconductor component includes a leadframe, a die, upper and lower body segments encapsulating the die, and dummy segments on the leadframe. The dummy segments are configured to vent trapped air in a molding compound during molding of the body segments, such that corners of the body segments do not include the trapped air.

Abstract: Aspects of the invention recite wire bonding on thinned portions of a lead-frame that is configured for use in an IC package. A harder lead-frame material, improved adhesive tape, and various structural features of the lead-frame itself, in various combinations or subcombinations, facilitate the attachment of wire bonds to thinned areas of the lead-frame. This eliminates the need for supports placed directly under the bond sites, removing unwanted conductive areas on the outer surface of an IC package.

Abstract: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications.

Abstract: A semiconductor device X1 comprises: a first conductor 110 including a first terminal surface 113a; a second conductor 120 placed by the first conductor 110 and including a second terminal surface 123a facing a same direction as does the first terminal surface 113a; a third conductor 130 connected with the first conductor 110; a semiconductor chip 140 including a first surface 141 and a second surface 142 away from the first surface, and bonded to the first conductor 110 and to the second conductor 120 via the second surface 142; and a resin package 150. The first surface 141 of the semiconductor chip 140 is provided with a first electrode electrically connected with the first conductor 110 via the third conductor 130. The second surface 142 is provided with a second electrode electrically connected directly with the second conductor 120.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.

Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.

Abstract: A semiconductor package that includes two power semiconductor dies, such as power MOSFET dies, including vertical conduction MOSFETs, arranged in a half-bridge configuration is disclosed. The package may be mounted on a split conductive pad including two isolated die pads, each die pad being electrically connected to the second power electrode of the die that is on it. The split pad may include several conductive leads, including at least one output lead electrically connected to a first electrode of the first semiconductor die on the same side of the die as the control electrode and to the second electrode of the second die located on the opposite side of the second die from the control electrode.

Abstract: The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the multiple dotted grooves.

Abstract: An electronic module includes a semiconductor power switch and a semiconductor diode. The lower side of the semiconductor power switch includes an output contact mounted on a die pad of a leadframe, and the upper side of the semiconductor power switch includes a control contact and an input contact. The anode contact of the semiconductor diode is disposed on and electrically connected to the input contact of the semiconductor power switch. The cathode contact of the diode is electrically connected with the output contact of the power semiconductor switch.

Abstract: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material (108). The lead frame material (108) may comprise of a portion of a contiguous metal sheeting (204) rolled upon a first coil (202), wherein the contiguous metal sheeting (204) is fed into an external lead stamping apparatus (206), thus forming the external leads (122), and rolled onto a second coil (215). The portion is fed into a plating apparatus and plated with the metal (222), and rolled onto a third coil (218) prior to forming the plurality of internal leads (124). The third coil (218) can be unrolled into an internal lead stamping apparatus (226), thus forming the internal leads (124) of a lead frame (100).

Abstract: A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: A semiconductor device is provided including a semiconductor element having a plurality of electrodes, a plurality of bonding portions of a lead frame, a plate-like current path material which electrically connects at least one of the plurality of electrodes and one of the plurality of bonding portions, a housing which packages the semiconductor element having the plurality of electrodes, the plurality of bonding portions of the lead frame, and the current path material, wherein the plate-like current path material is arranged to be directly bonded to one of the plurality of electrodes and one of the plurality of bonding portions, and the middle portion of the current path material is formed apart from the surface of the semiconductor element. A method of manufacturing the same is also provided.

Abstract: A semiconductor device comprises a semiconductor chip which is mounted on a stage. A plurality of leads are electrically connected with the semiconductor chip. A package encloses the semiconductor chip and a part of the plurality of leads. A first corner lead is provided in the stage and outwardly extends from at least one of vertex portions at four corners of the stage to an exterior of the package.

Abstract: A lead-frame method and assembly for interconnecting circuits within a circuit module allows a circuit module to be fabricated without a circuit board substrate. Integrated circuit dies are attached to a metal lead-frame assembly and the die interconnects are wire-bonded to interconnect points on the lead-frame assembly. An extension of the lead-frame assembly out of the circuit interconnect plane provides external electrical contacts for connection of the circuit module to a socket.

Abstract: A semiconductor device which permits reduction in the number of pins and in size thereof is provided.

Abstract: Provided is a method of producing a semiconductor package including at least two rows of leads in which the leads of each row separately connecting a semiconductor chip to an external substrate. The method includes: forming a lead frame, the lead frame including a die pad and a plurality of leads arranged about the die pad; attaching an adhesive tape to a surface of the lead frame covering at least substantially the die pad and the plurality of leads; removing portions of the leads and the adhesive tape disposed in a dividing region and thereby separating at least some of the plurality of leads to form multiple rows of leads; and mounting a semiconductor chip on the die pad, electrically connecting the semiconductor chip with the lead frame, and molding the lead frame and the semiconductor chip to provide a semiconductor package. The adhesive tape attached at undesirable locations of the lead frame is preferably removed after provision of the semiconductor package.

Abstract: A flip-chip semiconductor package with a lead frame and a method for fabricating the same are provided. The lead frame has a plurality of leads, each lead having an upper surface, a lower surface, and an inner end directed toward the center of the lead frame. A recessed portion is formed on the upper surface of the inner end of each lead, making the inner end shaped as a stepped structure. The depth of the recessed portion is equal to a height of a reflow-collapsed solder bump that is for electrically connecting a chip to the lead. At least one chip is electrically connected to the leads in a flip-chip manner via a plurality of solder bumps bonded to the recessed portions. An encapsulation body is formed to encapsulate the lead frame, chip and solder bumps, with the lower surfaces of the leads being exposed from the encapsulation body.

Abstract: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention is that the integrated circuit products are produced a batch at a time, and that singulation of the batch into individualized integrated circuit products uses a non-linear (e.g., non-rectangular or curvilinear) sawing or cutting action so that the resulting individualized integrated circuit packages no longer need to be completely rectangular. Another aspect of the invention is that the integrated circuit products can be produced with semiconductor assembly processing such that the need to provide an external package or container becomes optional.

Abstract: A semiconductor package comprising a semiconductor die which has opposed first and second surfaces and at least first and second bond pads disposed on the second surface thereof. In addition to the semiconductor die, the semiconductor package includes at least one lead having opposed first and second surfaces, the first surface of the lead being electrically connected to the first bond pad. Also included in the semiconductor package is at least one conductive post having opposed first and second surfaces, the first surface of the conductive post being electrically connected to the second bond pad. A package body at least partially encapsulates the semiconductor die, the lead, and the conductive post such that the second surface of the lead and the second surface of the conductive post are exposed in a common exterior surface of the package body.

Abstract: A power QFN package includes signal leads, a die pad, support leads, and an adhesive for die bonding. These elements are encapsulated with a resin encapsulant. The lower parts of the signal leads are exposed from the resin encapsulant to function as external electrodes. A middle part of the die pad is formed at a higher level than a peripheral part thereof. This permits the formation of through holes in a thin part of the die pad. This enhances the degree of flexibility in the size of a semiconductor chip and the moisture resistance thereof.

Abstract: The specification describes a plastic overmolded package for high power devices that has a very low lead count, typically fewer than eight, and in a preferred embodiment, only two. The leads occupy essentially the same linear space as the multiple leads in a conventional package and thus have a wide-blade configuration. To improve mechanical integrity, the leads in the package are provided with retention slots to add back the equivalent of the plastic joints in the spaces that were eliminated due to the wide-blade design. The retention slots extend in the width dimension of the leads.

Abstract: A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal includes conductors which function as an internal signal transmission system for the component, and a mask layer which functions as a solder mask and an outer insulating layer for the component. An adhesive layer in physical contact with the conductors attaches the circuit decal to the stiffener, and electrically insulates the conductors from the stiffener. The component also includes an area array of terminal contacts on the conductors electrically isolated by the mask layer. A method for fabricating the component includes the steps of attaching the circuit decal to the stiffener, attaching the die to the stiffener, interconnecting the die and the circuit decal, encapsulating the die, and forming the terminal contacts.

Abstract: A leadframe, a semiconductor package, and methods of making the same are disclosed. A leadframe includes leads having an inner end segment. A first subset of the leads include a recess in a first surface of the inner end segment. A second subset of the leads include a recess in an opposite second surface of the inner end segment. The first subset leads are in an alternating lateral pattern with the second subset leads such that the recess of adjacent inner end segments are oriented in opposite directions. The recesses separate adjacent inner end segments in a vertical direction, thereby eliminating or reducing a need for horizontal spacing between adjacent inner end segments. In a semiconductor package, a semiconductor chip is electrically connected by a bond wire to the inner end segment of the leads. The bond wire is bonded within the recess of alternating leads.

Abstract: A low profile semiconductor device package includes a lead frame with terminal leads and two die pads for receiving at least two semiconductor die that are interconnected to form a circuit. A further low profile semiconductor device package includes a lead frame with two die pads for receiving at least two semiconductor die that are interconnected to form a circuit and also has a reduced height through removal of a mounting tab. An example of such device packages is a package that includes first and second MOSFET die, each connected to a respective die pad. The source of one MOSFET is connected to the drain of the other MOSFET, thereby forming a low profile device package that provides a half-bridge circuit. Other example device packages include different arrangements of two interconnected MOSFET die, two interconnected IGBTs, or a combination of a MOSFET die and a diode.

Abstract: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).