Abstract: The semiconductor device comprises a first area and a second area positioned adjacent to the outside of the first area, the semiconductor substrate having a main surface and side surfaces and disposed in such a manner that the main surface is positioned in the first area and each of the side surfaces is positioned at a boundary between the first area and the second area, a plurality of pads formed over the main surface of the semiconductor substrate and a plurality of external connecting terminals formed thereon, which are respectively electrically connected to the pads, a first resin portion which is formed over the main surface of the semiconductor substrate so as to cover the pads and has a main surface and side surfaces, and which is formed in such a manner that the external connecting terminals are exposed from the main surface and each of the side surfaces is positioned at the boundary, and a second resin portion which is positioned in the second area and formed so as to cover the side surfaces of the s

Abstract: An integrated circuit package system includes: providing a protective layer having an opening; forming a conductive layer over the protective layer and filling the opening; patterning a rigid locking lead, having both a lead locking portion and a lead exposed portion, from the conductive layer; connecting an integrated circuit and the rigid locking lead; and forming an encapsulation over the integrated circuit with the lead locking portion in the encapsulation and the lead exposed portion exposed from the encapsulation.

Abstract: A semiconductor device (100) comprises a first resin substrate (101) on which a first semiconductor chip (125) is mounted a surface thereof; a second resin substrate (111) on which a second semiconductor chip (131) is mounted on a surface thereof; and a resin base material (109), joined to a front surface of the first resin substrate (101) and to a back surface of the second resin substrate (111), so that these surfaces are electrically connected. The resin base material (109) is disposed in a circumference of the first resin substrate (101) in the surface of the first resin substrate (101). Further, the first semiconductor chip (125) is disposed in a space section provided among the first resin substrate (101), the second resin substrate (111) and the resin base material (109) in the surface of the first resin substrate (101).

Abstract: A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing resin, and a shielding member configured to cover the sealing resin and be connected to the ground electrode.

Abstract: In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed.

Abstract: The invention relates to an organic electronic component, such as e.g. an organic light diode or an organic solar cell with structures made of passivation material, the passivation material comprising at least one dessicant.

Abstract: A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors.

Abstract: A semiconductor package with electromagnetic shielding capabilities is disclosed. The semiconductor package includes a substrate (101), a plurality of semiconductor dies (102), a plurality of shielding metal elements (103), a plurality of grounding metal elements (104) and a plurality of conductive metal elements (110). The semiconductor dies are disposed on an upper surface (105) of the substrate along a horizontal direction. The shielding metal elements are provided on the upper surface of the substrate, and are arranged between and around the semiconductor dies so that each semiconductor die is surrounded by the shielding metal elements and thus electromagnetic interference in the horizontal direction can be effectively shielded from each semiconductor die.

Abstract: An electrical device and method of making same is provided wherein a chip or other electrical component is embedded in a substrate. The substrate may be a thermoplastic material capable of deforming around the chip and at least partially encasing the chip when heat and/or pressure is applied to the substrate. Electromagnetic radiation such a near infrared radiation can be used to heat the substrate. The substrate may include a compressible layer that can be compressed and/or crushed to form a recess into which the chip can be inserted. Once embedded, the chip or electrical component is secured by the substrate and may be coupled to another electrical component. A method of making an RFID transponder is also provided wherein an RFID chip is embedded in a substrate using heat and/or pressure, an antenna structure is applied to the substrate, and the RFID chip and antenna structure are coupled together.

Abstract: A semiconductor device includes a substrate 2, a semiconductor element 3, a molding resin portion 4, and a plurality of connection terminals 5 arranged on a surface of the substrate around the outer periphery of the molding resin portion 4. In a region B corresponding to a resin passage used to form the molding resin portion 4, a plurality of metal planes 18 and 19 as resin peel-off portions exhibiting a low adhesive strength to the molding resin are arranged in a direction along the resin passage at appropriate intervals. At least one connection terminal 5 is located between the metal planes 18 and 19.

Abstract: The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.

Abstract: Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.

Abstract: Embodiments of the invention relate generally to an integrated circuit and a memory module. In an embodiment of the invention, an integrated circuit is provided. The integrated circuit may include a semiconductor carrier including at least one electrically inactive region on an upper surface thereof, a passivation layer structure disposed above the upper surface of the semiconductor carrier, and at least one lithographic trench in the passivation layer structure above the at least one electrically inactive region on the upper surface of the semiconductor carrier.

Abstract: The present invention provides a sealing film excellent in filling properties and adhesiveness as a sealing film which comprises a resin layer containing the following (A), (B) and (C) and having a flow within the range of 150 to 1800 ?m at 80° C.: (A) a resin component containing (a1) a high-molecular-weight component comprising crosslinking functional groups and having a weight-average molecular weight of 100,000 or more and a Tg within the range of ?50 to 50° C. and (a2) a thermoplastic component comprising an epoxy resin as main component, (B) a filler having an average particle size within the range of 1 to 30 ?m, and (C) a colorant, as well as a method for manufacturing the same and a semiconductor device using the same.

Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.

Abstract: An electronic device includes: a substrate on which an interconnect pattern is formed; a chip component having a first surface on which an electrode is formed and a second surface opposite to the first surface, the chip component being mounted in such a manner that the second surface faces the substrate; an insulating section formed of a resin and provided adjacent to the chip component; and an interconnect which is formed to extend from above the electrode, over the insulating section and to above the interconnect pattern.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: The present invention relates to a method for encapsulating a substrate, which comprises: (a1) providing a substrate with a plurality of chips mounted on a top side of the substrate; (b1) compressing a dry film photoresist on the top side of the substrate to form a photoresist layer; (c1) exposing the photoresist layer to a light source through a mask to form unexposed photoresist regions and exposed photoresist regions; (d1) developing the photoresist layer to uncover underlying portions of the unexposed photoresist regions; (e1) molding the top side of the substrate with a molding material; (f1) curing the molding material; and (g1) removing the unexposed photoresist regions from the substrate with a photoresist-removing agent.

Abstract: A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the sealing resin layer.

Abstract: A semiconductor component (has at least one semiconductor chip in which an electrical circuit is integrated. The semiconductor chip is surrounded by an electrically insulating encapsulating compound and has on its surface at least one termination surface for a test signal, which is covered by the encapsulating compound. The termination surface is connected in an electrically conductive manner to an analysis contact that projects above the surface of the semiconductor chip, that is located in the interior of the encapsulating compound at a distance from its exterior surface, and that can be exposed by removing a layer of the encapsulating compound located near the exterior.

Abstract: A curable phenoxyphenyl polysiloxane composition is disclosed. A cured phenoxyphenyl polysiloxane composition is further disclosed, along with a method of making that cured phenoxyphenyl polysiloxane composition from the curable phenoxyphenyl silicon composition. An encapsulated semiconductor device, and a method of making that encapsulated semiconductor device by coating a semiconductor element of a semiconductor device with cured phenoxyphenyl polysiloxane are further disclosed.

Abstract: Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications.

Abstract: The present invention provides a transparent inorganic oxide dispersion which makes it possible to improve the refractive index and mechanical characteristics and to maintain transparency by modifying the surface of inorganic oxide particles with a surface modifier having one or more reactive functional groups; and an inorganic oxide particle-containing resin composition in which the transparent inorganic oxide dispersion and a resin are compositely integrated by the polymerization reaction, a composition for sealing a light emitting element, a light emitting element, and a method for producing an inorganic oxide particle-containing resin composition; and a hard coat film which has high transparency and makes it possible to improve a refractive index and tenacity, an optical functional film, an optical lens and an optical component.

Abstract: A method for producing multiple semiconductor devices. An electrically conductive layer is applied onto a semiconductor wafer. The semiconductor wafer is structured to produce multiple semiconductor chips. The electrically conductive layer is structured to produce multiple semiconductor devices.

Abstract: An integrated circuit package system includes: providing an integrated circuit; mounting a lead on the periphery of the integrated circuit; connecting the integrated circuit to the lead with an interconnect; and forming a conformable material by pressing the conformable material on the integrated circuit, the lead, and the interconnect.

Abstract: A process for producing a circuit substrate having a resin sheet having embedded circuit chips which is obtained by embedding circuit chips into a resin sheet, which comprises steps of (a) arranging and fixing circuit chips on a substrate for processing, (b) coating the substrate for processing on which the circuit chips have been arranged and fixed with a liquid material for forming a resin sheet of an energy curing type to form an uncured coating layer, (c) curing the uncured coating layer by impressing energy to form a layer of a resin sheet having embedded circuit chips, and (d) removing the substrate for processing from the layer of a resin sheet having embedded circuit chips, and a circuit substrate obtained in accordance with the process. A circuit substrate having a resin sheet having embedded circuit chips for controlling pixels of displays and the like can be produced efficiently with excellent quality and excellent productivity.

Abstract: Provided is a laminated body comprising a substrate to be ground and a support, where the substrate may be ground to a very small (thin) thickness and can then be separated from the support without damaging the substrate. One embodiment is a laminated body comprising a substrate to be ground, a curable silicone adhesive layer in contact with the substrate to be ground, a photothermal conversion layer comprising a light absorbing agent and a heat decomposable resin, and a light transmitting support. After grinding the substrate surface which is opposite that in contact with the adhesive layer, the laminated body is irradiated through the light transmitting layer and the photothermal conversion layer decomposes to separate the substrate and the light transmitting support.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: The present invention provides a semiconductor device having a coating film of a predetermined thickness provided along the circumference of a semiconductor light emitting element, and provide a method for easily manufacturing the semiconductor device. A semiconductor light emitting element 2 that emits blue light is mounted face down on the top face of a pedestal 1, and a coating film 3 containing a YAG fluorescent material 6 that emits yellow light is placed so as to cover the top face and side face of the semiconductor light emitting element 2 and the top face of the pedestal 1. With the semiconductor light emitting element 2 and other elements placed between a first film 8 and a second film 9, the films are laminated in vacuum, thereby to fasten the coating film 3 onto the semiconductor light emitting element 2.

Abstract: A semiconductor package and a method for fabricating the same are disclosed. The present invention discloses mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interfacial layer or a heat-dissipating member having the interfacial layer on the semiconductor chip, and forming an encapsulant for covering the semiconductor chip, the interfacial layer or the heat dissipating member. The method further includes cutting the encapsulant along edges of the interfacial layer, and removing the redundant encapsulant on the interfacial layer so as to expose the semiconductor chip or the heat-dissipating member without forming burr or heavily wearing cutting tools.

Abstract: An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted.

Abstract: A manufacturing method of a chip package structure is provided. A circuit substrate having a first surface, a second surface, and a through hole connecting the first surface and the second surface is provided. A chip having an active surface and bonding pads disposed on the active surface is provided. The chip is fixed on the circuit substrate, wherein the second surface is opposite to the active surface and the bonding pads are exposed to the through hole. Bonding wires connecting the bonding pads and the first surface are formed through the through hole. A film having an opening is formed on the first surface. The bonding wires, the bonding pads, the through hole, and part of the first surface are exposed by the opening. An encapsulant is formed to encapsulate part of the active surface, the bonding wires, and part of the first surface. The film is removed.

Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, a panel of semiconductor packages may undergo a first cutting process which cuts the curvilinear edges of the packages. Next, the partially singulated panel of packages may undergo an abrasion process for smoothing the cut curvilinear edges. The abrasion process may occur by forcing abrasive particles over the jagged side edges of a semiconductor package as a result of a pressure differential above and below the semiconductor packages. Upon completion of the abrasive process, a second cutting process may be performed which cuts along straight edges and singulates the respective packages from the panel.

Abstract: There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.

Abstract: A method of laser-marking a semiconductor device involves providing a semiconductor wafer having a plurality of solder bumps formed on contact pads disposed on its active surface. The solder bumps have a diameter of about 250-280 ?m. A backgrinding tape is applied over the solder bumps. The tape is translucent to optical images. A backside of the semiconductor wafer, opposite the active surface, undergoes grinding to reduce wafer thickness. The backside of the semiconductor wafer is laser-marked while the tape remains applied to the solder bumps. The laser-marking system including an optical recognition device, control system, and laser. The optical recognition device reads patterns on the active surface through the tape to control the laser. The tape reduces wafer warpage during laser-marking to about 0.3-0.5 mm. The tape is removed after laser-marking the backside of the semiconductor wafer.

Abstract: According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.

Abstract: A semiconductor device for adequately removing heat generated by a semiconductor element is provided. A semiconductor device 100 is equipped with a substrate 2, having a bottom surface 2b and an element mounting surface 2a which is positioned on the opposite side of bottom surface 2b, and a semiconductor element 1, having a main surface 1a which is mounted onto element mounting surface 2a. With L being the length in the long direction of main surface 1 and H being the distance between bottom surface 2b and element mounting surface 2a, the ratio H/L is 0.3 or greater. When the semiconductor element is a light emitting element, element mounting surface 2a is a cavity 2u, and element 1 is provided in cavity 2u. A metal layer 13 is provided on the surface of cavity 2u. In addition, when an electrode 32 which connects to an external part is provided on main surface 1a, on the cavity side of the part which connects with electrode 32, main surface 1a is provided with a groove.

Abstract: A power module includes: an encapsulation-target portion having at least one semiconductor element; and an encapsulation member that has first and second planes between which the encapsulation-target portion is interposed, and that encapsulates the encapsulation-target portion. The encapsulation member has, on the at least one semiconductor element, at least one opening that exposes part of a surface of the encapsulation-target portion the surface being on a side of the first plane. Thus, a semiconductor device of which size can be reduced can be provided.

Abstract: A semiconductor device is disclosed. One embodiment provides a semiconductor chip having a main surface, wherein a first molding compound accommodates the semiconductor chip. The first molding compound has a surface that is substantially coplanar to the main surface of the semiconductor chip. A second molding compound is arranged in a space between the first molding compound and the semiconductor chip.

Abstract: A wafer-level packaging method is shown below: providing an un-cut wafer having a front side and a back side. A plurality of cutting lines is formed on the front side of the wafer so as to define the positions of each chip module such as a wireless module. The next step is providing an extendible film attached onto the back side of the wafer. Next is dicing the wafer along the cutting line to separate each chip module and expending the extendible film so that a gap is formed between each chip module. At last, filling a packaging compound onto the front side and the lateral side of the chip module produces a packaged structure. As mentioned above, the structure is employed for protecting the external surface of the chip.

Abstract: A micromechanical component has a structure such that a material flow is guided from at least one preferred direction for the purpose of uniformly enveloping the micromechanical component.

Abstract: A semiconductor apparatus includes a substrate and elements or semiconductor chips provided on the substrate. The elements are sealed by being brought into contact with a sealing compound. The surface of contact on the elements or the sealing compound is plasma treated. The semiconductor chip is adhesively attached to another semiconductor chip via an adhesive compound. The surface of the semiconductor chip in contact with the adhesive compound is plasma treated.

Abstract: A semiconductor element is provided with electrode pads which are arranged on a front surface of an element main body, an insulating protection film which covers the front surface of the element main body excepting its outer peripheral area while exposing the electrode pads, and an insulating adhesive layer which is formed to cover a back surface, a sidewall surface and a corner between the front surface and the sidewall surface of the element main body. A plurality of semiconductor elements are stacked on a circuit substrate. The semiconductor elements are adhered via the insulating adhesive layer.

Abstract: This invention relates to molded plastic article having an in-mold label comprising radio frequency identification (RFID) device, and methods of in-mold labeling. In one embodiment of the invention, an RFID label comprises an RFID inlay and a substrate underneath the RFID inlay. The substrate includes a first surface and a second surface, with the RFID inlay disposed on the first surface. A primer is applied to the first surface including the inlay and the second surface of the substrate. A polymer cover is applied over the primer on the first surface and the second surface using slot die coating.

Abstract: The present invention is disclosed a semiconductor device which enables to easily perform a visual inspection of the bonded state between a lead and a land of wiring board. This semiconductor device comprises a lead in which at least a part of the lower surface thereof is exposed form the lower surface of the encapsulation resin and the end face thereof is exposed from the lateral surface of the encapsulation resin. The lower surface of the lead is provided with a groove which reaches the outer end edge of the lead.

Abstract: A stacked-type semiconductor device includes a plurality of semiconductor elements stacked on a wiring board. Electrode pads of these semiconductor elements are electrically connected to connection pads of the wiring board via metal wires respectively. The long-looped metal wires connected to the upper semiconductor element are fixed by a wire fixing resin portion to the short-looped metal wires connected to the lower semiconductor element. The wire fixing resin portion is filled at least between the metal wires. The stacked semiconductor elements are sealed by a sealing resin layer together with the metal wires.

Abstract: Provided are a semiconductor device producing method making production steps therein simple while preventing a matter that wire bonding cannot be attained due to contamination of a bonding pad and preventing the generation of a warp in an adherend such as a substrate, a lead frame, or a semiconductor element, thereby improving the yield; an adhesive sheet used in this method; and a semiconductor device obtained by this method. The invention includes a pre-setting step of pre-setting a semiconductor element 13 to an adherend 11 through an adhesive sheet 12, and a wire bonding step of wire bonding the element 13 in the bonding temperatures range of 80 to 250° C. without performing any heating step, wherein, as the adhesive sheet 12, a sheet having a storage elastic modulus of 1 MPa or more in the temperature range of 80 to 250° C. or a storage elastic modulus of 1 MPa or more at any temperature in the temperature range before curing the sheet 12 is used.

Abstract: An integrated circuit encapsulation system with vent is provided including providing a sheet material, forming a leadframe array on the sheet material, forming a leadframe air vent on the leadframe array, attaching an integrated circuit to the leadframe array, mounting the leadframe array in a mold and encapsulating the integrated circuit and the leadframe array.

Abstract: A method for activating a getter at low temperature for encapsulation in a device cavity containing a microdevice comprises etching a passivation layer off the getter material while the device wafer and lid wafer are enclosed in a bonding chamber. A plasma etching process may be used, wherein by applying a large negative voltage to the lid wafer, a plasma is formed in the low pressure environment within the bonding chamber. The plasma then etches the passivation layer from the getter material, which is directly thereafter sealed within the device cavity of the microdevice, all within the etching/bonding chamber.

Abstract: A stacked die system (10) has a first die (16) having a first surface with active circuitry, a second die (18) having a first surface with active circuitry, and a conductive shield (28) interposed between the first surface of the first die and the first surface of the second die. In one embodiment, the distance between the first surfaces of the first and second die is less than one millimeter. The stacked die system may also include a package substrate (12) where the active circuitry of the first and second die are electrically connected to the package substrate. The electrical connections may be formed using wire bonds (56, 58, 60, 62). Alternatively, the first die may be connected to the package substrate in a flip chip configuration. In one embodiment, the active circuitry of the first die generates RF signals where the shield helps protect the RF signals from interference caused by the active circuitry of the second die.