Encapsulations, E.g., Encapsulating Layers, Coatings, E.g., For Protection (epo) Patents (Class 257/E23.116)
  • Publication number: 20090011543
    Abstract: An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.
    Type: Application
    Filed: July 3, 2007
    Publication date: January 8, 2009
    Inventors: Tjandra Winata Karta, Steven Hsu, Chien-Hsiun Lee, Gene Wu, Jimmy Liang
  • Patent number: 7473994
    Abstract: A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a second step of forming a metal atomic layer on the substrate and forming an oxygen atomic layer on the metal atomic layer, wherein the concentration of the metal atoms in the insulator thin film is controlled by controlling the number of times the first step and the second step are carried out.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: January 6, 2009
    Assignee: Sony Corporation
    Inventor: Tomoyuki Hirano
  • Patent number: 7474008
    Abstract: A high reliability semiconductor device is provided which can prevent electromigration due to the deposition of metal ions originating from wires. The device includes: a flexible wiring board 11 including a base film 1 and multiple wires 9; a semiconductor chip 5 mounted to the flexible wiring board 11; and a sealing resin 6 disposed between the flexible wiring board 11 and the semiconductor chip 5 so as to at least partially in contact with the wires 9. The sealing resin 6 contains a metal ion binder mixed thereto.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: January 6, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhiko Fukuta, Kenji Toyosawa, Takashi Kidoguchi
  • Publication number: 20090001612
    Abstract: An integrated circuit package system comprising: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae
  • Publication number: 20090001613
    Abstract: An integrated circuit package system comprising: forming a substrate having a solder mask with a support structure formed from the solder mask; mounting a first integrated circuit device over the support structure; connecting the substrate and the first integrated circuit device; and encapsulating the first integrated circuit device and the support structure.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: Ja Eun Yun, Jong Wook Ju
  • Publication number: 20080308917
    Abstract: An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes a substrate embedding the package structure.
    Type: Application
    Filed: June 13, 2007
    Publication date: December 18, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Pressel, Gottfried Beer
  • Publication number: 20080308926
    Abstract: A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 18, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Min-Shun Hung, Ho-Yi Tsai, Chien-Ping Huang, Cheng-Hsu Hsiao
  • Publication number: 20080308922
    Abstract: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming in a material disposed on the surface portion of the semiconductor wafer device-exposing openings to exposed the devices and electrical contacts pads openings to expose electrical contact pads for devices; mounting a rigid dielectric layer over the formed material, such rigid material being suspended over the device exposing openings in the material and over the electrical contacts pads openings in the material; and forming electrical contact pad openings in portions of the rigid dielectric layer disposed over electrical contact pads of the devices with other portions of the rigid dielectric layer remaining suspended over the device exposing openings in the material.
    Type: Application
    Filed: June 14, 2007
    Publication date: December 18, 2008
    Inventors: Yiwen Zhang, Robert B. Hallock, Michael G. Adlerstein, Thomas E. Kazior, Susan C. Trulli
  • Patent number: 7466027
    Abstract: Interconnect structures are provided. An exemplary embodiment of an interconnect structure comprises a substrate with a low-k dielectric layer thereon. A via opening and a trench opening are formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and the via opening exposes a portion of the substrate. A liner layer is formed on sidewalls of the low-k dielectric layer exposed by the trench and via protions and a bottom surface exposed by the trench via portion, wherein the portion of the liner layer on sidewalls of the low-k dielectric layer exposed by the trench and via protions and the portion of the liner layer formed on a bottom surface exposed by the trench portion comprise different materials. A conformal conductive barrier layer is formed in the trench and via openings, covering the liner layer and the exposed portion of the substrate. A conductive layer is formed on the conductive barrier layer, filling in the trench and via openings.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: December 16, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chi Ko, Keng-Chu Lin, Chia-Cheng Chou
  • Publication number: 20080299288
    Abstract: A method of providing a durable protective coating structure which comprises at least three layers, and which is stable at temperatures in excess of 400° C., where the method includes vapor depositing a first layer deposited on a substrate, wherein the first layer is a metal oxide adhesion layer selected from the group consisting of an oxide of a Group IIIA metal element, a Group IVB metal element, a Group VB metal element, and combinations thereof; vapor depositing a second layer upon said first layer, wherein said second layer includes a silicon-containing layer selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride; and vapor depositing a third layer upon said second layer, wherein said third layer is a functional organic-comprising layer. Numerous articles useful in electronics, MEMS, nanoimprinting lithography, and biotechnology applications can be fabricated using the method.
    Type: Application
    Filed: May 5, 2008
    Publication date: December 4, 2008
    Inventors: Boris Kobrin, Dangaria Nikunji Hirji, Romuald Nowak, Michael T. Grimes
  • Publication number: 20080290482
    Abstract: A method of packaging integrated circuit dice into exposed die packages is described. The method includes depositing a metallic layer onto the back surface of an integrated circuit wafer such that it covers the back surface. The method additionally includes applying a protective layer over the metallic layer such that the protective layer covers the metallic layer. The method further includes singulating the wafer to produce individual dice. Each die may then be electrically connected to a lead frame. The die and portions of the lead frame may then be encapsulated with a molding compound. The protective layer inhibits the molding compound from contacting the metallic layer on the back surface of the die. The protective layer is then removed from the metallic layer. As a result, an individual IC package is produced that includes a die having a metallic layer exposed on the back surface of the die.
    Type: Application
    Filed: September 19, 2007
    Publication date: November 27, 2008
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jaime A. Bayan, Nghia Tu, Will K. Wong
  • Patent number: 7456049
    Abstract: A method of fabricating a lead frame for a semiconductor device having a semiconductor chip resin-sealed therein. The lead frame includes a lead to be electrically connected to the semiconductor chip within sealing resin and to be sealed into the sealing resin such that at least a part of its mounting surface is exposed from the sealing resin. The method includes a lead forming step for forming the lead, and a side edge coining step for subjecting a side edge of a sealed surface, which is a surface on the opposite side of the mounting surface, of the lead to coining processing from the side of the sealed surface, to form a slipping preventing portion. The slipping preventing portion is to project sideward from the lead and to have a slipping preventing surface between the mounting surface and the sealed surface of the lead.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: November 25, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Osamu Miyata
  • Publication number: 20080283952
    Abstract: Provided are a semiconductor package, a method of fabricating the same, and a semiconductor package module for an image sensor The semiconductor package includes a mounting portion on which a semiconductor chip is mounted; a semiconductor chip including a plurality of bonding pads disposed along an edge thereof, wherein the semiconductor chip adhered onto the mounting portion; a plurality of leads spaced apart from a sidewall of the semiconductor chip and having a greater height than the semiconductor chip; an encapsulant for fixing the mounting portion and the leads and encapsulating a bottom surface and a sidewall of the semiconductor package and exposing top and bottom surfaces of the leads; bonding wires for connecting the bonding pads of the semiconductor chip with the exposed top surfaces of the leads; and a transparent plate adhered onto the leads a predetermined space apart from the semiconductor chip.
    Type: Application
    Filed: December 22, 2006
    Publication date: November 20, 2008
    Inventors: Hyun-Kyu Choi, Chor Hong Koh
  • Publication number: 20080284047
    Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices in the first side. A polymeric stiffener ring is formed on the first side. The stiffener ring embeds the first plurality of passive devices without covering a central portion of the first surface of the substrate. A semiconductor chip is mounted on the central portion of the first surface of the substrate.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Inventors: Eric Tosaya, Jun Zhai, Chia-Ken Leong, Tom Ley
  • Publication number: 20080272503
    Abstract: A transfer mold process for encapsulation of a matrix array package of dice on a substrate is proposed wherein the flow of the mold compound between dice is at least partly obstructed. In other words, the flow velocity of the mold compound between dice is constrained with the goal of approximating it to the flow velocity above the dice. It is to be understood that every limitation of the flow velocity between the dice, even if it does not result in equal or uniform velocity throughout the cross-sectional area, will bring about a positive effect in terms of reducing the clustering of filler particles in certain areas of the mold compound. The semiconductor device thus produced is part of the present disclosure.
    Type: Application
    Filed: May 4, 2007
    Publication date: November 6, 2008
    Inventor: Henning Mieth
  • Publication number: 20080265388
    Abstract: An ultra thin image sensing chip package includes an image sensing chip and a flexible and optically transparent film. The chip has an image sensor and a plurality of electrical conductive pads. The flexible and optically transparent film includes a transparent window, and a pattern of conductors formed on a surface thereof and around the transparent window. The film wraps the chip in such a way that the transparent window thereof corresponds to the image sensor of the chip, a sealed space is formed between the transparent window and the image sensor, one end of each of the conductors of the film bonds to each of the electrical conductive pads of the chip, and the other end of each of the conductors of the film is opened so as to electrically connect with other electrical elements.
    Type: Application
    Filed: March 25, 2008
    Publication date: October 30, 2008
    Inventors: Jin-Chyuan BIAR, Chih-Kung Huang
  • Publication number: 20080265443
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Application
    Filed: June 24, 2008
    Publication date: October 30, 2008
    Applicant: Kabushiki Kaisha Toshiba,
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Publication number: 20080258318
    Abstract: Disclosed herewith is a semiconductor device capable of suppressing the peeling-off that might occur between an island and a resin layer due to a difference of the shrinkage between those items, thereby the reliability of the semiconductor device is improved. The semiconductor device of the present invention includes an island, a semiconductor chip mounted on the island, and a resin layer that seals the island and the semiconductor chip respectively. And at the interface between the island and the resin layer is provided a buffer film having an elastic modulus lower than that of the resin layer.
    Type: Application
    Filed: April 18, 2008
    Publication date: October 23, 2008
    Applicant: NEC Electronics Corporation
    Inventor: Naoto Kimura
  • Publication number: 20080251949
    Abstract: Example embodiments include molding apparatuses, semiconductor packages, a fabricating methods for fabricating the same. The molding apparatus may include a first mold die for adhering a partially completed package, a second mold die including a cavity formed such that the partially completed package is positioned inside the cavity and a molding resin for encapsulating the partially completed package inserted into the cavity, and a multi-layered film supply unit for supplying a multi-layered film to the cavity of the second mold die. The semiconductor package may include a substrate, a semiconductor chip electrically connected to the substrate, a molding resin for encapsulating the semiconductor chip and an electrical portion of the substrate, and a marking film, adhered to an outer surface of the molding resin such that a mark is marked in the marking film.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 16, 2008
    Inventors: Wha-Su Sin, Heui-Seog Kim, Jong-Keun Jeon
  • Patent number: 7432130
    Abstract: A method of packaging a semiconductor die (10) includes providing a flip-chip die (10) with bump connections (12) on its bottom surface (14). An adhesive tape (18) is attached to a plate surface (16) and lead fingers (20) are formed on the tape (18). The die (10) is placed on the tape (18) such that the bumps (12) on the die (10) contact respective ones of the lead fingers (20) on the tape (18). A reflow process is performed on the die (10), the tape (18) and the plate (16), which forms C5 type interconnects. A mold compound (24) is formed over the die (10) and the tape (18), and then the tape (18) and the plate (16) are removed.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: October 7, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Aminuddin Ismail, Chee Seng Foong, Ruzaini Ibrahim
  • Patent number: 7432604
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to simulate the components from the substrate. Prior to the simulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: October 7, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Publication number: 20080237897
    Abstract: Liquid crystalline epoxy compounds, compositions including the compounds, and methods of using the compositions are disclosed. In one aspect, an epoxy compound may have a melting point that is less than 140° C. and may be liquid crystalline at a temperature greater than 150° C.
    Type: Application
    Filed: May 6, 2008
    Publication date: October 2, 2008
    Inventors: James Christopher Matayabas, Paul Koning
  • Publication number: 20080237818
    Abstract: Methods and apparatus for providing an integrated circuit using a multi-stage molding process to protect wirebonds. In one embodiment, a method includes attaching a die to a leadframe having a lead finger, attaching a wirebond between the die and the leadfinger, applying a first mold material over at least a portion of the wirebond and the die and the leadfinger to form an assembly, waiting for the first mold material to at least partially cure, and applying a second mold material over the assembly.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Inventors: Raymond W. Engel, Nirmal Sharma, William P. Taylor
  • Patent number: 7429799
    Abstract: A semiconductor device has a substrate and an encapsulation area on a first surface of the substrate. A first plurality of metal lands is on the first surface of the substrate around a periphery of the encapsulation area. Solder mask covers portions of the first plurality of metal lands closest to the encapsulation area. Remaining portions of the first plurality of metal lands are exposed areas having no solder mask.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: September 30, 2008
    Assignee: Amkor Technology, Inc.
    Inventors: Akito Yoshida, Mahmoud Dreiza
  • Publication number: 20080224291
    Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 18, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Matt E. Schwab, J. Michael Brooks, David J. Corisis
  • Publication number: 20080224333
    Abstract: A semiconductor device is disclosed that includes a wiring board having a via formed therein; a semiconductor element provided on the wiring board; a resist layer covering a surface of the wiring board, the resist layer having an opening in a part thereof positioned on the via; and a sealing resin covering the surface of the via in the opening and the resist layer, and sealing the semiconductor device.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 18, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Norio Fukasawa
  • Patent number: 7425469
    Abstract: The invention relates to a method for encapsulating an electronic component, in particular a semiconductor, fixed on a carrier, comprising the processing steps of: a) placing at least one foil layer in a mould, b) placing the carrier in contact with the foil layer with the side remote from the component, and c) encapsulating the electronic component with encapsulating material, wherein the foil layer undergoes a treatment whereby the adhesion of the foil layer is increased such that it adheres to the carrier. The invention also relates to a foil material for applying during such a method.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: September 16, 2008
    Assignee: Fico B.V.
    Inventors: Wilhelmus Gerardus Jozef Gal, Franciscus Bernardus Antonius De Vries
  • Publication number: 20080220568
    Abstract: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion.
    Type: Application
    Filed: May 8, 2008
    Publication date: September 11, 2008
    Inventors: Akira MUTO, Ichio Shimizu, Katsuo Arai, Hidemasa Kagii, Hiroshi Sato, Hiroyuki Nakamura, Takuya Nakajo, Keiichi Okawa, Masahiko Osaka
  • Publication number: 20080217765
    Abstract: A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a support structure and encapsulated within a mold compound is mounted on the adhesive tape. A second semiconductor die is mounted to the packaged semiconductor die. Bond pads on the second semiconductor die are electrically connected to the leadframe, the support structure on which the first semiconductor die is mounted, or both. A mold compound is formed around the second semiconductor die, portions of the leadframe, and the packaged semiconductor die. The adhesive tape is removed and the leadframe is singulated to form multi-chip packages.
    Type: Application
    Filed: March 2, 2007
    Publication date: September 11, 2008
    Inventors: Jay A. Yoder, Joseph K. Fauty, James P. Letterman
  • Patent number: 7417325
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: August 26, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 7417330
    Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: August 26, 2008
    Assignee: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 7416913
    Abstract: Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes disposing a plurality of discrete stand-offs on the support member. The discrete stand-offs are arranged in arrays relative to corresponding imaging dies. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member, and attaching a plurality of covers to corresponding stand-off arrays so that the covers are positioned over the image sensors.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: August 26, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Frank L. Hall, William J. Reeder, Bret K. Street, James M. Derderian
  • Publication number: 20080197455
    Abstract: A semiconductor device having a rectangular exterior appearance includes a substrate for arranging an integrated circuit on the surface thereof, at least one rewire electrically connected to the integrated circuit via at least one pad electrode, at least one electrode terminal formed on the rewire, and a resin layer for completely sealing the substrate including the rewire such that the electrode terminal be exposed to the exterior. Slopes are formed at the corners between the backside and the side faces of the resin layer; and other slopes are further formed at the corners between the surface and the side faces of the resin layer. Thus, it is possible to reliably prevent the semiconductor device sealed with the resin layer from chipping or peeling irrespective of an impact occurring at the corners of the resin layer.
    Type: Application
    Filed: December 11, 2007
    Publication date: August 21, 2008
    Applicant: YAMAHA CORPORATION
    Inventor: Yoshio Fukuda
  • Patent number: 7407836
    Abstract: The invention relates to a high-voltage module comprising a housing (9) which accommodates at least one structural component (4, 5) that is fastened on a metal-ceramics substrate from a ceramic layer (1) comprising a first main face (11) and a second main face (12) opposite said first main face (11), an upper metal layer (15) on the first main face (11) and a lower metal layer (16) on the second main face (12). The high-voltage module is further characterized by comprising on the outer edges (14) of the substrate either a cast from weakly conductive particles (17) and a gel, or a cast from particles having a high dielectric constant as compared to the cast gel (17), and a gel.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: August 5, 2008
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Volker Gabler, Thomas Licht
  • Patent number: 7402457
    Abstract: A film, based on polyimide or epoxy, is laminated onto a surface of a substrate under a vacuum, so that the film closely covers the surface and adheres thereto. Contact surfaces to be formed on the surface are uncovered by opening windows in the film. A contact is established in a plane manner between each uncovered contact surface and a layer of metal. This establishes a large-surface contact providing high current density for power semiconductor chips.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: July 22, 2008
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kerstin Häse, Laurence Amigues, Herbert Schwarzbauer, Norbert Seliger, Karl Weidner, Jörg Zapf, Matthias Rebhan
  • Publication number: 20080164545
    Abstract: A MEMS microphone package includes a carrier, an application specific IC, an encapsulant and a microphone chip. The application specific IC and the microphone chip are respectively disposed on first and second surfaces of the carrier, and the application specific IC and the microphone chip are electrically connected to the carrier. The encapsulant includes first and second encapsulants, the first encapsulant is formed on the first surface to seal the application specific IC, the second encapsulant is formed on the second surface to become a cavity and the microphone chip is located at the cavity. Because the application specific IC and the microphone chip are disposed on the first and second surfaces of the carrier, respectively, the second encapsulant surrounds the microphone chip, and the first and second encapsulants are formed at the same time, it can increase the structural strength of package and reduce the process.
    Type: Application
    Filed: November 21, 2007
    Publication date: July 10, 2008
    Inventor: Wei-Min Hsiao
  • Patent number: 7397140
    Abstract: A chip module having a chip which is mounted by means of chip adhesive on a mount and is electrically connected via bonding wires to contact pads, and an encapsulation compound which surrounds the chip and the bonding wires and is bounded by a subarea of the mount. The encapsulation compound is radiation-hardened and heat-hardened in a combined form and has radiation-impermeable pigments.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: July 8, 2008
    Assignees: Infineon Technologies AG, Delo Industire Klebstoffe GmbH + Co. KG
    Inventors: Frank Puschner, Dietmar Dengler, Wolfgang Schindler, Thomas Spottl
  • Publication number: 20080160658
    Abstract: A mold structure for packaging LED chips includes a top mold and a bottom mold. The bottom mold is mated with the top mold. The bottom mold has a main flow channel, a plurality of receiving spaces formed beside the main flow channel, a plurality of secondary flow channels for respectively and transversely communicating the receiving spaces with each other, and a plurality of ejection pins penetrating through the bottom mold.
    Type: Application
    Filed: September 12, 2007
    Publication date: July 3, 2008
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, JONNIE CHUANG, HUI-YEN HUANG
  • Publication number: 20080157403
    Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.
    Type: Application
    Filed: June 28, 2007
    Publication date: July 3, 2008
    Inventors: Jung-Seock Lee, Ki-Won Nam
  • Publication number: 20080142996
    Abstract: According to one embodiment, a polymer coating is disposed on a surface of a package substrate. The polymer coating comprises a material capable of inhibiting the flow of an underfill material into a keep-out zone (KOZ). In a further embodiment, a die is disposed on the substrate and a layer of the underfill material is disposed between the die and substrate, and the polymer coating inhibits the flow of the underfill into the KOZ. Other embodiments are described and may be claimed.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Gopalakrishnan Subramanian, Nirupama Chakrapani, Lawrence D. Decesare, Shripad Gokhale, Jason M. Murphy, Jinlin Wang
  • Patent number: 7387914
    Abstract: A semiconductor chip is attached to a lead frame with a filmy organic die-bonding material having a water absorption of 1.5% by volume or less; having a saturation moisture absorption of 1.0% by volume or less, having a residual volatile component in an amount not more than 3.0% by weight, having a modulus of elasticity of 10 MPa or less at a temperature of 250° C. The semiconductor device thus obtained can be free from occurrence of reflow cracks during reflow soldering for the packaging of semiconductor devices.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: June 17, 2008
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Shinji Takeda, Takashi Masuko, Masami Yusa, Tooru Kikuchi, Yasuo Miyadera, Iwao Maekawa, Mitsuo Yamasaki, Akira Kageyama, Aizou Kaneda
  • Patent number: 7384822
    Abstract: The invention relates to a packaging for semiconductor components such as FBGA packages in BOC technology or the like, wherein at least the back and the lateral edges of a chip (2) mounted on a substrate are enclosed by a mold coating (6), the casting compound used for the mold coating (6) being linked with the substrate and forming an integrated whole therewith. The invention further relates to a method for producing such a packaging for semiconductor components. The aim of the invention is to provide a packaging for semiconductor components which is characterized by reduced thermomechanical stress and at the same time a substantially improved adhesion of the mold coating to the substrate, thereby allowing for a higher package load.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: June 10, 2008
    Assignee: Infineon Technologies AG
    Inventors: Juergen Zacherl, Stephan Blaszczak, Martin Reiss, Sylke Ludewig
  • Patent number: 7382059
    Abstract: In one embodiment, a semiconductor package is formed by adding a layer of particles to desired portions of a packing substrate. The layer of particles forms a matrix of crevices that provides a micro-lock feature for mechanically locking or engaging encapsulating materials.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: June 3, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Harold G. Anderson, Cang Ngo, Yong Li Xu, James Mohr
  • Publication number: 20080122082
    Abstract: According to the present invention, a semiconductor device, having an electrode pad as a part of wirings on the uppermost layer thereof, includes a passivation film and a bump electrode for external connection. The passivation film is formed on the electrode pad, and the bump electrode is formed on the passivation film and electrically connected to the electrode pad. The electrode pad is formed so as to be smaller in size than the bump electrode, and a part of the wiring on the uppermost layer are formed under the bump electrode. In this manner, it is possible to utilize the area under the bump electrode effectively without sacrificing flatness of the passivation film. As a result, the semiconductor device and the semiconductor package can be made smaller.
    Type: Application
    Filed: November 14, 2007
    Publication date: May 29, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Hiroshi YAMAMOTO, Eiji TAKEICHI
  • Patent number: 7378300
    Abstract: An integrated circuit package system is provided including forming a leadframe structure having a encapsulant space provided predominantly inside the leadframe structure and attaching a die to the leadframe structure in the encapsulant space inside the leadframe structure. The system further includes electrically connecting the die to the leadframe structure and injecting encapsulant into the encapsulant space to form the integrated circuit package system.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: May 27, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Pandi Chelvam Marimuthu, Il Kwon Shim
  • Patent number: 7378301
    Abstract: A method for molding digital storage memory cards such as, for example, multimedia cards (MMC), secure digital cards (SD), and similar small form factor digital memory cards. A PCA subassembly including, for example, a leadframe (TSOP) package for enclosing a flash IC and a (e.g., land grad array) controller package for enclosing a controller IC are mounted on a printed wiring board within a mold cavity. A high melt flow index resin is injected into the mold cavity to form an integral, solid body within which to completely encapsulate the flash IC and controller packages and form a cover over top the flash IC package so as to maintain the required memory card height tolerance. In one embodiment, the resin material is injected downwardly into the mold cavity from locations above the respective rows of leads of the flash IC package.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: May 27, 2008
    Assignee: Kingston Technology Corporation
    Inventors: Wei H. Koh, Ben W. Chen, David H. D. Chen
  • Publication number: 20080108182
    Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 8, 2008
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chien Ping Huang, Yu-Po Wang, Chih-Ming Huang
  • Publication number: 20080093722
    Abstract: An encapsulation type semiconductor device and a manufacturing method of the encapsulation type semiconductor device are disclosed. The encapsulation type semiconductor device includes a substrate provided with a concave portion which concaves in a direction from a first principal surface portion to a second principal surface portion. A first semiconductor chip using MEMS is mounted on the concave portion. A first principal surface portion of a second semiconductor chip faces at least the concave portion of the substrate with a space interposed between the first principal surface portion and the concave portion. An outer peripheral side of the concave portion of the first principal surface portion of the substrate is connected with the first principal surface portion of the second semiconductor chip facing the concave portion, by use of a connecting portion.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 24, 2008
    Inventor: Norihiko Shishido
  • Publication number: 20080088002
    Abstract: A chip package structure includes a substrate having a cavity, wherein the substrate includes a plurality of first contacts and second contacts disposed on a surface thereof, and the first contacts are located within the cavity and the second contacts are located outside the cavity. The substrate further includes a through hole located at the bottom of the cavity. A first chip is disposed in the cavity, wherein the first chip is electrically connected to the first contacts. A second chip is disposed above the cavity, wherein the second chip is electrically connected to the second contacts. A third chip is disposed in the through hole, wherein the third chip is attached to the first chip. An encapsulant is filled in the cavity to encapsulate the first chip and the second chip.
    Type: Application
    Filed: November 30, 2007
    Publication date: April 17, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chao-Ming Tseng
  • Patent number: 7352070
    Abstract: Improved encapsulated, overmolded and/or underfilled electrical components having a complete encapsulation, overmolding and/or underfilling with a coefficient of thermal expansion that is uniform and substantially free of gradients includes a polymeric matrix and an inorganic filler having a platelet geometric structure. The platelet structure of the filler allows a desirable coefficient of thermal expansion to be achieved using a very low level of filler material. This low level of filler material facilitates lower viscosity during forming of the encapsulation and/or overmolding, thereby facilitating complete filling of a mold cavity and underfilling of space between a circuit board and a semi-conductor chip electrically connected to the circuit board. In addition, the low viscosity has processing advantages that reduce the potential for damage to electrical components during encapsulation, overmolding and/or underfilling.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: April 1, 2008
    Assignee: Delphi Technologies, Inc.
    Inventors: Thomas S. Ellis, Glen E. Novak, Bruce A. Myers, Scott D. Brandenburg, Jeenhuei S. Tsai