Abstract: The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.

Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

Abstract: An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a semiconductor device with a high yield. A first insulator and a second insulator facing each other, a semiconductor integrated circuit and an antenna provided between the first insulator and the second insulator facing each other, a conductive shield provided on one surface of the first insulator, and a conductive shield provided on one surface of the second insulator are provided. The conductive shield provided on one surface of the first insulator and the conductive shield provided on one surface of the second insulator are electrically connected.

Abstract: A conductive shield covering a semiconductor integrated circuit prevents electrostatic breakdown of the semiconductor integrated circuit (e.g., malfunction of a circuit and damage to a semiconductor element) due to electrostatic discharge. Further, with use of a pair of insulators between which the semiconductor integrated circuit is sandwiched, a highly reliable semiconductor having resistance can be provided while achieving reduction in the thickness and size. Moreover, also in the manufacturing process, external stress, or defective shapes or deterioration in characteristics resulted from electrostatic discharge are prevented, and thus the semiconductor device can be manufactured with high yield.

Abstract: In a method of producing an integrated circuit (1, 91, 131) for a transponder (2, 112) a photoresist layer (11) is applied on a first surface (8) of a semiconductor device (3). A patterned mask (14, 94) is generated by lithographically patterning the photoresist layer (11), so that the photoresist layer (11) comprises at least one first via (12, 13). The patterned mask (14, 94) comprises a second surface (17) facing away from the first surface (8). The first via (12, 13) is filled with a first bump (15, 16) by depositing the first bump (12, 13) on the first surface (8). A conductive structure (18, 19, 98, 99, 132) is formed on the second surface (17) of the patterned mask (14, 94). The conductive structure (18, 19, 98, 99, 132) is electrically connected to the first bump (15, 16).

Abstract: A process for fabricating multiple microfluidic device chips. The process includes fabricating multiple micromachined tubes in a semiconductor device wafer. The tubes are fabricated so that each tube has an internal fluidic passage and an inlet and outlet thereto defined in a surface of the device wafer. The device wafer is then bonded to a glass wafer to form a device wafer stack, and so that through-holes in the glass wafer are individually fluidically coupled with the inlets and outlets of the tubes. The glass wafer is then bonded to a metallic wafer to form a package wafer stack, so that through-holes in the metallic wafer are individually fluidically coupled with the through-holes of the glass wafer. Multiple microfluidic device chips are then singulated from the package wafer stack. Each device chip has a continuous flow path for a fluid therethrough that is preferably free of organic materials.

Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.

Abstract: A method of manufacturing a micromodule including the steps of: producing an integrated circuit on an active face of a chip made of a semi-conductive material, making a via passing through the chip, electrically linked to the integrated circuit, and inserting the chip into a box comprising a cavity and an electrically conductive element, the active face of the chip being disposed towards the bottom of the cavity, forming on at least one part of a lateral face of the chip a conductive lateral layer made of an electrically conductive material, electrically linked to a conductive element of the rear face of the chip, and producing a connection between the conductive lateral layer and the conductive element by depositing an electrically conductive material in the cavity.

Abstract: At a semiconductor device, an integrated circuit including an optoelectronic conversion device is formed on a front face of a sensor chip. A rewiring layer, which leads from pad electrodes, and post electrodes, on the rewiring layer, are formed on the sensor chip. At least a portion of surroundings of the rewiring layer and the post electrodes is sealed with sealing resin, so as to be open above the integrated circuit face. A light-transmissive substrate is disposed over the sealed sensor chip. Penetrating electrodes, corresponding with positions of the post electrodes disposed on the sensor chip, are formed in the light-transmissive substrate, and external terminals such as solder balls or the like are formed so as to electrically connect with the penetrating electrodes.

Abstract: The present disclosure relates to methods of treating a silicon substrate with an ultra-fast laser to create a getter material for example in a substantially enclosed MEMS package. In an embodiment, the laser treating comprises irradiating the silicon surface with a plurality of laser pulses adding gettering microstructure to the treated surface. Semiconductor based packaged devices, e.g. MEMS, are given as examples hereof.

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract: A multilayer wiring substrate included in the semiconductor package includes: a first insulating layer and a second insulating layer, in which wiring layers are respectively provided on the upper and the lower surfaces; and; a core layer provided between the first insulating layer and the second insulating layer. The first insulating layer and the second insulating layer are constituted by different materials from each other.

Abstract: A semiconductor device includes a chip, a laminated wiring structure formed integrally with the chip, a frame disposed to surround the chip and made of a material having stiffness, and a sealing resin formed to bury therein the frame and at least the periphery of the side surface of the chip. The laminated wiring structure includes a required number of wiring layers, which are formed by patterning in such a manner that a wiring pattern directly routed from an electrode terminal of the chip is electrically connected to pad portions for bonding external connection terminals, the pad portions being provided, at a position directly below a mounting area of the chip and at a position directly below an area outside the mounting area, on a surface to which the external connection terminals are bonded.

Abstract: Disclosed are a micro electro mechanical system (MEMS) device and a package thereof. The packaging method of a MEMS device comprises: sequentially forming a sacrificial layer, a support layer, and a block copolymer layer on a substrate on which the MEMS device is formed; self-assembling the block copolymer layer formed on the support layer; selectively etching a part of the self-assembled block copolymer layer to form a plurality of nano-pores; forming a plurality of etching holes in the support layer corresponding to the plurality of nano-pores using the block copolymer layer in which the plurality of nano-pores are formed as a mask; removing the sacrificial layer using the etching holes formed in the support layer; and forming a shielding layer on the support layer.

Abstract: A suspension microstructure and its fabrication method, in which the method comprises the steps of: forming at least one insulation layer with inner micro-electro-mechanical structures on an upper surface of a silicon substrate, the micro-electro-mechanical structure includes at least one microstructure and a plurality of metal circuits that are independent from each other, the micro-electro-mechanical structures have an exposed portion on the surface of the insulation layer, and the exposed portion is provided with through holes or stacked metal-via layers correspondingly to the predetermined etching spaces of the micro-electro-mechanical structures, the above predetermined etching spaces and the stacked metal-via layers only penetrate the insulation layer; forming a photoresist with an opening on the upper surface of the exposed portion, and the opening of the photoresist is located outside all the through holes or the stacked metal-via layers; subsequently, conducting etching to realize the suspension of t

Abstract: An IC tag comprises a substrate on which a wiring pattern is formed, an IC chip which is bonded and mounted to the substrate by bringing a bump into press-contact with the wiring pattern, a repulsive member that is arranged on the surface opposite to the surface of the substrate on which surface the IC chip is mounted, and that is made of a material having higher rigidity than the substrate, and an exterior package member which is configured to cover the substrate, the IC chip, and the repulsive member.

Abstract: A rectifying diode package structure includes a base which has a holding deck to hold a diode chip and a protective portion on the perimeter of the base to form sealing space filled by a filling material to seal the diode chip in an integrated manner. The diode chip has a conductive element extended outside the sealing space. The holding deck and the protective portion are interposed by a buffer ring embedded in the filling material. The buffer ring has at least one retaining ridge which has at least one first end and one second end of different cross sections formed in an upright manner to form a retaining relationship between the buffer ring and the filling material.

Abstract: A sensor device having small variations in sensor characteristics and improved resistance to electrical noise is provided. This sensor device has a sensor unit, which is provided with a frame having an opening, a movable portion held in the opening to be movable relative to the frame, and a detecting portion for outputting an electric signal according to a positional displacement of the movable portion, and a package substrate made of a semiconductor material, and bonded to a surface of the sensor unit. The package substrate has an electrical insulating film on a surface facing the sensor unit. The package substrate is bonded to the sensor unit by forming a direct bonding between an activated surface of the electrical insulating film and an activated surface of the sensor unit at room temperature.

Abstract: A semiconductor module includes: a plastic housing composition; at least one semiconductor chip with an active top side, a coplanar underside of the semiconductor module including the active top side of the semiconductor chip(s) and a surface of the plastic housing composition; a wiring structure arranged on the coplanar underside, the wiring structure including a center region and edge regions, with external contact areas distributed uniformly in the center region; external contacts arranged on the external contact areas of the wiring structure; and at least one surface-mountable semiconductor component arranged on the wiring structure in at least one of the edge regions, the surface-mountable semiconductor component(s) having a structural height that is less than the height of the external contacts.

Abstract: A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.

Abstract: The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate.

Abstract: An object of the invention is to provide a smaller semiconductor device of which the manufacturing process is simplified and the manufacturing cost is reduced and a method of manufacturing the same. Furthermore, an object of the invention is to provide a semiconductor device having a cavity. A first supporting body 5 having a penetration hole 6 penetrating it from the front surface to the back surface is attached to a front surface of a semiconductor substrate 2 with an adhesive layer 4 being interposed therebetween. A device element 1 and wiring layers 3 are formed on the front surface of the semiconductor substrate 2. A second supporting body 7 is attached to the first supporting body 5 with an adhesive layer 8 being interposed therebetween so as to cover the penetration hole 6. The device element 1 is sealed in a cavity 9 surrounded by the semiconductor substrate 2, the first supporting body 5 and the second supporting body 7.

Abstract: Provided are wafer level chip scale packages, each having a redistribution substrate in which a pad pitch is improved, and methods of fabricating the same. An exemplary wafer level chip scale package includes a semiconductor chip and a redistribution substrate. The semiconductor chip includes a plurality of pads arranged with a first pitch on a first surface thereof. The redistribution substrate includes a plurality of connection wires arranged with a second pitch, which is greater than the first pitch, on a first surface thereof. The redistribution substrate expands a pad pitch from the first pitch to the second pitch by electrically connecting the pads to the connection wires.

Abstract: Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder out of the solder connections to form openings within the underfill matrix. The underfill material is then removed to expose metallurgy of the substrate. A blank having a release layer with an array of solder connections is aligned with the exposed metallurgy, and this solder array is transferred from the blank onto the metallurgy. The transferred solder connections are then flattened using heat and pressure, followed by attaching solder connections of a new component to the flattened solder connections and underfilling these reworked solder connections residing between the new chip and substrate.

Abstract: A functional device includes: a substrate; a functional structure formed on the substrate; a cavity in which the functional structure is disposed; and a cover which covers the cavity, wherein the cover includes a bumpy structure including rib shaped portions, or groove shaped portions, which cross a covering range covering at least the cavity.

Abstract: A substrate 10 for a semiconductor device includes: a base plate 1, a plurality of external terminal portions 12p, 12q, respectively arranged in a plane on the base plate 1 and having external terminal faces 12pb, 12qb respectively facing the base plate 1; a plurality of internal terminal portions 11, respectively arranged in the plane on the base plate 1 and having internal terminal faces 11a respectively facing an opposite side to the base plate 1. The internal terminal portions 11 are connected with the external terminal portions 12p, 12q, via wiring portions 17, respectively. A part of the external terminal portions 12p are located on the base plate 1 in a predetermined arrangement area A in which a semiconductor element 50 is arranged.

Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

Abstract: A semiconductor unit includes an interface plate, a supporting plate integrally formed with the interface plate, two chip packages positioned at opposite sides of the supporting plate, and leading traces running in the interface plate and the supporting plate, connected with the chip packages respectively.

Abstract: A semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality of through interconnects in the substrate, and redistribution conductors on the back side of the substrate. Each through interconnect includes a via aligned with a substrate contact, and a conductive layer at least partially lining the via in physical and electrical contact with the substrate contact. Each redistribution conductor is formed by a portion of the conductive layer. A system includes a supporting substrate and at least one semiconductor substrate having the through interconnects and the redistribution conductors.

Abstract: Molded leadless packages having improved stacked structures are disclosed. An exemplary molded leadless package includes a die attaching pad, a plurality of leads spaced apart from the die attaching pad at a periphery region of the die attaching pad, a semiconductor chip on the die attaching pad, a plurality of bonding wires electrically connecting the leads to the semiconductor chip, and a sealing member fixedly enclosing the semiconductor chip and the bonding wires while partly exposing an outer surface of each of the leads. The sealing member fills gaps between the die attaching pad and the leads and includes at least one protrusion protruding downward from the die attaching pad and the leads.

Abstract: A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner opening is located on the inner side of the first seal ring. The outer opening is located on the outer side of the first seal ring. The outer opening and the inner opening are not aligned. The connecting groove connects the inner opening and the outer opening.

Abstract: A semiconductor device includes: a semiconductor element; a package body having the semiconductor element bonded inside thereof and electrically connected to the semiconductor element; a lid-like member covering the semiconductor element, and bonded to the package body to form a hollow structure; and a bonding member for bonding the package body and the lid-like member to each other. The bonding member is a resin adhesive containing an epoxy resin, a polymerization initiator, and a filling material, and a content of the filling material in the bonding member is 30 wt % to 60 wt %.

Abstract: A mount for a semiconductor device has a first surface with at least one contact region and a second surface. The mount has a substrate to receive the second surface of the semiconductor device and a planar element. The planar element has an aperture sized to surround the semiconductor. A first surface of the planar element is mounted to the substrate and is located to surround the semiconductor device such that the semiconductor device is aligned by the aperture. The mount further has means for mounting the semiconductor device to the substrate in an aligned position. Some embodiments include a method of making and/or using such a mount.

Abstract: According to the present invention, protrusions 4 are formed on electrodes 3 of semiconductor elements 6, and an optical member 7 is secured on the semiconductor element 6 with an adhesive 8 so as to be pressed onto the protrusions 4.

Abstract: A design method of a semiconductor device comprising forming a base wafer by using a plurality of semiconductor chips including a plurality of functional macros, generating macro test information by testing the plurality of function macros of the plurality of semiconductor devices; and picking a macro that is prohibited from being used out of the plurality of function macros based on the macro test information and a net list of user circuit. Since tests are carried out at the phase of a base wafer, it is possible to improve yield rates in the manufacture of semiconductor integrated circuits.

Abstract: A system including an inter-chip communication system is disclosed. One embodiment includes a base chip including a base chip transceiver network. At least one chip is stacked on the base chip, the at least one stacked chip including a substrate, a cavity formed in the substrate, a first surface, and a stacked chip transceiver network disposed on the first surface adjacent to the cavity.

Abstract: A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.

Abstract: An integrated circuit package system comprising: providing a substrate having a cavity; sealing a package over the cavity of the substrate; and forming an encapsulant over the package and a portion of the substrate substantially preventing the encapsulant from forming in the cavity.

Abstract: Methods and apparatus provide for: applying an inorganic barrier layer to at least a portion of a flexible substrate, the barrier layer being formed from a low liquidus temperature (LLT) material; and sintering the inorganic barrier layer while maintaining the flexible substrate below a critical temperature.

Abstract: A semiconductor package in which an electronic device chip is provided in a cavity of a silicon substrate stacked product constituted by stacking a plurality of silicon substrates.

Abstract: The present invention relates to a stacked package module and a method for fabricating the same. The stacked package module comprises: a first package structure, a second package structure, a ceramic-surfaced aluminum plate, and a metal paste. Herein, the ceramic-surfaced aluminum plate has a plurality of through holes filled with the metal paste to correspond with and electrically connect the first conductive pads of the first package structure and the second conductive pads of the second package structure; and the ceramic-surfaced aluminum plate further has a first cavity to receive a chip. Besides, the present invention provides a stacked package module, which can avoid warpage, omit the process for soldering, favor the shrinkage of size and pitch of the conductive pads, and also can reduce the height of the package.

Abstract: According to the present invention, a method for making a micro-electro-mechanical system (MEMS) device comprises: providing a substrate with devices and interconnection formed thereon, the substrate having a to-be-etched region; depositing and patterning an etch stop layer; depositing and patterning metal and via layers to form an MEMS structure, the MEMS structure including an isolation region between MEMS parts, an isolation region exposed upwardly, and an isolation region exposed downwardly, wherein the isolation region exposed downwardly is in contact with the etch stop layer; masking the isolation region exposed upwardly, and removing the isolation region between MEMS parts; and removing the etch stop layer.

Abstract: An optical device includes a semiconductor substrate (11) on which a light receiving part (12) (or a light emitting part) and electrodes (13) are formed, and a translucent plate (2) bonded on the light receiving part (12) with a translucent adhesive (5), the semiconductor substrate (11) having a plurality of convex portions (31) formed so as to separate the light receiving part (12) and the electrodes (13) and have proper gaps (32) therebetween.

Abstract: A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.

Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.

Abstract: A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips with a semiconductor chip body having an upper surface, a lower surface, side surfaces coupling the upper surface and the lower surface, and a circuit part. The semiconductor chips include pads coupled to the circuit part and disposed at an edge of the upper surface. A recess parts are concavely formed in the side surfaces corresponding to each pad. Conductive connection patterns cover the recess parts, and each conductive connection pattern is electrically connected to a corresponding bonding pad. The semiconductor chip module is disposed on a substrate, and the contact pads of the semiconductor substrate are electrically connected to the conductive connection patterns. The stacked semiconductor package provides an improved structure that can contain a plurality of stacked semiconductor chips with no reduction in data storage capacity.

Abstract: Provided are a semiconductor device and a method of fabricating the same, and more particularly, a semiconductor package and a method of fabricating the semiconductor package. The semiconductor package includes a first package that comprises a first substrate, at least one first semiconductor chip stacked on the first substrate, and first conductive pads exposed on a top surface of the first substrate; a second package disposed below the first package such that the second package comprises a second substrate, at least one second semiconductor chip, and second conductive pads exposed on a bottom surface of the second substrate; and a connection unit that extends from the first conductive pads to the second conductive pads such that the connection unit covers a side surface of the first package and a side surface of the second package in order to electrically connect the first package to the second package.

Abstract: Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.

Abstract: An integrated circuit packaging system including: forming a base structure, having an opening; mounting a base structure device in the opening; attaching an integrated circuit device over the base structure device; and molding an encapsulant on the base structure, the base structure device, and the integrated circuit device.