Abstract: Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.

Abstract: A micromechanical device having a substrate wafer has at least one first cavity and one second cavity, the cavities being hermetically separated from each other, the first cavity having a different internal atmospheric pressure than the second cavity. The cavities are capped by a thin film cap. A method is for manufacturing a micromechanical device which has a thin film cap having cavities of different internal atmospheric pressures.

Abstract: A crack stopping structure is disclosed. The crack stopping structure includes a semiconductor substrate having a die region, a die seal ring region, and a scribe line region; a metal interconnect structure disposed on the semiconductor substrate of the scribe line region; and a plurality of dielectric layers disposed on the semiconductor substrate of the die region, the die seal ring region, and the scribe line region. The dielectric layers include a first opening exposing the surface of the metal interconnect structure of the scribe line region and a second opening exposing the dielectric layer adjacent to the metal interconnect structure such that the metal interconnect structure and the exposed portion of the dielectric layer form a step.

Abstract: A semiconductor module includes a base plate, at least one semiconductor chip mounted on the base plate, a case fixed to the base plate and surrounding the at least one semiconductor chip, an electrically insulating gel layer covering the at least one semiconductor chip, a thermosetting resin layer formed on top of the gel layer, and a lid formed on top of the thermosetting resin layer. The lid comprises a lid-extension, which defines a lid-opening. The lid-opening extends through the thermosetting resin layer to the gel layer and allows gel of the gel layer to expand into the lid-opening.

Abstract: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced.

Abstract: An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer 120 having heat conductive particles 125 suspended therein. A portion of the particles are exposed on at least one non-planar surface 135 of the resin layer such that the portion of exposed particles 130 occupies a majority of a total area of a horizontal plane 140 of the non-planar surface.

Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

Abstract: A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element g

Abstract: A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures.

Abstract: A hermetic package for electronic components which is made of metallic silicon is disclosed. The package includes a plurality of silicon elements which are bonded together. In the first embodiment, a cavity is hollowed out in the cover to house the Application Specific Integrated Circuit oscillator and the resonator. In a second embodiment, the cavity is formed in the base member with a plurality of pedestal shelves to hold the resonator above and out of contact with the electrical circuitry for the oscillator and thermal controls.

Abstract: A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes.

Abstract: A semiconductor chip includes an integrated circuit region, at least one alignment indicator region and a seal-ring. The alignment indicator region is disposed near the integrated circuit region. The seal-ring surrounding the integrated circuit region is disposed outside of the integrated circuit region, and is formed as a mark for alignment on the alignment indicator region at a corner of the semiconductor chip. A manufacturing process of the seal-ring structure is also disclosed.

Abstract: A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Abstract: A semiconductor package includes a package body with a cavity housing a first integrated circuit die. A wireless tag including a wireless element and an antenna is embedded in the semiconductor package. In one embodiment, the antenna is embedded in the package body of the semiconductor package. In another embodiment, the antenna is formed on or in the first integrated circuit die housed in the semiconductor package. According to another aspect of the present invention, the semiconductor package may be mounted on a printed circuit board and a second antenna is formed on the printed circuit board in electrical connection to the antenna embedded in the semiconductor package.

Abstract: A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.

Abstract: A method of manufacturing a micromodule including the steps of: producing an integrated circuit on an active face of a chip made of a semi-conductive material, making a via passing through the chip, electrically linked to the integrated circuit, and inserting the chip into a box comprising a cavity and an electrically conductive element, the active face of the chip being disposed towards the bottom of the cavity, forming on at least one part of a lateral face of the chip a conductive lateral layer made of an electrically conductive material, electrically linked to a conductive element of the rear face of the chip, and producing a connection between the conductive lateral layer and the conductive element by depositing an electrically conductive material in the cavity.

Abstract: A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.

Abstract: A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.

Abstract: The present invention relates to a semiconductor package having an antenna. The semiconductor package includes a substrate, a chip, a molding compound and an antenna. The substrate has a first surface and a second surface. The chip is disposed on the first surface of the substrate, and electrically connected to the substrate. The molding compound encapsulates the whole or a part of the chip. The antenna is disposed on the molding compound, and electrically connected to the chip. The antenna is disposed on the molding compound that has a relatively large area, so that the antenna will not occupy the space for the substrate.

Abstract: Provided is a manufacturing apparatus that manufactures an integrated circuit package by packaging an integrated circuit chip, the manufacturing apparatus comprising a flattening section that flattens the integrated circuit chip; a holding section that holds a base substrate; a transporting section that transports the flattened integrated circuit chip to load the integrated circuit chip on the base substrate held by the holding section; and a packaging section that packages the integrated circuit chip and the base substrate as the integrated circuit package.

Abstract: A package of a MEMS microphone is suitable for being mounted on a printed circuit board. The package includes a substrate, at least one MEMS microphone, and a conductive sealing element. The MEMS microphone is arranged on the substrate, and electrically connected to a conductive layer on a bottom surface of the substrate. The conductive sealing element is arranged on the substrate and around the MEMS microphone for connecting the printed circuit board, and constructs an acoustic housing with the printed circuit board and the substrate. The acoustic housing has at least one acoustic hole passing through the substrate. The acoustic hole has a metal layer on the inner wall thereof for connecting the conductive layer on the bottom surface of the substrate to another conductive layer on the top surface of the substrate.

Abstract: A structure comprising a cavity delimited by a first substrate and a second substrate attached to the first substrate by an adhesion interface, in which a first part of a first portion of a getter material forms part of the adhesion interface, and a second part of the first portion of getter material is placed in the cavity, the first portion of getter material being placed against the first substrate or the second substrate, the adhesion interface further comprising part of a second portion of a getter material thermocompressed to the first part of the first portion of getter material, said second portion of getter material being placed against the second substrate when the first portion of getter material is placed against the first substrate or placed against the first substrate when the first portion of getter material is placed against the second substrate.

Abstract: The present invention relates to a chip card and a method for the production of a chip card having a chip (21) which is arranged in a card body, and having a plurality of components (18, 19, 22) being electrically conductively connected to the chip by means of a conductor arrangement (20), wherein the card body is composed of a plurality of substrate layers (11, 12, 13) which are arranged in a layer structure, wherein the components and the conductor arrangement are arranged in different substrate layers, specifically a component layer arrangement and a connecting layer arrangement, and have contact surfaces (23, 24, 25, 26, 31, 32, 33, 34), which are disposed so as to overlap one another, for producing an electrically conductive contacting.

Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.

Abstract: A semiconductor package includes a chip, a carrier, a bonding wire and a molding compound. The chip includes a pad. The carrier includes a finger and has an upper surface and a lower surface opposite to the upper surface, wherein the upper surface supports the chip. The bonding wire is extended from the finger to the pad for electrically connecting the chip to the carrier, wherein the bonding wire defines a projection portion on the upper surface of the carrier, a straight line is defined to pass through the finger and pad, there is a predetermined angle between the tangent line of the projection portion at the finger and the straight line. The molding compound seals the chip and the bonding wire, and covers the carrier.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.

Abstract: A kind of microphone package structure includes at least of a substrate, a sound processing unit, an upper cap and other devices. There would be at least one trench set on the substrate, and a separation gap between the trench and the bonding pad of the substrate is maintained. After connective paste is smeared on the surface of the substrate, the trench would be assembled with other devices. This kind of package structure could prevent a short circuit being caused by the overflowing of the connective paste.

Abstract: A sensing device comprises a substrate having an upper surface, a sensor member, at least an external conductive wire, and a standing-ring member. The sensor member, the external conductive wire and the stand-ring member are on the upper surface. The sensor member is located at the central area on the upper surface, and the standing-ring member surrounds the sensor member. The standing-ring member and the sensor member are electrically connected through the at least an external conductive wire.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a first substrate; bonding a second substrate to the first substrate, the second substrate including a microelectromechanical system (MEMS) device; and bonding a third substrate to the first substrate.

Abstract: A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are arranged in a contiguous region of an terminal area of the multi-chip module.

Abstract: An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor.

Abstract: A semiconductor device includes: a first substrate made of semiconductor and having first regions, which are insulated from each other and disposed in the first substrate; and a second substrate having electric conductivity and having second regions and insulation trenches. Each insulation trench penetrates the second substrate so that the second regions are insulated from each other. The first substrate provides a base substrate, and the second substrate provides a cap substrate. The second substrate is bonded to the first substrate so that a sealed space is provided between a predetermined surface region of the first substrate and the second substrate. The second regions include an extraction conductive region, which is coupled with a corresponding first region.

Abstract: A hermetically sealed MEMS device package comprises a MEMS device platform, a hermetic interface chip, and an outer seal ring. The MEMS device platform includes a MEMS device surrounded by a continuous outer boundary wall with a top surface. The hermetic interface chip includes a glass substrate and at least one silicon mesa. The glass substrate includes at least one hole and has a lower surface with an inner portion surrounded by an outer portion. The at least one silicon mesa is bonded to the inner portion of the lower surface of the glass substrate, such that the at least one silicon mesa is aligned with the at least one hole in the glass substrate. The outer seal ring bonds the outer portion of the lower surface of the glass substrate to the top surface of the continuous outer boundary wall of the MEMS device platform.

Abstract: A method for producing a device including at least one integrated circuit and at least one N/MEMS. The method produces the N/MEMS in at least one upper layer arranged at least above a first section of a substrate, produces the integrated circuit in a second section of the substrate and/or in a semiconductor layer arranged at least above the second section of the substrate, and further produces a cover encapsulating the N/MEMS from at least one layer used for production of a gate in the integrated circuit and/or for producing at least one electrical contact of the integrated circuit.

Abstract: An integrated circuit package includes a thermally and electrically conductive package lid. The package lid may be in electrical communication with an electrically conductive pad connected to a power plane, ground plane, or signal route in the integrated circuit. The electrically conductive package lid may provide an electrical connection for electrical power or electrical signals or may serve as an electrical ground. In some embodiments, the package lid may include a thermally and electrically conductive material. In other embodiments, the package lid may include an electrically insulative substrate coated on at least one surface with a layer of metal or another conductive material. The conductive layer may be electrically connected to electrical ground, a reference voltage, or a signal pay by at least one electrically conductive via.

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Abstract: An electronic component capable of withstanding stress from a printed-circuit board or the like is provided. In an electronic component, a cavity hermetically sealed by a base and a lid is formed. In the cavity, a crystal resonator is supported by a supporting member over the top surface of the base. The base is made of glass. A stress buffer layer made of a conductive resin or the like is formed over the whole bottom surface of the base. An external electrode and an external electrode that are in continuity with the electrodes of the crystal resonator individually extend to the bottom surface of the stress buffer layer via the side surfaces of the base and stress buffer layer. The thus configured electronic component is surface-mounted by, for example, soldering the external electrode and external electrode formed on the bottom surface of the stress buffer layer to a printed-circuit board.

Abstract: A method for producing a nitride semiconductor laser light source is provided. The nitride semiconductor laser light source has a nitride semiconductor laser chip, a stem for mounting the laser chip thereon, and a cap for covering the laser chip. The laser chip is encapsulated in a sealed container composed of the stem and the cap. The method for producing this nitride semiconductor laser light source has a cleaning step of cleaning the surface of the laser chip, the stem, or the cap. In the cleaning step, the laser chip, the stem, or the cap is exposed with ozone or an excited oxygen atom, or baked by heat. The method also has, after the cleaning step, a capping step of encapsulating the laser chip in the sealed container composed of the stem and the cap. During the capping step, the cleaned surface of the laser chip, the stem, or the cap is kept clean.

Abstract: A nickel-based material is used on one or both wafers to be bonded, and the two wafers are bonded at low temperature and pressure through interdiffusion of the nickel-based material with either another nickel-based material or aluminum. In various embodiments, nickel-based walls are formed on one wafer, and corresponding walls are formed on the other wafer from a nickel-based material or aluminum. The walls of the two wafers are placed in contact with one another under sufficient pressure and temperature to cause bonding of the walls through interdiffusion.

Abstract: A semiconductor module and a method for producing the same is disclosed. In one embodiment, the semiconductor module has adjacent regions on a common wiring substrate in a common plastic housing composition. The regions are thermally decoupled by a thermal barrier. Semiconductor chips whose evolution of heat loss differs are arranged in these thermally separate regions, the thermal barrier ensuring that the function of the more thermally sensitive semiconductor chip is not impaired by the heat-loss-generating semiconductor chip.

Abstract: An integrated circuit package-in-package system includes: mounting a first integrated circuit device over a substrate; mounting an integrated circuit package system having an inner encapsulation over the first integrated circuit device with a first offset; mounting a second integrated circuit device over the first integrated circuit device and adjacent to the integrated circuit package system; connecting the integrated circuit package system and the substrate; and forming a package encapsulation as a cover for the first integrated circuit device, the integrated circuit package system, and the second integrated circuit device.

Abstract: A TAB tape (100) packaging structure in which (i) the TAB tape (100) including a plurality of semiconductor chips (103) which are fixed, on a film (101) on which wiring patterns are repeatedly provided and (ii) an embossed tape (200) which is electroconductive and has embossed parts (202) which are sequentially provided on a first surface of and in a longitudinal direction of a film (201) are wound on a reel which is electroconductive is arranged such that the TAB tape (100) and the embossed tape (200) are wound on the reel, while (i) a first surface of the film (101) on which surface the plurality of semiconductor chips (103) are fixed and (ii) the first surface of the film (201) on which surface the embossed parts (202) protrude are overlapping and facing each other, and the embossed tape (200) has a total thickness of not less than (t+0.4) mm and not more than 1.1 mm in a case where each of the plurality of semiconductor chips (103) has a thickness of t (0.2?t?0.

Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.

Abstract: A window-type semiconductor package is revealed, primarily comprising a substrate with an interconnection channel, a chip on the substrate, a die-attach adhesive between the chip and the substrate, and an encapsulant filling the interconnection channel. A first solder mask formed on the top surface of the substrate has a specific pattern. The die-attach adhesive bonds the active surface of the chip to the first solder mask with the bonding pads of the chip aligned inside the interconnection channel. The first solder mask has an opening to expose the interconnection channel and further to form an indentation from the interconnection channel to expose the top surface to prevent damaging of the active surface of the chip adjacent to the edges of the interconnection channel to ensure the integrity and yield of the final products.

Abstract: Provided is a resin sealed semiconductor device including: a semiconductor element; a plurality of micro-balls including an internal terminal surface and an external connection electrode in two sides of the micro-balls; metal wires for electrically connecting the semiconductor element and an internal terminal surface; and a sealing body for sealing the semiconductor element, a part of each the plurality of the terminals, and metal wires with a sealing resin, in which a back surface of the semiconductor element is exposed from the sealing body, and a part of each the plurality of micro-balls are exposed as the external connection electrodes from a bottom surface of the sealing body in a projection manner.

Abstract: An electronic-component-housing package comprises a container including a rectangular mount on which an electronic component is to be mounted and a sidewall surrounding the mount. The electronic-component-housing package comprises a lead terminal extending from an inside of a space enclosed by the sidewall to an outside of the space. A tip part of the lead terminal is extending along one side of the mount.

Abstract: The present invention relates to a wafer level package and a method of manufacturing the same. The wafer level package includes a first substrate including a first region and second regions with grooves around the first region; a semiconductor device positioned in the first region; first sealing members positioned in the grooves; a second substrate including projection units corresponding to the second regions in order to form a cavity corresponding to the first region; and second sealing members which are positioned above the projection units and laminate the first and second substrates to each other by being bonded to the first sealing members, and can prevent the sealing members from flowing to any region except for the sealing regions.

Abstract: A MEMS device is described that has a body with a component bonded to the body. The body has a main surface and a side surface adjacent to the main surface and smaller than the main surface. The body is formed of a material and the side surface is formed of the material and the body is in a crystalline structure different from the side surface. The body includes an outlet in the side surface and the component includes an aperture in fluid connection with the outlet.

Abstract: According to an aspect of the present invention, there is provided an electronic apparatus including: a housing; a circuit board that is housed in the housing; a semiconductor package that includes a first surface on which solder balls are provided and a second surface opposite to the first surface and that is mounted on the circuit board so as to be electrically connected to the circuit board through the solder balls; a protective film that has a water repellency and that is applied on the circuit board so as to expose around the semiconductor package mounted on the circuit board; and a joint member that joins at least a part of a side surface of the semiconductor package and the circuit board.